Xi 8088: add the UMB dip switch and allow the programming of the BIOS flash memory

Add create 1.2MB floppy image.
Add missed Zenith Data SupersPort source to compile.

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,38 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior:
+1. Go to '...'
+2. Click on '....'
+3. Scroll down to '....'
+4. See error
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
+
+**Emulator configuration**
+ - Machine: [e.g. IBM AT, AMI 486 clone etc]
+ - CPU:
+ - Graphics/sound cards:
+ - Installed OS
+
+**Host machine**
+ - OS: [e.g. Windows 10, Ubuntu 18.04 etc]
+ - Emulator version
+ - Any other relevant information
+
+**Additional context**
+Add any other context about the problem here.

.github/workflows/c-cpp.yml

@@ -0,0 +1,201 @@
+name: C/C++ CI
+
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+        - name: Ubuntu 64bit (gcc)
+          os: ubuntu-latest
+          args: --enable-networking --enable-release-build CFLAGS="-DPCEM_BUILD_VERSION=${GITHUB_SHA::8}"
+          artifacts_name: PCem-Ubuntu-${{ github.head_ref }}-${{ github.run_number }}
+          artifacts_path: PCem-${{ github.sha }}.tar.bz2
+          installdeps: >-
+            libsdl2-dev
+            libopenal-dev
+            libwxgtk3.0-gtk3-dev
+            libncap-dev
+        - name: Windows 32bits (MSYS2)
+          os: windows-latest
+          compiler: MINGW32
+          args: --enable-networking --enable-release-build CFLAGS="-DPCEM_BUILD_VERSION=${GITHUB_SHA::8}"
+          artifacts_name: PCem-Windows-MINGW32-${{ github.head_ref }}-${{ github.run_number }}
+          artifacts_path: PCem-${{ github.sha }}.zip
+          installdeps: >-
+            base-devel
+            zip
+            unzip
+            mingw-w64-i686-ntldd-git
+            mingw-w64-i686-toolchain 
+            mingw-w64-i686-SDL2 
+            mingw-w64-i686-openal 
+            mingw-w64-i686-wxWidgets
+        - name: Windows 64bits (MSYS2)
+          os: windows-latest
+          compiler: MINGW64
+          args: --enable-networking --enable-release-build CFLAGS="-DPCEM_BUILD_VERSION=${GITHUB_SHA::8}"
+          artifacts_name: PCem-Windows-MINGW64-${{ github.head_ref }}-${{ github.run_number }}
+          artifacts_path: PCem-${{ github.sha }}.zip
+          installdeps: >-
+            base-devel
+            zip
+            unzip
+            mingw-w64-x86_64-ntldd-git
+            mingw-w64-x86_64-toolchain
+            mingw-w64-x86_64-SDL2
+            mingw-w64-x86_64-openal
+            mingw-w64-x86_64-wxWidgets
+
+    runs-on: ${{ matrix.os }}
+    name: ${{ matrix.name }}
+    
+    steps:
+    - uses: actions/checkout@v2
+      with:
+        path: temp
+        fetch-depth: 0
+
+    - name: Setup MSYS2 (Windows)
+      if: runner.os == 'Windows'
+      # You may pin to the exact commit or the version.
+      # uses: msys2/setup-msys2@a43b8403533fffe0c157dd8498f021ddec66bff7
+      uses: msys2/setup-msys2@v2
+      with:
+        # Variant of the environment to set by default: MSYS, MINGW32, MINGW64, UCRT64 or CLANG64
+        msystem: ${{ matrix.compiler }}
+        # Retrieve and extract base installation from upstream GitHub Releases
+        release: false # optional, default is true
+        # Update MSYS2 installation through pacman
+        update: false
+        # Install packages after installation through pacman
+        install: ${{ matrix.installdeps }}
+    - name: npcap download (Windows)
+      if: runner.os == 'Windows'
+      shell: msys2 {0}
+      run: |
+       wget https://nmap.org/npcap/dist/npcap-sdk-1.05.zip
+       unzip -d npcap-sdk-1.05/ npcap-sdk-1.05.zip
+       cd npcap-sdk-1.05
+       cp -r Include/* /mingw32/include/
+       cp -r Include/* /mingw64/include/
+       cp -r Lib/*.lib /mingw32/lib/
+       cp -r Lib/x64/*.lib /mingw64/lib/
+    - name: Setup ubuntu dependencies
+      if: runner.os == 'Linux'
+      run: |
+        sudo apt-get update
+        sudo apt-get install ${{ matrix.installdeps }}
+
+    # Copy all the sources to the dist folder, before we start generating intermediate files.
+    - name: prepare-package (Windows32)
+      if: runner.os == 'Windows' && matrix.compiler == 'MINGW32'
+      shell: msys2 {0}
+      run: |
+        mkdir dist
+        cp -R ./temp/* dist
+        rm -Rf ./dist/.git
+        cp /mingw32/bin/libdeflate.dll dist
+        cp /mingw32/bin/libexpat-1.dll dist
+        cp /mingw32/bin/libgcc_s_dw2-1.dll dist
+        cp /mingw32/bin/libjpeg-8.dll dist
+        cp /mingw32/bin/liblzma-5.dll dist
+        cp /mingw32/bin/libopenal-1.dll dist
+        cp /mingw32/bin/libpng16-16.dll dist
+        cp /mingw32/bin/libstdc++-6.dll dist
+        cp /mingw32/bin/libtiff-5.dll dist
+        cp /mingw32/bin/libwebp-7.dll dist
+        cp /mingw32/bin/libwinpthread-1.dll dist
+        cp /mingw32/bin/libzstd.dll dist
+        cp /mingw32/bin/SDL2.dll dist
+        cp /mingw32/bin/wxbase30u_gcc_custom.dll dist
+        cp /mingw32/bin/wxbase30u_xml_gcc_custom.dll dist
+        cp /mingw32/bin/wxmsw30u_adv_gcc_custom.dll dist
+        cp /mingw32/bin/wxmsw30u_core_gcc_custom.dll dist
+        cp /mingw32/bin/wxmsw30u_html_gcc_custom.dll dist
+        cp /mingw32/bin/wxmsw30u_xrc_gcc_custom.dll dist
+        cp /mingw32/bin/zlib1.dll dist
+    - name: prepare-package (Windows64)
+      if: runner.os == 'Windows' && matrix.compiler == 'MINGW64'
+      shell: msys2 {0}
+      run: |
+        mkdir dist
+        cp -R ./temp/* dist
+        rm -Rf ./dist/.git
+        cp /mingw64/bin/libdeflate.dll dist
+        cp /mingw64/bin/libexpat-1.dll dist
+        cp /mingw64/bin/libgcc_s_seh-1.dll dist
+        cp /mingw64/bin/libjpeg-8.dll dist
+        cp /mingw64/bin/liblzma-5.dll dist
+        cp /mingw64/bin/libopenal-1.dll dist
+        cp /mingw64/bin/libpng16-16.dll dist
+        cp /mingw64/bin/libstdc++-6.dll dist
+        cp /mingw64/bin/libtiff-5.dll dist
+        cp /mingw64/bin/libwebp-7.dll dist
+        cp /mingw64/bin/libwinpthread-1.dll dist
+        cp /mingw64/bin/libzstd.dll dist
+        cp /mingw64/bin/SDL2.dll dist
+        cp /mingw64/bin/wxbase30u_gcc_custom.dll dist
+        cp /mingw64/bin/wxbase30u_xml_gcc_custom.dll dist
+        cp /mingw64/bin/wxmsw30u_adv_gcc_custom.dll dist
+        cp /mingw64/bin/wxmsw30u_core_gcc_custom.dll dist
+        cp /mingw64/bin/wxmsw30u_html_gcc_custom.dll dist
+        cp /mingw64/bin/wxmsw30u_xrc_gcc_custom.dll dist
+        cp /mingw64/bin/zlib1.dll dist
+    - name: configure (Windows)
+      if: runner.os == 'Windows'
+      shell: msys2 {0}
+      run: |
+        cd temp
+        autoreconf -i
+        ./configure ${{ matrix.args }}
+    - name: make (Windows)
+      if: runner.os == 'Windows'
+      shell: msys2 {0}
+      run: |
+        cd temp
+        make -j
+    - name: package (Windows)
+      if: runner.os == 'Windows'
+      shell: msys2 {0}
+      run: |
+        cp ./temp/src/pcem.exe dist
+        cd dist
+        zip -r -9 ${{ matrix.artifacts_path }} *
+
+    - name: prepare-package (Linux)
+      if: runner.os == 'Linux'
+      run: |
+       mkdir dist
+       cp -R ./temp/* dist
+       rm -Rf ./dist/.git
+    - name: configure (Linux)
+      if: runner.os == 'Linux'
+      run: |
+        cd temp
+        autoreconf -i
+        ./configure ${{ matrix.args }}
+    - name: make (Linux)
+      if: runner.os == 'Linux'
+      run: |
+        cd temp
+        make -j
+    - name: package (Linux)
+      if: runner.os == 'Linux'
+      run: |
+       cp ./temp/src/pcem dist
+       cd dist
+       tar -cjf ${{ matrix.artifacts_path }} *
+
+    - name: "Upload GitHub Actions artifacts"
+      uses: actions/upload-artifact@v2
+      with:
+        name: ${{ matrix.artifacts_name }}
+        path: ./dist/${{ matrix.artifacts_path }}
+

.gitignore

@@ -0,0 +1,11 @@
+*.o
+*.swp
+/Makefile
+/src/Makefile
+autom4te.cache
+config.log
+config.status
+.deps
+.dirstamp
+/pcem
+/src/pcem

Makefile.in

@@ -1,7 +1,7 @@
-# Makefile.in generated by automake 1.16.1 from Makefile.am.
+# Makefile.in generated by automake 1.16.3 from Makefile.am.
 # @configure_input@
 
-# Copyright (C) 1994-2018 Free Software Foundation, Inc.
+# Copyright (C) 1994-2020 Free Software Foundation, Inc.
 
 # This Makefile.in is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -196,6 +196,8 @@ am__relativize = \
 DIST_ARCHIVES = $(distdir).tar.gz
 GZIP_ENV = --best
 DIST_TARGETS = dist-gzip
+# Exists only to be overridden by the user if desired.
+AM_DISTCHECK_DVI_TARGET = dvi
 distuninstallcheck_listfiles = find . -type f -print
 am__distuninstallcheck_listfiles = $(distuninstallcheck_listfiles) \
   | sed 's|^\./|$(prefix)/|' | grep -v '$(infodir)/dir$$'
@@ -308,6 +310,7 @@ pdfdir = @pdfdir@
 prefix = @prefix@
 program_transform_name = @program_transform_name@
 psdir = @psdir@
+runstatedir = @runstatedir@
 sbindir = @sbindir@
 sharedstatedir = @sharedstatedir@
 srcdir = @srcdir@
@@ -543,6 +546,10 @@ dist-xz: distdir
 	tardir=$(distdir) && $(am__tar) | XZ_OPT=$${XZ_OPT--e} xz -c >$(distdir).tar.xz
 	$(am__post_remove_distdir)
 
+dist-zstd: distdir
+	tardir=$(distdir) && $(am__tar) | zstd -c $${ZSTD_CLEVEL-$${ZSTD_OPT--19}} >$(distdir).tar.zst
+	$(am__post_remove_distdir)
+
 dist-tarZ: distdir
 	@echo WARNING: "Support for distribution archives compressed with" \
 		       "legacy program 'compress' is deprecated." >&2
@@ -585,6 +592,8 @@ distcheck: dist
 	  eval GZIP= gzip $(GZIP_ENV) -dc $(distdir).shar.gz | unshar ;;\
 	*.zip*) \
 	  unzip $(distdir).zip ;;\
+	*.tar.zst*) \
+	  zstd -dc $(distdir).tar.zst | $(am__untar) ;;\
 	esac
 	chmod -R a-w $(distdir)
 	chmod u+w $(distdir)
@@ -600,7 +609,7 @@ distcheck: dist
 	    $(DISTCHECK_CONFIGURE_FLAGS) \
 	    --srcdir=../.. --prefix="$$dc_install_base" \
 	  && $(MAKE) $(AM_MAKEFLAGS) \
-	  && $(MAKE) $(AM_MAKEFLAGS) dvi \
+	  && $(MAKE) $(AM_MAKEFLAGS) $(AM_DISTCHECK_DVI_TARGET) \
 	  && $(MAKE) $(AM_MAKEFLAGS) check \
 	  && $(MAKE) $(AM_MAKEFLAGS) install \
 	  && $(MAKE) $(AM_MAKEFLAGS) installcheck \
@@ -761,7 +770,7 @@ uninstall-am:
 	am--refresh check check-am clean clean-cscope clean-generic \
 	cscope cscopelist-am ctags ctags-am dist dist-all dist-bzip2 \
 	dist-gzip dist-lzip dist-shar dist-tarZ dist-xz dist-zip \
-	distcheck distclean distclean-generic distclean-tags \
+	dist-zstd distcheck distclean distclean-generic distclean-tags \
 	distcleancheck distdir distuninstallcheck dvi dvi-am html \
 	html-am info info-am install install-am install-data \
 	install-data-am install-dvi install-dvi-am install-exec \

README.md

@@ -0,0 +1,397 @@
+# [PCem](https://pcem-emulator.co.uk/)
+## Download: [Windows](https://pcem-emulator.co.uk/files/PCemV17Win.zip)/[Linux](https://pcem-emulator.co.uk/files/PCemV17Linux.tar.gz)
+
+Latest version: <b>v17</b> [Changelog](https://pcem-emulator.co.uk/index.html)
+
+PCem is licensed under GPL v2.0, see [COPYING](COPYING) for more details.
+
+You can submit patches on our [forum](https://pcem-emulator.co.uk/phpBB3). Before you do, please note the [guidelines](https://pcem-emulator.co.uk/phpBB3/viewtopic.php?f=3&t=5) for submitting patches.
+
+:exclamation: Note: <b>NO COPYRIGHTED ROM FILES ARE INCLUDED NOR WILL THEY BE. PLEASE DO NOT ASK FOR THEM.</b>
+
+## BSD and Linux supplement (v17)
+
+You will need the following libraries (and their dependencies):
+- SDL2
+- wxWidgets 3.x
+- OpenAL
+
+Open a terminal window, navigate to the PCem directory then enter:
+### Linux
+```
+./configure --enable-release-build
+make
+```
+### BSD
+```
+./configure --enable-release-build
+gmake
+```
+
+then `./pcem` to run.
+
+The Linux/BSD versions store BIOS ROM images, configuration files, and other data in `~/.pcem`
+
+configure options are :
+```
+  --enable-release-build : Generate release build. Recommended for regular use.
+  --enable-debug         : Compile with debugging enabled.
+  --enable-networking    : Build with networking support.
+  --enable-alsa          : Build with support for MIDI output through ALSA. Requires libasound.
+```
+
+The menu is a pop-up menu in the Linux/BSD port. Right-click on the main window when mouse is not
+captured.
+
+CD-ROM support currently only accesses `/dev/cdrom`. It has not been heavily tested.
+
+## Links
+
+### PCem emulates the following hardware (as of v17):
+
+Hardware | Links
+--- | ---
+Systems | [8088](#8088-based)<br/>[8086](#8086-based)<br/>[286](#286-based)<br/>[386](#386-based)<br/>[486](#486-based)<br/>[Pentium](#pentium-based)<br/>[Super Socket 7](#super-socket-7-based)
+Graphics | [Basic](#basic-cards)<br/>[Unaccelerated (S)VGA cards](#unaccelerated-svga-cards)<br/>[2D accelerated SVGA cards](#2d-accelerated-svga-cards)<br/>[3D accelerated SVGA cards](#3d-accelerated-svga-cards)<br/>[3D only cards](#3d-only-cards)
+Sound | [Cards](#sound-cards)
+HDD Controller | [Cards](#hdd-controller-cards)
+Misc | [Cards](#misc-cards)
+
+### [Software Tested](TESTED.md) (list)
+- [DOS](TESTED.md#dos)<br/>
+- [Windows](TESTED.md#windows)<br/>
+- [Windows NT](TESTED.md#windows-nt)<br/>
+- [OS/2](TESTED.md#os2)<br/>
+- [Linux](TESTED.md#linux)<br/>
+- [Applications](TESTED.md#applications)<br/>
+- [Games](TESTED.md#games)<br/>
+- [Demos](TESTED.md#demos)<br/>
+- [Emulators](TESTED.md#emulators)<br/>
+
+<hr>
+
+## Systems
+
+### 8088 based
+Release | Machine | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | ---
+1981 | <b>IBM PC</b><br/>8088 at 4.77 MHz<br/>16KB - 640KB RAM (min. 64KB) | ibmpc/pc102782.bin<br/>ibmpc/basicc11.f6<br/>ibmpc/basicc11.f8<br/>ibmpc/basicc11.fa<br/>ibmpc/basicc11.fc
+1983 | <b>Compaq Portable Plus</b><br/>8088 at 4.77 MHz<br/>128KB - 640KB RAM | compaq_pip/Compaq Portable Plus 100666-001 Rev C.bin
+1983 | <b>IBM XT</b><br/>8088 at 4.77 MHz<br/>64KB - 640KB RAM | ibmxt/5000027.u19<br/>ibmxt/1501512.u18
+1983 | <b>Leading Edge Model M</b><br/>8088 at 7.16 MHz<br/>128KB - 704KB RAM | leadingedge_modelm/Leading Edge - Model M - BIOS ROM - Version 4.71.bin
+1984 | <b>IBM PCjr</b> <i>[[5]](#system-note-5)</i><br/>8088 at 4.77 MHz<br/>64KB - 640KB RAM (min. 128KB)<br/>Built-in 16 colour graphics<br/>3 voice sound<br/>Not generally PC compatible. | ibmpcjr/bios.rom
+1984 | <b>Tandy 1000</b> <i>[[5]](#system-note-5)</i><br/>8088 at 4.77 MHz<br/>128KB - 640KB RAM<br/>Built-in 16 colour graphics<br/>3 voice sound | tandy/tandy1t1.020
+1985 | <b>NCR PC4i</b><br/>8088 at 4.77 MHz<br/>256KB - 640KB RAM | ncr_pc4i/NCR_PC4i_BIOSROM_1985.BIN
+1986 | <b>DTK Clone XT</b><br/>8088 at 8/10 MHz<br/>64KB - 640KB RAM | dtk/dtk_erso_2.42_2764.bin
+1986 | <b>Phoenix XT clone</b><br/>8088 at 8/10 MHz<br/>64KB - 640KB RAM | pxxt/000p001.bin
+1987 | <b>Tandy 1000HX</b><br/>8088 at 7.16 MHz<br/>256KB - 640KB RAM<br/>Built-in 16 colour graphics<br/>3 voice sound<br/>Has DOS 2.11 in ROM | tandy1000hx/v020000.u12
+1987 | <b>Thomson TO16 PC</b><br/>8088 at 9.54 MHz<br/>512KB - 640KB RAM | to16_pc/TO16_103.bin
+1987 | <b>Toshiba T1000</b> <i>[[1]](#system-note-1)</i> <i>[[5]](#system-note-5)</i><br/>8088 at 4.77 MHz<br/>512KB - 1024KB RAM<br/>CGA on built-in LCD | t1000/t1000.rom<br/>t1000/t1000font.rom
+1987 | <b>VTech Laser Turbo XT</b><br/>8088 at 10 MHz<br/>640KB RAM | ltxt/27c64.bin
+1987 | <b>Zenith Data SupersPort</b><br/>8088 at 8 MHz<br/>128KB - 640KB RAM<br/>Built-in LCD video is not currently emulated | zdsupers/z184m v3.1d.10d
+1988? | <b>&#169;Anonymous Generic Turbo XT BIOS</b><br/>8088 at 8+ MHz<br/>64KB - 640KB RAM | genxt/pcxt.rom
+1988 | <b>Atari PC3</b><br/>8088 at 8 MHz<br/>640KB RAM | ataripc3/AWARD_ATARI_PC_BIOS_3.08.BIN
+1988 | <b>Juko XT clone</b> | jukopc/000o001.bin
+1988 | <b>Schneider Euro PC</b><br/>8088 at 9.54 MHz<br/>512KB - 640KB RAM | europc/50145<br/>europc/50146
+1989 | <b>AMI XT clone</b><br/>8088 at 8+ MHz<br/>64KB - 640KB RAM | amixt/ami_8088_bios_31jan89.bin
+2015 | <b>Xi8088</b><br/>8088 at 4.77-13.33 MHz<br/>640KB RAM | xi8088/bios-xi8088.bin
+
+### 8086 based
+Release | Machine | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | ---
+1984 | <b>Compaq Deskpro</b><br/>8086 at 8 MHz<br/>128KB - 640KB RAM | deskpro/Compaq - BIOS - Revision J - 106265-002.bin
+1984 | <b>Olivetti M24</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>128KB - 640KB RAM<br/>Built-in enhanced CGA (supports 640x400x2) | olivetti_m24/olivetti_m24_version_1.43_low.bin<br/>olivetti_m24/olivetti_m24_version_1.43_high.bin
+1986 | <b>Amstrad PC1512</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>512KB - 640KB RAM<br/>Enhanced CGA (supports 640x200x16)<br/>Custom mouse port | pc1512/40043.v1<br/>pc1512/40044.v2<br/>pc1512/40078.ic127
+1987 | <b>Amstrad PC1640</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>640KB RAM<br/>Built-in Paradise EGA<br/>Custom mouse port | pc1640/40043.v3<br/>pc1640/40044.v3<br/>pc1640/40100
+1987 | <b>Toshiba T1200</b> <i>[[1]](#system-note-1)</i> <i>[[5]](#system-note-5)</i><br/>8086 at 9.54 MHz<br/>1MB - 2MB RAM<br/>CGA on built-in LCD | t1200/t1200_019e.ic15.bin<br/>t1200/t1000font.rom
+1988 | <b>Amstrad PPC512/640</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>512KB - 640KB RAM<br/>Built-in CGA w/ plasma display | ppc512/40107.v2<br/>ppc512/40108.v2<br/>ppc512/40109.bin
+1988 | <b>Sinclair PC200/Amstrad PC20</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>512KB - 640KB RAM<br/>Built-in CGA (supports TV-out 50hz PAL) | pc200/pc20v2.0<br/>pc200/pc20v2.1<br/>pc200/40109.bin
+1988 | <b>VTech Laser XT3</b><br/>8086 at 10 MHz<br/>512KB - 1152KB RAM | lxt3/27c64d.bin
+1989 | <b>Amstrad PC2086</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>640KB RAM<br/>Built-in VGA | pc2086/40179.ic129<br/>pc2086/40180.ic132<br/>pc2086/40186.ic171
+1989 | <b>Tandy 1000SL/2</b> <i>[[5]](#system-note-5)</i><br/>8086 at 9.54 MHz<br/>512KB - 768KB RAM<br/>Built-in 16 colour graphics<br/>4 voice sound | tandy1000sl2/8079047.hu1<br/>tandy1000sl2/8079048.hu2
+1990 | <b>Amstrad PC3086</b> <i>[[5]](#system-note-5)</i><br/>8086 at 8 MHz<br/>640KB RAM<br/>Built-in VGA | pc3086/fc00.bin<br/>pc3086/c000.bin
+1991 | <b>Amstrad PC5086</b><br/>8086 at 8 MHz<br/>640KB RAM | pc5086/sys_rom.bin
+
+### 286 based
+Release | Machine | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | ---
+1984 | <b>IBM AT</b><br/>286 at 6 or 8 MHz<br/>256KB - 16MB RAM | ibmat/at111585.0<br/>ibmat/at111585.1
+1986 | <b>Compaq Portable II</b><br/>286 at 8 MHz<br/>256KB - 15MB RAM | compaq_pii/109739-001.rom<br/>compaq_pii/109740-001.rom
+1986 | <b>IBM XT Model 286</b><br/>286 at 6 MHz<br/>256KB - 16MB RAM | ibmxt286/BIOS_5162_21APR86_U34_78X7460_27256.BIN<br/>ibmxt286/BIOS_5162_21APR86_U35_78X7461_27256.BIN
+1986 | <b>Toshiba T3100e</b> <i>[[1]](#system-note-1)</i> <i>[[5]](#system-note-5)</i><br/>286 at 12 MHz<br/>1MB - 5MB RAM<br/>CGA on gas-plasma display | t3100e/t3100e_font.bin<br/>t3100e/t3100e.rom
+1987 | <b>IBM PS/2 Model 50</b> <i>[[5]](#system-note-5)</i><br/>286 at 10 MHz<br/>1MB - 16MB RAM<br/>Built-in VGA<br/>MCA bus | i8550021/90x7420.zm13<br/>i8550021/90x7423.zm14<br/>i8550021/90x7426.zm16<br/>i8550021/90x7429.zm18
+1988 | <b>Bull Micral 45</b><br/>286 at 12 MHz<br/>1MB - 6MB RAM | bull_micral_45/even.fil<br/>bull_micral_45/odd.fil
+1988 | <b>Commodore PC30-III</b><br/>286 at 12 MHz<br/>512KB - 16MB RAM | cmdpc30/commodore pc 30 iii even.bin<br/>cmdpc30/commodore pc 30 iii odd.bin
+1988 | <b>IBM PS/2 Model 30-286</b><br/>286 at 10 MHz<br/>1MB - 16MB RAM<br/>Built-in VGA<br/>MCA bus | ibmps2_m30_286/33f5381a.bin
+1989 | <b>Epson PC AX</b><br/>286<br/>256KB - 16MB RAM | epson_pcax/EVAX<br/>epson_pcax/ODAX
+1989 | <b>Epson PC AX2e</b><br/>286 at 12 MHz<br/>256KB - 16MB RAM | epson_pcax2e/EVAX<br/>epson_pcax2e/ODAX
+1990 | <b>AMI 286 clone</b><br/>286 at 8+ MHz<br/>512KB - 16MB RAM | ami286/amic206.bin
+1990 | <b>Award 286 clone</b><br/>286 at 8+ MHz<br/>512KB - 16MB RAM | award286/award.bin
+1990 | <b>Dell System 200</b><br/>286 at 12 MHz<br/>640KB - 16MB RAM | dells200/dell0.bin<br/>dells200/dell1.bin
+1990 | <b>IBM PS/1 Model 2011</b> <i>[[5]](#system-note-5)</i><br/>286 at 10 MHz<br/>512KB - 16MB RAM<br/>Built-in VGA<br/>DOS 4.01 + GUI menu system in ROM | ibmps1/f80000.bin
+? | <b>Goldstar GDC-212M</b><br/>286 at 12 MHz<br/>512KB - 4MB RAM | gdc212m/gdc212m_72h.bin
+? | <b>GW-286CT GEAR</b><br/>286 at 8+ MHz<br/>512KB - 16MB RAM | gw286ct/2ctc001.bin
+? | <b>Hyundai Super-286TR</b><br/>286 at 12 MHz<br/>1MB - 4MB RAM | super286tr/award.bin
+? | <b>Samsung SPC-4200P</b><br/>286 at 12 MHz<br/>512KB - 2MB RAM | spc4200p/u8.01
+? | <b>Samsung SPC-4216P</b><br/>286 at 12 MHz<br/>1MB - 5MB RAM | spc4216p/phoenix.bin<br/>&nbsp;&nbsp;&nbsp;<i>or</i><br/>spc4216p/7101.u8<br/>spc4216p/ac64.u10
+? | <b>Samsung SPC-4620P</b><br/>286 at 12 MHz<br/>1MB - 5MB RAM<br/>Built-in Korean ATI-28800 | spc4620p/31005h.u8<br/>spc4620p/31005h.u10<br/>spc4620p/svb6120a_font.rom<br/>spc4620p/31005h.u8<br/>spc4620p/31005h.u10
+? | <b>Tulip AT Compact</b><br/>286<br/>640KB - 16MB RAM | tulip_tc7/tc7be.bin<br/>tulip_tc7/tc7bo.bin
+
+### 386 based
+Release | Machine | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | ---
+1987 | <b>IBM PS/2 Model 80</b> <i>[[5]](#system-note-5)</i><br/>386DX at 20 MHz<br/>1MB - 12MB RAM<br/>Built-in VGA<br/>MCA bus | i8580111/15f6637.bin<br/>i8580111/15f6639.bin
+1988 | <b>ECS 386/32</b><br/>386DX at 20 MHz<br/>1MB - 16MB RAM | ecs386_32/386_32_even.bin<br/>ecs386_32/386_32_odd.bin
+1989 | <b>IBM PS/2 Model 70 (type 3)</b> <i>[[5]](#system-note-5)</i><br/>386DX at 25 MHz<br/>2MB - 16MB RAM<br/>Built-in VGA<br/>MCA bus | ibmps2_m70_type3/70-a_even.bin<br/>ibmps2_m70_type3/70-a_odd.bin
+1989 | <b>Compaq Deskpro 386</b><br/>386DX at 20 MHz<br/>1MB - 15MB RAM | deskpro386/109592-005.u11.bin<br/>deskpro386/109591-005.u13.bin
+1989 | <b>Epson PC AX3</b><br/>386SX at 16 MHz<br/>256KB - 16MB RAM | epson_pcax3/EVAX3<br/>epson_pcax3/ODAX3
+1989 | <b>IBM PS/2 Model 55SX</b><br/>386SX at 16 MHz<br/>1MB - 8MB RAM<br/>Built-in VGA<br/>MCA bus | i8555081/33f8146.zm41<br/>i8555081/33f8145.zm40
+1990 | <b>DTK 386SX clone</b><br/>386SX<br/>512KB - 16MB RAM | dtk386/3cto001.bin
+1990 | <b>IBM PS/1 Model 2121</b> <i>[[5]](#system-note-5)</i><br/>386SX at 20 MHz<br/>1MB - 16MB RAM<br/>Built-in VGA | ibmps1_2121/fc0000.bin
+1990 | <b>Samsung SPC-6000A</b><br/>386DX<br/>1MB - 32 MB RAM | spc6000a/3c80.u27<br/>spc6000a/9f80.u26
+1992 | <b>Acermate 386SX/25N</b> <i>[[5]](#system-note-5)</i><br/>386SX at 25 MHz<br/>2MB - 16MB RAM<br/>Built-in Oak SVGA | acer386/acer386.bin<br/>acer386/oti067.bin
+1992 | <b>Amstrad MegaPC</b> <i>[[2]](#system-note-2)</i> <i>[[5]](#system-note-5)</i><br/>386SX at 25 MHz<br/>1MB - 16MB RAM<br/>Built-in VGA<br/> | megapc/41651-bios lo.u18<br/>megapc/211253-bios hi.u19
+1992 | <b>Commodore SL386SX-25</b> <i>[[5]](#system-note-5)</i><br/>386SX at 25 MHz<br/>1MB - 16MB RAM<br/>Built-in AVGA2 | cbm_sl386sx25/f000.bin<br/>cbm_sl386sx25/c000.bin
+1992 | <b>Packard Bell Legend 300SX</b><br/>386SX at 16 MHz<br/>1MB - 16MB RAM | pb_l300sx/pb_l300sx.bin
+1992 | <b>Samsung SPC-6033P</b><br/>386SX at 33 MHz<br/>2MB - 12 MB RAM | spc6033p/phoenix.bin<br/>spc6033p/svb6120a_font.rom
+1994 | <b>AMI 386DX clone</b><br/>386DX at 40 MHz<br/>1MB - 32MB RAM | ami386dx/opt495sx.ami
+1994 | <b>AMI 386SX clone</b><br/>386SX at 25 MHz<br/>1MB - 16MB RAM | ami386/ami386.bin
+1994 | <b>MR 386DX clone</b><br/>This is a generic 386DX clone with an MR BIOS | mr386dx/opt495sx.mr
+? | <b>KMX-C-02</b><br/>386SX<br/>512KB - 16MB RAM | kmxc02/3ctm005.bin
+
+### 486 based
+Release | Machine<br/>(+ addl. hardware) | CPU(s) Supported | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ---
+1990 | <b>IBM PS/2 Model 70 (type 4)</b> <i>[[3]](#system-note-3)</i><br/>2MB - 16MB RAM<br/>Built-in VGA<br/>MCA bus | <b>486DX</b> at 25 MHz | ibmps2_m70_type3/70-a_even.bin<br/>ibmps2_m70_type3/70-a_odd.bin
+1993 | <b>AMI 486 clone</b><br/>1MB - 32MB RAM | <b>486</b> at 16-66 MHz | ami486/ami486.bin
+1993 | <b>Elonex PC-425X</b> <i>[[5]](#system-note-5)</i><br/>1MB - 256MB RAM<br/>Built-in Trident TGUI9440CXi | <b>486SX</b> at 25 MHz | elx_pc425x/elx_pc425x.bin<br/>&nbsp;&nbsp;&nbsp;<i>or</i><br/>elx_pc425x/elx_pc425x_bios.bin<br/>elx_pc425x/elx_pc425x_vbios.bin
+1993 | <b>IBM PS/1 Model 2133 (EMEA 451)</b><br/>2MB - 64MB RAM<br/>Built-in Cirrus Logic GD5426 | <b>486SX</b> at 25 MHz | ibmps1_2133/PS1_2133_52G2974_ROM.bin
+1993 | <b>Packard Bell PB410A</b> <i>[[5]](#system-note-5)</i><br/>1MB - 64MB RAM<br/>Built-in HT-216 video | <b>486</b> at 25-120 MHz<br/><b>Am5x86</b> at 133-160 MHz<br/><b>Cx5x86</b> at 100-133 MHz<br/><b>Pentium Overdrive</b> at 63-83 MHz | pb410a/PB410A.080337.4ABF.U25.bin
+1994 | <b>AMI WinBIOS 486 clone</b><br/>1MB - 32MB RAM | <b>486</b> at 16-66 MHz | win486/ali1429g.amw
+1995 | <b>Award SiS 496/497</b><br/>1MB - 64MB RAM | <b>486</b> at 16-120 MHz<br/><b>Am5x86</b> at 133-160 MHz<br/><b>Cx5x86</b> at 100-133 MHz<br/><b>Pentium Overdrive</b> at 63-83 MHz | sis496/sis496-1.awa
+
+### Pentium based
+Release | Machine<br/>(+ addl. hardware) | CPU(s) Supported | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ---
+1994 | <b>Intel Premiere/PCI (Batman's Revenge)</b><br/>1MB - 128MB RAM | <b>Pentium</b> at 60-66 MHz<br/><b>Pentium Overdrive</b> at 120-133 MHz | revenge/1009af2_.bi0<br/>revenge/1009af2_.bi1
+1995 | <b>Intel Advanced/EV (Endeavor)</b> <i>[[4]](#system-note-4)</i><br/>1MB - 128MB RAM | <b>Pentium</b> at 75-133 MHz<br/><b>Pentium Overdrive</b> at 125-200 MHz | endeavor/1006cb0_.bi0<br/>endeavor/1006cb0_.bi1
+1995 | <b>Intel Advanced/ZP (Zappa)</b><br/>1MB - 128MB RAM | <b>Pentium</b> at 75-133 MHz<br/><b>Pentium Overdrive</b> at 125-200 MHz | zappa/1006bs0_.bio<br/>zappa/1006bs0_.bi1
+1995 | <b>Packard Bell PB520R (Robin LC)</b> <i>[[5]](#system-note-5)</i><br/>1MB - 128MB RAM<br/>Built-in Cirrus Logic GD-5434 | <b>Pentium</b> at 60-66 MHz<br/><b>Pentium Overdrive</b> at 120-133 MHz | pb520r/1009bc0r.bio<br/>pb520r/1009bc0r.bi1<br/>pb520r/gd5434.bin
+1995 | <b>Packard Bell PB570 (Hillary)</b> <i>[[5]](#system-note-5)</i><br/>1MB - 128MB RAM<br/>Built-in Cirrus Logic GD-5430 | <b>Pentium</b> at 75-133 MHz<br/><b>Pentium Overdrive</b> at 125-200 MHz | pb570/1007by0r.bio<br/>pb570/1007by0r.bi1<br/>pb570/gd5430.bin
+1996 | <b>ASUS P/I-P55TVP4</b><br/>1MB - 128MB RAM | <b>Pentium</b> at 75-200 MHz<br/><b>Pentium MMX</b> at 166-233 MHz<br/><b>Mobile Pentium MMX</b> at 120-300 MHz<br/><b>Cyrix 6x86</b> at PR90<i>(80 MHz)</i>-PR200<i>(200 MHz)</i><br/><b>Cyrix 6x86MX/MII</b> at PR166<i>(133 MHz)</i>-PR400<i>(285 MHz)</i><br/><b>IDT WinChip</b> at 75-240 MHz<br/><b>IDT Winchip 2</b> at 200-240 MHz<br/><b>IDT Winchip 2A</b> at 200-233 MHz<br/><b>AMD K6</b> at 166-300 MHz<br/><b>AMD K6-2</b> <i>(AFR-66)</i> at 233-300 MHz | p55tvp4/tv5i0204.awd
+1996 | <b>ASUS P/I-P55T2P4</b><br/>1MB - 512MB RAM | <b>Pentium</b> at 75-200 MHz<br/><b>Pentium MMX</b> at 166-233 MHz<br/><b>Mobile Pentium MMX</b> at 120-300 MHz<br/><b>Cyrix 6x86</b> at PR90<i>(80 MHz)</i>-PR200<i>(200 MHz)</i><br/><b>Cyrix 6x86MX/MII</b> at PR166<i>(133 MHz)</i>-PR400<i>(285 MHz)</i><br/><b>IDT WinChip</b> at 75-240 MHz<br/><b>IDT Winchip 2</b> at 200-240 MHz<br/><b>IDT Winchip 2A</b> at 200-233 MHz<br/><b>AMD K6</b> at 166-300 MHz<br/><b>AMD K6-2</b> <i>(AFR-66)</i> at 233-300 MHz | p55t2p4/0207_j2.bin
+1996 | <b>Award 430VX PCI</b><br/>1MB - 128MB RAM | <b>Pentium</b> at 75-200 MHz<br/><b>Pentium MMX</b> at 166-233 MHz<br/><b>Mobile Pentium MMX</b> at 120-300 MHz<br/><b>Cyrix 6x86</b> at PR90<i>(80 MHz)</i>-PR200<i>(200 MHz)</i><br/><b>Cyrix 6x86MX/MII</b> at PR166<i>(133 MHz)</i>-PR400<i>(285 MHz)</i><br/><b>IDT WinChip</b> at 75-240 MHz<br/><b>IDT Winchip 2</b> at 200-240 MHz<br/><b>IDT Winchip 2A</b> at 200-233 MHz<br/><b>AMD K6</b> at 166-300 MHz<br/><b>AMD K6-2</b> <i>(AFR-66)</i> at 233-300 MHz | 430vx/55xwuq0e.bin
+1996 | <b>Itautec Infoway Multimidia</b><br/>8MB - 128MB RAM | <b>Pentium</b> at 75-133 MHz<br/><b>Pentium Overdrive</b> at 125-200 MHz | infowaym/1006bs0_.bio<br/>infowaym/1006bs0_.bi1
+1997 | <b>Epox P55-VA</b><br/>1MB - 128MB RAM | <b>Pentium</b> at 75-200 MHz<br/><b>Pentium MMX</b> at 166-233 MHz<br/><b>Mobile Pentium MMX</b> at 120-300 MHz<br/><b>Cyrix 6x86</b> at PR90<i>(80 MHz)</i>-PR200<i>(200 MHz)</i><br/><b>Cyrix 6x86MX/MII</b> at PR166<i>(133 MHz)</i>-PR400<i>(285 MHz)</i><br/><b>IDT WinChip</b> at 75-240 MHz<br/><b>IDT Winchip 2</b> at 200-240 MHz<br/><b>IDT Winchip 2A</b> at 200-233 MHz<br/><b>AMD K6</b> at 166-300 MHz<br/><b>AMD K6-2</b> <i>(AFR-66)</i> at 233-300 MHz | p55va/va021297.bin
+
+### Super Socket 7 based
+Release | Machine<br/>(+ addl. hardware) | CPU(s) Supported | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ---
+1998 | <b>FIC VA-503+</b><br/>1MB - 512MB RAM | <b>AMD K6</b> at 166-300 MHz<br/><b>AMD K6-2</b> at 233-550 MHz<br/><b>AMD K6-2+</b> at 450-550 MHz<br/><b>AMD K6-III</b> at 400-450 MHz<br/><b>AMD K6-III+</b> at 400-500 MHz<br/><b>Pentium</b> at 75-200 MHz<br/><b>Pentium MMX</b> at 166-233 MHz<br/><b>Mobile Pentium MMX</b> at 120-300 MHz<br/><b>Cyrix 6x86</b> at PR90<i>(80 MHz)</i>-PR200<i>(200 MHz)</i><br/><b>Cyrix 6x86MX/MII</b> at PR166<i>(133 MHz)</i>-PR400<i>(285 MHz)</i><br/><b>IDT WinChip</b> at 75-240 MHz<br/><b>IDT WinChip2</b> at 200-250 MHz<br/><b>IDT Winchip 2A</b> at PR200<i>(200 MHz)</i>-PR300<i>(250 MHz)</i> | fic_va503p/je4333.bin
+
+### Socket 8 based
+Release | Machine<br/>(+ addl. hardware) | CPU(s) Supported | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ---
+1996 | <b>Intel VS440FX</b><br/>8MB - 256 MB RAM | <b>Pentium Pro</b> at 150-200 MHz<br/><b>Pentium II Overdrive</b> at 300-333 MHz | vs440fx/1018CS1_.BI1<br/>vs440fx/1018CS1_.BI2<br/>vs440fx/1018CS1_.BI3<br/>vs440fx/1018CS1_.BIO<br/>vs440fx/1018CS1_.RCV
+
+### Slot 1 based
+Release | Machine<br/>(+ addl. hardware) | CPU(s) Supported | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ---
+1998 | <b>Gigabyte GA-686BX</b><br/>8MB - 512MB RAM | <b>Pentium II</b> at 233-450 MHz<br/><b>Celeron</b> at 266-533 MHz<br/><b>Cyrix III</b>at 500 MHz | ga686bx/6BX.F2a
+
+#### Additional Notes
+<a name="system-note-1">`[1]`</a> <b>Toshiba Button Mapping</b>:
+PCem maps [Fn] to `right-Ctrl` and `right-Alt`. The following functions are supported:
+Key Combo | Function
+---|---
+Fn + Num Lock | toggle numpad
+Fn + Home | Internal LCD display
+Fn + Page Down | Turbo on
+Fn + Right | Toggle LCD font
+Fn + End | External CRT display
+Fn + SysRQ | Toggle window
+
+<a name="system-note-2">`[2]`</a> <b>Amstrad MegaPC</b> <i>(386SX)</i>: The original machine had a built-in Sega MegaDrive. This is not emulated in PCem.
+
+<a name="system-note-3">`[3]`</a> <b>IBM PS/2 Model 70 (type 4)</b> <i>(486DX)</i>: PCem's FPU emulation is not bit accurate and can not pass IBM's floating point tests. As a result, this machine will always print 12903 and 162 errors on bootup. These can be ignored - F1 will boot the machine.
+
+<a name="system-note-4">`[4]`</a> <b>Intel Advanced/EV (Endeavor)</b> <i>(Pentium)</i>: The real board has a Sound Blaster 16 onboard and optionally an S3 Trio64V+. Neither are emulated as onboard devices.
+
+<a name="system-note-5">`[5]`</a> Some systems have fixed graphics adapters:<br/>
+<i>** = Can use external video card.</i><br/>
+
+System | Graphics | Addl. Info | **
+--- | --- | --- | :-:
+<b>Amstrad MegaPC</b> | Paradise 90C11 | A development of the PVGA1 with 512KB VRAM | &#10004;
+<b>Acer 386SX/25N</b> | Oak OTI-067 | Another 512KB SVGA clone | &#10004;
+<b>Amstrad PC1512</b> | CGA | Has a new mode (640x200x16) | X
+<b>Amstrad PC1640</b> | Paradise EGA | &nbsp; | &#10004;
+<b>Amstrad PC2086/PC3086</b> | Paradise PVGA1 | An early SVGA clone with 256KB VRAM | &#10004;
+<b>Amstrad PPC512/640</b> | CGA/MDA | Outputs to 640x200 plasma display | &#10004;
+<b>Commodore SL386SX-25</b> | AVGA2 | 256KB - 512KB VRAM | X
+<b>Elonex PC-425X</b> | Trident TGUI9400CXi | 512KB VRAM | X
+<b>IBM PCjr</b> | CGA | Has various new modes: <br/>160x200 x 16<br/>320x200 x 16<br/>640x200 x 4 | X
+<b>IBM PS/1 Model 2011</b> | Stock VGA | 256KB VRAM | X
+<b>IBM PS/1 Model 2121</b> | Basic (and unknown) SVGA | 256KB VRAM | X
+<b>IBM PS/2 machines</b> | Stock VGA | 256KB VRAM | X
+<b>Olivetti M24</b> <i>[[6]](#system-note-6)</i>| CGA | Has double-res text modes + 640x400 mode | X
+<b>Packard Bell PB410A</b> | Headland HT-216 | &nbsp; | &#10004;
+<b>Packard Bell PB520R</b> | Cirrus Logic GD-5434 | &nbsp; | &#10004;
+<b>Packard Bell PB570</b> | Cirrus Logic GD-5430 | &nbsp; | &#10004;
+<b>Sinclair PC200</b> | CGA | Can output to TV @ 50hz (UK) | &#10004;
+<b>Tandy 1000</b> | Clone of PCjr video | Widely supported in 80s games | X
+<b>Tandy 1000 SL/2</b> | Improved Tandy 1000 | Has support for 640x200x16 | X
+<b>Toshiba T-series</b> | CGA | Outputs to built-in LCD or plasma display | X
+
+<a name="system-note-6">`[6]`</a> <b>Olivetti M24 (display)</b>: I haven't seen a dump of the font ROM for this yet, so if one is not provided the MDA font will be used - which looks slightly odd as it is 14-line instead of 16-line.
+
+<hr>
+
+## Graphics Cards
+
+### Basic cards
+Hardware | Addl. Info | ROM file needed<br/>(within ./roms/ folder)
+--- | --- | ---
+<b>MDA</b> <i>(1981)</i> | 80x25 monochrome text | <i>(none)</i>
+<b>CGA</b> <i>(1981)</i> | 40x25 and 80x25 text<br/>320x200 in 4 colours<br/>620x200 in 2 colours<br/>Supports composite output for ~16 colours. | <i>(none)</i>
+<b>Hercules</b> <i>(1982)</i> | 80x25 monochrome text<br/>720x348 in monochrome | <i>(none)</i>
+<b>Plantronics ColorPlus</b> | An enhanced CGA board with support for 320x200x16 and 640x200x4 | <i>(none)</i>
+<b>Wyse WY-700</b> | A CGA-compatible board with support for a 1280x800 mode | <i>(none)</i>
+<b>MDSI Genius</b> | Mono portrait board with support for a 728x1008 mode | 8x12.bin
+<b>IBM EGA</b> <i>(1984)</i> | Text up to 80x43<br/>Graphics up to 640x350 in 16 colours | ibm_6277356_ega_card_u44_27128.bin
+<b>ATI EGA Wonder 800+</b> | An enhanced EGA-compatible board with support for up to 800x600 in 16 colours | ATI EGA Wonder 800+ N1.00.BIN
+<b>Hercules InColor</b> | An enhanced Hercules with a custom 720x350 16 colour mode | <i>(none)</i>
+
+### Unaccelerated (S)VGA cards
+Hardware | Addl. Info | ROM file needed<br/>(within ./roms/ folder)
+--- | --- | ---
+<b>ATI Korean VGA</b> | ATI-28800 based.<br/>512KB VRAM<br/>Supports up to 8-bit colour<br/>Korean font support | atikorvga.bin<br/>ati_ksc5601.rom
+<b>ATI VGA Edge-16</b> | ATI-18800 based<br/>512KB VRAM<br/>Supports up to 8-bit colour | vgaedge16.vbi
+<b>ATI VGA Charger</b> | ATI-28800 based<br/>512KB VRAM<br/>Supports up to 8-bit colour | bios.bin
+<b>AVGA2</b> | Also known as Cirrus Logic GD5402<br/>256KB - 512KB VRAM<br/>Supports up to 8-bit colour | avga2vram.vbi
+<b>IBM VGA</b> <i>(1987)</i> | 256KB VRAM<br/>Text up to 80x50<br/>Graphics up to 320x200 in 256 colours or 640x480 in 16 colours | ibm_vga.bin
+<b>Kasan Hangulmadang-16</b> | ET4000AX based<br/>1MB VRAM<br/>Supports up to 8-bit colour<br/>Korean font support | et4000_kasan16.bin<br/>kasan_ksc5601.rom
+<b>OAK OTI-037C</b> | 256KB VRAM<br/>Supports up to 8-bit colour | oti037/bios.bin
+<b>OAK OTI-067</b> | 256KB - 512KB VRAM<br/>Supports up to 8-bit colour | oti067/bios.bin
+<b>Olivetti GO481 (Paradise PVGA1A)</b> | 256KB VRAM<br/>Supports up to 8-bit colour | oli_go481_lo.bin<br/>oli_go481_hi.bin
+<b>Trident 8900D SVGA</b> | 256KB - 1MB VRAM<br/>Supports up to 24-bit colour | trident.bin
+<b>Trident 9000B SVGA</b> | 512KB VRAM<br/>Supports up to 8-bit colour | tvga9000b/BIOS.BIN
+<b>Trident TGUI9400CXi</b> | 1MB - 2MB VRAM<br/>Supports up to 24-bit colour | 9440.vbi
+<b>Trigem Korean VGA</b> | ET4000AX based<br/>1MB VRAM<br/>Supports up to 8-bit colour<br/>Korean font support | tgkorvga.bin<br/>tg_ksc5601.rom
+<b>Tseng ET4000AX SVGA</b> | 1MB VRAM<br/>Supports up to 8-bit colour | et4000.bin
+
+### 2D Accelerated SVGA cards
+Hardware | Addl. Info | ROM file needed<br/>(within ./roms/ folder)
+--- | --- | ---
+<b>ATI Graphics Pro Turbo</b> | Mach64GX based<br/>1MB - 4MB VRAM | mach64gx/bios.bin
+<b>ATI Video Xpression</b> | Mach64VT2 based<br/>2MB - 4MB VRAM<br/>Has video acceleration | atimach64vt2pci.bin
+<b>Cirrus Logic GD-5428</b> | 1MB - 2MB VRAM | Machspeed_VGA_GUI_2100_VLB.vbi
+<b>Cirrus Logic GD-5429</b> | 1MB - 2MB VRAM | 5429.vbi
+<b>Cirrus Logic GD-5430</b> | 1MB - 2MB VRAM | gd5430/pci.bin
+<b>Cirrus Logic GD-5434</b> <i>[[1]](#graphics-note-1)</i> | 2MB - 4MB VRAM | gd5434.bin
+<b>Diamond Stealth 32 SVGA</b> | ET4000/W32p based<br/>1MB - 2MB VRAM | et4000w32.bin
+<b>IBM 1MB SVGA Adapter/A</b> | Cirrus Logic GD5428 based<br/>1 MB VRAM<br/>Only supported on PS/2 models | SVGA141.ROM
+<b>Number Nine 9FX</b> | S3 Trio64 based<br/>1MB - 2MB VRAM | s3_764.bin
+<b>Paradise Bahamas 64</b> | S3 Vision864 based<br/>1MB - 4MB VRAM | bahamas64.bin
+<b>Phoenix S3 Trio32</b> | S3 Trio32 based<br/>512KB - 2MB VRAM | 86c732p.bin
+<b>Phoenix S3 Trio64</b> | S3 Trio64 based<br/>1MB - 4MB VRAM | 86c764x1.bin
+<b>Trident TGUI9440</b> | 1MB - 2MB VRAM | 9440.vbi
+
+### 3D Accelerated SVGA cards
+Hardware | Addl. Info | ROM file needed<br/>(within ./roms/ folder)
+--- | --- | ---
+<b>3DFX Voodoo Banshee (reference)</b> | Voodoo Banshee based<br/>8MB - 16MB VRAM | pci_sg.rom
+<b>3DFX Voodoo 3 2000</b> | Voodoo 3 based<br/>16MB VRAM | voodoo3_2000/2k11sd.rom
+<b>3DFX Voodoo 3 3000</b> | Voodoo 3 based<br/>16MB VRAM | voodoo3_3000/3k12sd.rom
+<b>Creative Labs 3D Blaster Banshee</b> | Voodoo Banshee based<br/>16MB VRAM | blasterpci.rom
+<b>Diamond Stealth 3D 2000</b> <i>[[2]](#graphics-note-2)</i>| S3 ViRGE/325 based<br/>2MB - 4MB VRAM | s3virge.bin
+<b>S3 ViRGE/DX</b> <i>[[3]](#graphics-note-3)</i>| S3 ViRGE/DX based<br/>2MB - 4MB VRAM | 86c375_1.bin
+
+### 3D only cards
+Hardware | Addl. Info 
+--- | --- 
+<b>3DFX Voodoo Graphics</b> <i>[[4]](#graphics-note-4)</i>| 3D accelerator. Widely supported in late 90s games.
+<b>Obsidian SB50</b> <i>[[5]](#graphics-note-5)</i>| Voodoo with 2 TMUs
+<b>3DFX Voodoo 2</b> <i>[[6]](#graphics-note-6)</i>| Improved Voodoo Graphics<br/>Higher clocks<br/>2 TMUs<br/>Triangle setup, etc.
+
+#### Additional Notes
+<a name="graphics-note-1">`[1]`</a> <b>Cirrus Logic GD-5434</b>: Real chip also supports 1MB configurations, however this is not currently supported in PCem.
+
+<a name="graphics-note-2">`[2]`</a> <b>Diamond Stealth 3D 2000</b>: PCem emulates the ViRGE S3D engine in software. This works with most games I tried, but there may be some issues. The Direct3D drivers for the /325 are fairly poor (often showing as missing triangles), so use of the /DX instead is recommended.
+
+<a name="graphics-note-3">`[3]`</a> <b>S3 ViRGE/DX</b>: The drivers that come with Windows are similar to those for the /325, however better ones do exist (try the 8-21-1997 version). With the correct drivers, many early Direct3D games work okay (if slowly).
+
+<a name="graphics-note-4">`[4]`</a> <b>3DFX Voodoo Graphics</b>: PCem emulates this in software. The emulation is a lot faster than in v10 (thanks to a new dynamic recompiler) and should be capable of hitting Voodoo 1 performance on most machines when two render threads are used. As before, the emulated CPU is the bottleneck for most games. <br/><br/>PCem can emulate 6 and 8 MB configurations, but defaults to 4 MB for compatibility. It can also emulate the screen filter present on the original card, though this does at present have a noticeable performance hit.<br/><br/>Almost everything I've tried works okay, with a very few exceptions - Screamer 2 and Rally have serious issues.
+
+<a name="graphics-note-5">`[5]`</a> <b>Obsidian SB50</b>: Drivers for this are a bit limited - the official drivers don't support 2 TMUs in Direct3D.
+
+<a name="graphics-note-6">`[6]`</a> <b>3DFX Voodoo 2</b>: PCem can emulate both 8 and 12 MB configurations. It can also emulate 6 and 10 MB configurations (with 2MB framebuffer memory), which were never sold into the PC market but do exist for arcade systems.
+
+<hr>
+
+## Sound Cards
+
+Hardware | Notes
+--- | ---
+<b>PC speaker</b> | The standard beeper on all PCs. Supports samples/RealSound.
+<b>Tandy PSG</b> | The Texas Instruments chip in the PCjr and Tandy 1000. Supports 3 voices plus noise. I reused the emulator in B-em for this (slightly modified). PCem emulates the differences between the SN76496 (PCjr and Tandy 1000), and the NCR8496 (currently assigned to the Tandy 1000HX). Maniac Mansion and Zak McKraken will only sound correct on the latter.
+<b>Tandy PSSJ</b> | Used on the Tandy 1000SL/2, this clones the NCR8496, adding an addition frequency divider (did any software actually use this?) and an 8-bit DAC.
+<b>PS/1 audio card</b> | An SN76496 clone plus an 8-bit DAC. The SN76496 isn't at the same address as PCjr/Tandy, so most software doesn't support it.
+<b>Gameblaster</b> | The Creative Labs Gameblaster/Creative Music System, Creative's first sound card introduced in 1987. Has two Philips SAA1099, giving 12 voices of square waves plus 4 noise voices. In stereo!
+<b>Adlib</b> | Has a Yamaha YM3812, giving 9 voices of 2 op FM, or 6 voices plus a rhythm section. PCem uses the DOSBox dbopl emulator.
+<b>Adlib Gold</b> | OPL3 with YM318Z 12-bit digital section. Possibly some bugs (not a lot of software to test). The surround module is now emulated.
+<b>Sound Blaster</b> <i>[[1]](#sound-note-1)</i> | See linked note for more details.
+<b>Gravis Ultrasound</b> | 32 voice sample playback. Port address is fixed to 240, IRQ and DMA can be changed from the drivers. Emulation is improved significantly over previous versions.
+<b>Windows Sound System</b> | 16-bit digital + OPL3. Note that this only emulates WSS itself, and should not be used with drivers from compatible boards with additional components (eg Turtle Beach Monte Carlo)
+<b>Aztech Sound Galaxy Pro 16 AB (Washington)</b> | SB compatible + WSS compatible
+<b>Innovation SSI-2001</b> | SID6581. Emulated using resid-fp. Board is fixed to port 280.
+<b>Ensoniq AudioPCI (ES1371)<br/>Sound Blaster PCI 128</b> | Basic PCI sound card. Emulates Sound Blaster in software.
+
+### Additional Notes
+<a name="sound-note-1">`[1]`</a> <b>Sound Blaster</b>: Several Sound Blasters are emulated.
+* SB v1.0 - The original. Limited to 22khz, and no auto-init DMA (can cause crackles sometimes).
+* SB v1.5 - Adds auto-init DMA
+* SB v2.0 - Upped to 41khz
+* SB Pro v1.0 - Stereo with twin OPL2 chips.
+* SB Pro v2.0 - Stereo with OPL 3 chip
+* SB 16 - 16 bit stereo
+* SB AWE32 - SB 16 + wavetable MIDI. This requires a ROM dump from a real AWE32.
+
+All cards are set to Address 220, IRQ 7 and DMA 1 (and High DMA 5). IRQ and DMA can be changed for the SB16 & AWE32 in the drivers. The relevant SET line for autoexec.bat is `SET BLASTER = A220 I7 D1 Tx` - where Tx is T1 for SB v1.0, T3 for SB v2.0, T4 for SB Pro, and T6 for SB16.
+
+AWE32 requires a ROM dump called `awe32.raw`. AWE-DUMP is a utility which can get a dump from a real card. Most EMU8000 functionality should work, however filters are not correct and reverb/chorus effects are not currently emulated.
+
+<hr>
+
+## HDD Controller Cards
+
+Int. | Hardware | Notes | ROM file needed<br/>(within ./roms/ folder)
+:-: | --- | --- | ----
+MFM | <b>Fixed Disk Adapter (Xebec)</b> | MFM controller originally included in the IBM XT. This controller only supports HD types 0, 2, 13, and 16. | ibm_xebec_62x0822_1985.bin
+MFM | <b>DTC 5150X</b> | 8-bit MFM controller.<br/>To configure drive types, run `DEBUG.EXE` and enter `g=c800:5`. | dtc_cxd21a.bin
+MFM | <b>AT Fixed Disk Adapter</b> | MFM controller originally included in the IBM AT. Supported by all AT-compatible BIOSes. | <i>(none)</i>
+ESDI | <b>Western Digital WD1007V-SE1</b> | 16-bit ESDI controller | 62-000279-061.bin
+ESDI | <b>IBM ESDI Fixed Disk Controller</b> | MCA ESDI controller. Only supported on PS/2 models. | 90x8969.bin<br/>90x8970.bin
+IDE | <b>Standard IDE</b> | Standard IDE controller. Supported by all AT-compatible BIOSes. Use this if in any doubt! | <i>(none)</i>
+IDE | <b>XTIDE</b> | 8-bit IDE controller. The BIOS is available [here](http://code.google.com/p/xtideuniversalbios/). <br/>v2.0.0 beta 1 is the version I've mostly tested. v2.0.0 beta 3 is known to have some issues. | ide_xt.bin
+IDE | <b>XTIDE (AT)</b> | 16-bit IDE controller. | ide_at.bin
+IDE | <b>XTIDE (PS/1)</b> | IDE controller for the PS/1 model 2033. For this machine you will need BIOS version v1.1.5. The PS/1 is a bit fussy with XTIDE, and I've found that it works best when the XTIDE configuration has 'Full Operating Mode' disabled. | ide_at_1_1_5.bin
+SCSI | <b>Longshine LCS-6821N</b> | 8-bit SCSI controller. | Longshine LCS-6821N - BIOS version 1.04.bin
+SCSI | <b>Rancho RT1000B</b> | 8-bit SCSI controller. | Rancho_RT1000_RTBios_version_8.10R.bin
+SCSI | <b>Trantor T130B</b> | 8-bit SCSI controller. | trantor_t130b_bios_v2.14.bin
+SCSI | <b>IBM SCSI Adapter with Cache</b> | MCA SCSI controller. Only supported on PS/2 models. | 92F2244.U68<br/>92F2245.U69
+SCSI | <b>Adaptec AHA-1542C</b> | 16-bit SCSI controller. | adaptec_aha1542c_bios_534201-00.bin
+SCSI | <b>BusLogic BT-545S</b> | 16-bit SCSI controller. | BusLogic_BT-545S_U15_27128_5002026-4.50.bin
+
+<hr>
+
+## Misc Cards
+
+Hardware | Note
+--- | ---
+Serial mouse | A Microsoft compatible serial mouse on COM1. Compatible drivers are all over the place for this.
+M24 mouse | I haven't seen a DOS mouse driver for this yet but the regular scancode mode works as does the Windows 1.x driver.
+PC1512 mouse | The PC1512's perculiar quadrature mouse. You need Amstrad's actual driver for this one.
+PS/2 mouse | A standard 2 button PS/2 mouse. As with serial, compatible drivers are common.
+Microsoft PS/2 Intellimouse | A PS/2 mouse with mouse wheel.
+ATAPI CD-ROM | Works with OAKCDROM.SYS, VDD-IDE.SYS, and the internal drivers of every OS I've tried.

Readme-LINUX.txt

@@ -1,31 +0,0 @@
-PCem v14 Linux supplement
-
-
-You will need the following libraries :
-
-SDL2
-wxWidgets 3.x
-OpenAL
-
-and their dependencies.
-
-Open a terminal window, navigate to the PCem directory then enter
-
-./configure --enable-release
-make
-
-then ./pcem to run.
-
-The Linux version stores BIOS ROM images, configuration files, and other data in ~/.pcem
-
-configure options are :
-  --enable-release-build : Generate release build. Recommended for regular use.
-  --enable-debug         : Compile with debugging enabled.
-  --enable-networking    : Build with networking support.
-  --enable-alsa          : Build with support for MIDI output through ALSA. Requires libasound.
-
-
-The menu is a pop-up menu in the Linux port. Right-click on the main window when mouse is not
-captured.
-
-CD-ROM support currently only accesses /dev/cdrom. It has not been heavily tested.

TESTED.md

@@ -0,0 +1,330 @@
+## Software tested (v17):
+
+### DOS
+- PC-DOS 1.0
+- MS-DOS 2.11
+- MS-DOS 3.30
+- MS-DOS 4.01
+- MS-DOS 5.0
+- MS-DOS 6.0
+- MS-DOS 6.22
+
+### Windows
+- Windows 1.04
+- Windows/286 2.11
+- Windows/386 2.11
+- Windows 3.0
+- Windows 3.1
+- Windows for Workgroups 3.11
+- Windows 95
+- Windows 95 OSR2
+- Windows 98SE
+- Windows ME
+
+### Windows NT
+- Windows NT 3.1
+- Windows NT 3.51
+- Windows NT 4 Workstation (SP6a)
+- Windows 2000
+- Windows XP
+
+### OS/2
+- OS/2 v1.0
+- OS/2 v1.1
+- OS/2 v1.2
+- OS/2 v1.3
+- OS/2 v2.1
+- OS/2 Warp 3
+- OS/2 Warp 4
+
+### Linux
+- Corel Linux 1.2
+- Mandriva LE 2005
+- Red Hat Linux 7.1 (Seawolf)
+
+### BeOS
+- BeOS 5.0 Professional Edition
+
+### Applications
+- 3DMark 2000
+- 3DMark 2001SE
+- After Dark 3.06
+- Cinemania 1994
+- Creative Writer
+- Cubasis
+- Encarta 1994
+- Fasttracker v2.08
+- PageMaker 5.0
+- PC Paintbrush 1.05
+- Photoshop 3.0
+- Smartsuite 97
+- Visual Basic 3.0
+- Visual C++ 6.0
+- Word for Windows 2.0
+- Winzip 6.2
+
+### Games
+- 1602 AD (demo)
+- 3D Ultra Pinball Thrillride
+- A-10 Tank Killer
+- Actua Soccer
+- Adventure Pinball Forgotten Island (demo)
+- Aladdin
+- Alien vs Predator
+- Alien vs Predator 2 (demo)
+- All New World of Lemmings
+- Alone in the Dark
+- Alone in the Dark : The New Nightmare (demo)
+- Anachronox
+- Arkanoid
+- Armoured Fist 3 (demo)
+- Asteroids (1998)
+- B-17 Flying Fortress
+- Battle Chess
+- Battlezone
+- Battlezone II
+- Bejeweled
+- Beyond Castle Wolfenstein
+- Big Red Racing
+- Bio Menace
+- Black & White
+- Brix
+- Bugs Bunny Lost In Time (demo)
+- Cannon Fodder 2
+- Carnivores 2
+- Civilization
+- Civilization for Windows
+- Claw
+- Clive Barker's Undying (demo)
+- Clockwiser
+- Command & Conquer : Red Alert
+- Command & Conquer : Red Alert 2
+- Command & Conquer : Tiberian Sun (demo)
+- Command & Conquer Renegade
+- Conquest
+- Corridor 7
+- Counter-Strike 2D
+- Crimson Skies (demo)
+- Croc
+- Curse of Monkey Island
+- Cutthroats (demo)
+- Daikatana
+- Dawn Patrol
+- Day of the Tentacle
+- Dance Dance Revolution
+- Dead Reckoning (demo)
+- Death Drome
+- Desert Strike
+- Digger
+- Dirt Track Racing (demo)
+- Disciples (demo)
+- Discworld II
+- Doom (v1.2)
+- Doom II (v1.666)
+- Double Dragon
+- Drakan (demo)
+- Duke Nukem 3D (v1.3D)
+- Dune
+- DX-Ball 2
+- Echelon
+- Ecstatica
+- Epic Pinball
+- Every Extend
+- Evolva (demo)
+- Expendable
+- Eye of the Beholder
+- Fallout Tactics (demo)
+- Final Fantasy VIII (demo)
+- Flashback
+- Flight Simulator 5
+- Frogger
+- Frontier : First Encounters
+- Gabriel Knight 3 (demo)
+- Giants : Citizen Kabuto
+- GLQuake
+- Grand Theft Auto 2
+- Half-Life
+- Halloween Harry
+- Heartlight
+- Hellbender
+- Hexen
+- High Heat Baseball 2002 (demo)
+- Hitch Hiker's Guide to the Galaxy
+- Hocus Pocus
+- Homeworld Cataclysm (demo)
+- Incoming
+- James Pond 2 : Robocod
+- Jazz Jackrabbit
+- Jazz Jackrabbit 2
+- Jill of the Jungle
+- King's Quest
+- King's Quest II
+- King's Quest III
+- Lemmings
+- Lemmings 2 : The Tribes
+- Lode Runner : The Legend Continues
+- Lotus III
+- Madden 2002 (demo)
+- Majesty (demo)
+- Maniac Mansion (enhanced)
+- Max Payne
+- MDK (Direct3D, USA release)
+- MechCommander 2
+- Mechwarrior 2
+- Mechwarrior 3
+- Megaman Legends
+- Metal Gear Solid
+- Microsoft Arcade
+- Microsoft Golf 99 (demo)
+- Midtown Madness 2 (demo)
+- Monaco Grand Prix (demo)
+- Monkey Island 2
+- Monster Bash
+- Monster Truck Madness
+- Mortal Kombat
+- Mortal Kombat 2
+- Mortal Kombat 3
+- Motorcross Madness (demo)
+- Mystic Towers
+- Nascar Heat
+- Need for Speed II SE
+- Need for Speed III
+- Need for Speed : High Stakes
+- NHL 2001 (demo)
+- No One Lives Forever
+- Oddworld : Abe's Exoddus
+- One Must Fall 2097
+- Oni
+- Outlaws
+- Pacific Strike
+- Pacman Adventures in Time (demo)
+- Pharoah (demo)
+- Pinball Fantasies
+- Pinball Illusions
+- Police Quest
+- Police Quest 2
+- Porrasturvat
+- Power Drive
+- Prince of Persia
+- Prince of Persia 3D (demo)
+- Pro Pinball : The Web
+- Psycho Pinball
+- Quake
+- Quake II
+- Quake III Arena
+- Rayman 2 (demo)
+- Red Faction
+- Redline Racer
+- Rise of the Triad (v1.2)
+- Screamer
+- Sega Rally 2 (demo)
+- Sensible World of Soccer
+- Settlers 3 (demo)
+- Severance : Blade of Darkness (demo)
+- Shadow Company (demo)
+- Shadow Warrior
+- Shadowman (demo)
+- Sid Meier's Alien Crossfire (demo)
+- SimCity 2000
+- SimCity Classic
+- SimTower
+- Sink or Swim
+- Soldat (1.0.5)
+- Sonic CD
+- Space Simulator
+- Space Strike
+- Spider-Man (demo)
+- Springy Madness
+- Star Trek Hidden Evil (demo)
+- Star Trek Voyager Elite Force
+- Star Wars Jedi Academy
+- Starfleet Command 2 (demo)
+- Stargunner
+- Starlancer (demo)
+- Steel Beasts (demo)
+- Stunt Island
+- SWAT 3 Elite Edition (demo)
+- Syndicate
+- System Shock
+- Tanktics (demo)
+- Terminal Velocity
+- The Dig
+- The Humans
+- The Labyrinth (RealArcade version)
+- The Lost Vikings
+- The Ultimate Doom (v1.9)
+- Theme Hospital
+- Theme Park
+- Tomb Raider
+- Tomb Raider II
+- Tomb Raider The Last Revelation (demo)
+- Tony Hawk's Pro Skater 2
+- Transport Tycoon
+- Transport Tycoon Deluxe
+- Tropico (demo)
+- Turrican 2
+- UFO : Enemy Unknown
+- Ultimate Ride (demo)
+- Unreal
+- Unreal Tournament
+- Unreal Tournament 2004 (Direct3D)
+- Wacky Wheels
+- Warlords Battlecry (demo)
+- Wheel of Time (demo)
+- Wing Commander
+- Wing Commander : Privateer
+- Wizkid
+- Wolfenstein 3D
+- World War III : Black Gold (demo)
+- Worms
+- Worms Armageddon
+- X-Com : Terror From The Deep
+- Xargon
+- Z : Steel Soldiers (demo)
+- Zak McKracken
+- Zone 66
+
+### Demos
+- Cascada - Cronologia
+- Coma - Paimen
+- Complex - Cyboman 2
+- Complex - Dope
+- EMF - Verses
+- Exceed - Heaven 7
+- Future Crew - Second Reality
+- Gazebo - Cyboman
+- Halcyon - Lifeforms
+- Iguana - Heartquake
+- Impact Studios - Legend
+- Impact Studios - Project Angel
+- KFMF - Dance, Move, Shake
+- KFMF - Trip
+- Logic Design - Fashion
+- Majic 12 - Show
+- Majic 12 - Wish
+- Megabusters - Hellraiser
+- Orange - x14
+- Renaissance - Amnesia
+- Skull - Putre Faction
+- Tran - Ambience (flickery)
+- Tran - Luminati (flickery)
+- Tran - Timeless
+- Triton - Crystal Dream
+- Triton - Crystal Dream 2
+- Ultraforce - Coldcut
+- Ultraforce - Vector Demo
+- Valhalla - Solstice
+- Witan - Witan House
+
+### Emulators
+- Beebem v1.02
+- BeebInC v0.99f
+- CPE v5.2i
+- DOSBox 0.74-3
+- Fellow 0.33
+- KGen98 v0.4b
+- PaCifiST v0.48
+- SNES9x v0.96
+- UltraHLE v1.0.0
+- vMac v0.1.9.1
+- ZSNES v0.800c

aclocal.m4

@@ -1,6 +1,6 @@
-# generated automatically by aclocal 1.15 -*- Autoconf -*-
+# generated automatically by aclocal 1.16.3 -*- Autoconf -*-
 
-# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+# Copyright (C) 1996-2020 Free Software Foundation, Inc.
 
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -14,15 +14,15 @@
 m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])])
 m4_ifndef([AC_AUTOCONF_VERSION],
   [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl
-m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.69],,
+m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.71],,
-[m4_warning([this file was generated for autoconf 2.69.
+[m4_warning([this file was generated for autoconf 2.71.
 You have another version of autoconf.  It may work, but is not guaranteed to.
 If you have problems, you may need to regenerate the build system entirely.
 To do so, use the procedure documented by the package, typically 'autoreconf'.])])
 
-dnl pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
+# pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
-dnl serial 11 (pkg-config-0.29)
+# serial 12 (pkg-config-0.29.2)
-dnl
+
 dnl Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
 dnl Copyright © 2012-2015 Dan Nicholson <dbn.lists@gmail.com>
 dnl
@@ -63,7 +63,7 @@ dnl
 dnl See the "Since" comment for each macro you use to see what version
 dnl of the macros you require.
 m4_defun([PKG_PREREQ],
-[m4_define([PKG_MACROS_VERSION], [0.29])
+[m4_define([PKG_MACROS_VERSION], [0.29.2])
 m4_if(m4_version_compare(PKG_MACROS_VERSION, [$1]), -1,
     [m4_fatal([pkg.m4 version $1 or higher is required but ]PKG_MACROS_VERSION[ found])])
 ])dnl PKG_PREREQ
@@ -164,7 +164,7 @@ AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
 AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
 
 pkg_failed=no
-AC_MSG_CHECKING([for $1])
+AC_MSG_CHECKING([for $2])
 
 _PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
 _PKG_CONFIG([$1][_LIBS], [libs], [$2])
@@ -174,7 +174,7 @@ and $1[]_LIBS to avoid the need to call pkg-config.
 See the pkg-config man page for more details.])
 
 if test $pkg_failed = yes; then
-   	AC_MSG_RESULT([no])
+        AC_MSG_RESULT([no])
         _PKG_SHORT_ERRORS_SUPPORTED
         if test $_pkg_short_errors_supported = yes; then
 	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1`
@@ -195,7 +195,7 @@ installed software in a non-standard prefix.
 _PKG_TEXT])[]dnl
         ])
 elif test $pkg_failed = untried; then
-     	AC_MSG_RESULT([no])
+        AC_MSG_RESULT([no])
 	m4_default([$4], [AC_MSG_FAILURE(
 [The pkg-config script could not be found or is too old.  Make sure it
 is in your PATH or set the PKG_CONFIG environment variable to the full
@@ -372,7 +372,7 @@ AC_ARG_VAR(SDL2_FRAMEWORK, [Path to SDL2.framework])
         done
       fi
 
-      if test -d $sdl_framework; then
+      if test x"$sdl_framework" != x && test -d "$sdl_framework"; then
         AC_MSG_RESULT($sdl_framework)
         sdl_framework_dir=`dirname $sdl_framework`
         SDL_CFLAGS="-F$sdl_framework_dir -Wl,-framework,SDL2 -I$sdl_framework/include"
@@ -675,7 +675,8 @@ AC_DEFUN([_WX_PRIVATE_CHECK_VERSION],
 
 dnl ---------------------------------------------------------------------------
 dnl WX_CONFIG_CHECK(VERSION, [ACTION-IF-FOUND [, ACTION-IF-NOT-FOUND
-dnl                  [, WX-LIBS [, ADDITIONAL-WX-CONFIG-FLAGS]]]])
+dnl                  [, WX-LIBS [, ADDITIONAL-WX-CONFIG-FLAGS
+dnl                  [, WX-OPTIONAL-LIBS]]]]])
 dnl
 dnl Test for wxWidgets, and define WX_C*FLAGS, WX_LIBS and WX_LIBS_STATIC
 dnl (the latter is for static linking against wxWidgets). Set WX_CONFIG_NAME
@@ -692,6 +693,10 @@ dnl Optional ADDITIONAL-WX-CONFIG-FLAGS argument is appended to wx-config
 dnl invocation command in present. It can be used to fine-tune lookup of
 dnl best wxWidgets build available.
 dnl
+dnl Optional WX-OPTIONAL-LIBS argument contains comma- or space-separated list
+dnl of wxWidgets libraries to link against if they are available.
+dnl WX-OPTIONAL-LIBS is supported on version 2.9.0 and later.
+dnl
 dnl Example use:
 dnl   WX_CONFIG_CHECK([2.6.0], [wxWin=1], [wxWin=0], [html,core,net]
 dnl                    [--unicode --debug])
@@ -743,8 +748,8 @@ AC_DEFUN([WX_CONFIG_CHECK],
       AC_MSG_CHECKING([for wxWidgets version >= $min_wx_version ($5)])
     fi
 
-    dnl don't add the libraries ($4) to this variable as this would result in
+    dnl don't add the libraries (4th argument) to this variable as this would
-    dnl an error when it's used with --version below
+    dnl result in an error when it's used with --version below
     WX_CONFIG_WITH_ARGS="$WX_CONFIG_PATH $wx_config_args $5"
 
     WX_VERSION=`$WX_CONFIG_WITH_ARGS --version 2>/dev/null`
@@ -768,14 +773,20 @@ AC_DEFUN([WX_CONFIG_CHECK],
 
     if test -n "$wx_ver_ok"; then
       AC_MSG_RESULT(yes (version $WX_VERSION))
-      WX_LIBS=`$WX_CONFIG_WITH_ARGS --libs $4`
+
+      wx_optional_libs=""
+      _WX_PRIVATE_CHECK_VERSION(2,9,0)
+      if test -n "$wx_ver_ok" -a -n "$6"; then
+        wx_optional_libs="--optional-libs $6"
+      fi
+      WX_LIBS=`$WX_CONFIG_WITH_ARGS --libs $4 $wx_optional_libs`
 
       dnl is this even still appropriate?  --static is a real option now
       dnl and WX_CONFIG_WITH_ARGS is likely to contain it if that is
       dnl what the user actually wants, making this redundant at best.
       dnl For now keep it in case anyone actually used it in the past.
       AC_MSG_CHECKING([for wxWidgets static library])
-      WX_LIBS_STATIC=`$WX_CONFIG_WITH_ARGS --static --libs $4 2>/dev/null`
+      WX_LIBS_STATIC=`$WX_CONFIG_WITH_ARGS --static --libs $4 $wx_optional_libs 2>/dev/null`
       if test "x$WX_LIBS_STATIC" = "x"; then
         AC_MSG_RESULT(no)
       else
@@ -1052,7 +1063,7 @@ AC_DEFUN([WX_ARG_ENABLE_YESNOAUTO],
                 $2=0
             elif test "$enableval" = "auto" ; then
                 AC_MSG_RESULT([will be automatically detected])
-                $2="auto"
+                $2=""
             else
                 AC_MSG_ERROR([
     Unrecognized option value (allowed values: yes, no, auto)
@@ -1078,7 +1089,7 @@ AC_DEFUN([WX_ARG_WITH_YESNOAUTO],
                 $2=0
             elif test "$withval" = "auto" ; then
                 AC_MSG_RESULT([will be automatically detected])
-                $2="auto"
+                $2=""
             else
                 AC_MSG_ERROR([
     Unrecognized option value (allowed values: yes, auto)
@@ -1130,17 +1141,17 @@ AC_DEFUN([WX_STANDARD_OPTIONS],
                 AC_MSG_CHECKING([for the --with-toolkit option])
                 if test "$withval" = "auto" ; then
                     AC_MSG_RESULT([will be automatically detected])
-                    TOOLKIT="auto"
+                    TOOLKIT=""
                 else
                     TOOLKIT="$withval"
 
                     dnl PORT must be one of the allowed values
-                    if test "$TOOLKIT" != "gtk1" -a "$TOOLKIT" != "gtk2" -a \
+                    if test "$TOOLKIT" != "gtk1" -a "$TOOLKIT" != "gtk2" -a "$TOOLKIT" != "gtk3" -a \
                             "$TOOLKIT" != "msw" -a "$TOOLKIT" != "motif" -a \
                             "$TOOLKIT" != "osx_carbon" -a "$TOOLKIT" != "osx_cocoa" -a \
-                            "$TOOLKIT" != "dfb" -a "$TOOLKIT" != "x11"; then
+                            "$TOOLKIT" != "dfb" -a "$TOOLKIT" != "x11" -a "$TOOLKIT" != "base"; then
                         AC_MSG_ERROR([
-    Unrecognized option value (allowed values: auto, gtk1, gtk2, msw, motif, osx_carbon, osx_cocoa, dfb, x11)
+    Unrecognized option value (allowed values: auto, gtk1, gtk2, gtk3, msw, motif, osx_carbon, osx_cocoa, dfb, x11, base)
                         ])
                     fi
 
@@ -1204,7 +1215,7 @@ AC_DEFUN([WX_STANDARD_OPTIONS],
                 AC_MSG_CHECKING([for the --with-wxversion option])
                 if test "$withval" = "auto" ; then
                     AC_MSG_RESULT([will be automatically detected])
-                    WX_RELEASE="auto"
+                    WX_RELEASE=""
                 else
 
                     wx_requested_major_version=`echo $withval | \
@@ -1239,7 +1250,7 @@ dnl ---------------------------------------------------------------------------
 dnl WX_CONVERT_STANDARD_OPTIONS_TO_WXCONFIG_FLAGS
 dnl
 dnl Sets the WXCONFIG_FLAGS string using the SHARED,DEBUG,UNICODE variable values
-dnl which are different from "auto".
+dnl which were specified.
 dnl Thus this macro needs to be called only once all options have been set.
 dnl ---------------------------------------------------------------------------
 AC_DEFUN([WX_CONVERT_STANDARD_OPTIONS_TO_WXCONFIG_FLAGS],
@@ -1263,11 +1274,11 @@ AC_DEFUN([WX_CONVERT_STANDARD_OPTIONS_TO_WXCONFIG_FLAGS],
             WXCONFIG_FLAGS="$WXCONFIG_FLAGS""--unicode=no "
         fi
 
-        if test "$TOOLKIT" != "auto" ; then
+        if test -n "$TOOLKIT" ; then
             WXCONFIG_FLAGS="$WXCONFIG_FLAGS""--toolkit=$TOOLKIT "
         fi
 
-        if test "$WX_RELEASE" != "auto" ; then
+        if test -n "$WX_RELEASE" ; then
             WXCONFIG_FLAGS="$WXCONFIG_FLAGS""--version=$WX_RELEASE "
         fi
 
@@ -1281,16 +1292,16 @@ AC_DEFUN([WX_CONVERT_STANDARD_OPTIONS_TO_WXCONFIG_FLAGS],
 
 
 dnl ---------------------------------------------------------------------------
-dnl _WX_SELECTEDCONFIG_CHECKFOR([RESULTVAR], [STRING], [MSG]
+dnl _WX_SELECTEDCONFIG_CHECKFOR([RESULTVAR], [STRING], [MSG])
-dnl                             [, ACTION-IF-FOUND [, ACTION-IF-NOT-FOUND]])
 dnl
-dnl Outputs the given MSG. Then searches the given STRING in the wxWidgets
+dnl Sets WX_$RESULTVAR to the value of $RESULTVAR if it's defined. Otherwise,
-dnl additional CPP flags and put the result of the search in WX_$RESULTVAR
+dnl auto-detect the value by checking for the presence of STRING in
-dnl also adding the "yes" or "no" message result to MSG.
+dnl $WX_SELECTEDCONFIG (which is supposed to be set by caller) and set
+dnl WX_$RESULTVAR to either 0 or 1, also outputting "yes" or "no" after MSG.
 dnl ---------------------------------------------------------------------------
 AC_DEFUN([_WX_SELECTEDCONFIG_CHECKFOR],
         [
-        if test "$$1" = "auto" ; then
+        if test -z "$$1" ; then
 
             dnl The user does not have particular preferences for this option;
             dnl so we will detect the wxWidgets relative build setting and use it
@@ -1305,11 +1316,9 @@ AC_DEFUN([_WX_SELECTEDCONFIG_CHECKFOR],
             if test "$WX_$1" != "0"; then
                 WX_$1=1
                 AC_MSG_RESULT([yes])
-                ifelse([$4], , :, [$4])
             else
                 WX_$1=0
                 AC_MSG_RESULT([no])
-                ifelse([$5], , :, [$5])
             fi
         else
 
@@ -1356,19 +1365,16 @@ AC_DEFUN([WX_DETECT_STANDARD_OPTION_VALUES],
             echo "[[dbg]] WX_SELECTEDCONFIG: $WX_SELECTEDCONFIG"
         fi
 
-
         dnl we could test directly for WX_SHARED with a line like:
         dnl    _WX_SELECTEDCONFIG_CHECKFOR([SHARED], [shared],
         dnl                                [if wxWidgets was built in SHARED mode])
         dnl but wx-config --selected-config DOES NOT outputs the 'shared'
         dnl word when wx was built in shared mode; it rather outputs the
         dnl 'static' word when built in static mode.
-        if test $WX_SHARED = "1"; then
+        if test "$WX_SHARED" = "1"; then
             STATIC=0
-        elif test $WX_SHARED = "0"; then
+        elif test "$WX_SHARED" = "0"; then
             STATIC=1
-        elif test $WX_SHARED = "auto"; then
-            STATIC="auto"
         fi
 
         dnl Now set the WX_UNICODE, WX_DEBUG, WX_STATIC variables
@@ -1391,7 +1397,7 @@ AC_DEFUN([WX_DETECT_STANDARD_OPTION_VALUES],
         AC_SUBST(WX_SHARED)
 
         dnl detect the WX_PORT to use
-        if test "$TOOLKIT" = "auto" ; then
+        if test -z "$TOOLKIT" ; then
 
             dnl The user does not have particular preferences for this option;
             dnl so we will detect the wxWidgets relative build setting and use it
@@ -1399,22 +1405,26 @@ AC_DEFUN([WX_DETECT_STANDARD_OPTION_VALUES],
 
             WX_GTKPORT1=$(expr "$WX_SELECTEDCONFIG" : ".*gtk1.*")
             WX_GTKPORT2=$(expr "$WX_SELECTEDCONFIG" : ".*gtk2.*")
+            WX_GTKPORT3=$(expr "$WX_SELECTEDCONFIG" : ".*gtk3.*")
             WX_MSWPORT=$(expr "$WX_SELECTEDCONFIG" : ".*msw.*")
             WX_MOTIFPORT=$(expr "$WX_SELECTEDCONFIG" : ".*motif.*")
             WX_OSXCOCOAPORT=$(expr "$WX_SELECTEDCONFIG" : ".*osx_cocoa.*")
             WX_OSXCARBONPORT=$(expr "$WX_SELECTEDCONFIG" : ".*osx_carbon.*")
             WX_X11PORT=$(expr "$WX_SELECTEDCONFIG" : ".*x11.*")
             WX_DFBPORT=$(expr "$WX_SELECTEDCONFIG" : ".*dfb.*")
+            WX_BASEPORT=$(expr "$WX_SELECTEDCONFIG" : ".*base.*")
 
             WX_PORT="unknown"
             if test "$WX_GTKPORT1" != "0"; then WX_PORT="gtk1"; fi
             if test "$WX_GTKPORT2" != "0"; then WX_PORT="gtk2"; fi
+            if test "$WX_GTKPORT3" != "0"; then WX_PORT="gtk3"; fi
             if test "$WX_MSWPORT" != "0"; then WX_PORT="msw"; fi
             if test "$WX_MOTIFPORT" != "0"; then WX_PORT="motif"; fi
             if test "$WX_OSXCOCOAPORT" != "0"; then WX_PORT="osx_cocoa"; fi
             if test "$WX_OSXCARBONPORT" != "0"; then WX_PORT="osx_carbon"; fi
             if test "$WX_X11PORT" != "0"; then WX_PORT="x11"; fi
             if test "$WX_DFBPORT" != "0"; then WX_PORT="dfb"; fi
+            if test "$WX_BASEPORT" != "0"; then WX_PORT="base"; fi
 
             dnl NOTE: backward-compatible check for wx2.8; in wx2.9 the mac
             dnl       ports are called 'osx_cocoa' and 'osx_carbon' (see above)
@@ -1432,14 +1442,8 @@ AC_DEFUN([WX_DETECT_STANDARD_OPTION_VALUES],
 
             AC_MSG_RESULT([$WX_PORT])
         else
-
             dnl Use the setting given by the user
-            if test -z "$TOOLKIT" ; then
+            WX_PORT=$TOOLKIT
-                WX_PORT=$TOOLKIT
-            else
-                dnl try with PORT
-                WX_PORT=$PORT
-            fi
         fi
 
         AC_SUBST(WX_PORT)
@@ -1470,35 +1474,29 @@ AC_DEFUN([WX_DETECT_STANDARD_OPTION_VALUES],
                          ])
         fi
 
-        dnl now we can finally update the DEBUG,UNICODE,SHARED options
+        dnl now we can finally update the options to their final values if they
-        dnl to their final values if they were set to 'auto'
+        dnl were not already set
-        if test "$DEBUG" = "auto"; then
+        if test -z "$UNICODE" ; then
-            DEBUG=$WX_DEBUG
-        fi
-        if test "$UNICODE" = "auto"; then
             UNICODE=$WX_UNICODE
         fi
-        if test "$SHARED" = "auto"; then
+        if test -z "$SHARED" ; then
             SHARED=$WX_SHARED
         fi
-        if test "$TOOLKIT" = "auto"; then
+        if test -z "$TOOLKIT" ; then
             TOOLKIT=$WX_PORT
         fi
 
-        dnl in case the user needs a BUILD=debug/release var...
+        dnl respect the DEBUG variable adding the optimize/debug flags and also
-        if test "$DEBUG" = "1"; then
+        dnl define a BUILD variable in case the user wants to use it
-            BUILD="debug"
+        dnl
-        elif test "$DEBUG" = "0" -o "$DEBUG" = ""; then
-            BUILD="release"
-        fi
-
-        dnl respect the DEBUG variable adding the optimize/debug flags
         dnl NOTE: the CXXFLAGS are merged together with the CPPFLAGS so we
         dnl       don't need to set them, too
         if test "$DEBUG" = "1"; then
+            BUILD="debug"
             CXXFLAGS="$CXXFLAGS -g -O0"
             CFLAGS="$CFLAGS -g -O0"
-        else
+        elif test "$DEBUG" = "0"; then
+            BUILD="release"
             CXXFLAGS="$CXXFLAGS -O2"
             CFLAGS="$CFLAGS -O2"
         fi
@@ -1591,7 +1589,7 @@ AC_DEFUN([AM_PATH_WXCONFIG], [
 ])
 AC_DEFUN([AM_PATH_WXRC], [WXRC_CHECK([$1],[$2])])
 
-# Copyright (C) 2002-2014 Free Software Foundation, Inc.
+# Copyright (C) 2002-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -1603,10 +1601,10 @@ AC_DEFUN([AM_PATH_WXRC], [WXRC_CHECK([$1],[$2])])
 # generated from the m4 files accompanying Automake X.Y.
 # (This private macro should not be called outside this file.)
 AC_DEFUN([AM_AUTOMAKE_VERSION],
-[am__api_version='1.15'
+[am__api_version='1.16'
 dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to
 dnl require some minimum version.  Point them to the right macro.
-m4_if([$1], [1.15], [],
+m4_if([$1], [1.16.3], [],
       [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl
 ])
 
@@ -1622,14 +1620,14 @@ m4_define([_AM_AUTOCONF_VERSION], [])
 # Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced.
 # This function is AC_REQUIREd by AM_INIT_AUTOMAKE.
 AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION],
-[AM_AUTOMAKE_VERSION([1.15])dnl
+[AM_AUTOMAKE_VERSION([1.16.3])dnl
 m4_ifndef([AC_AUTOCONF_VERSION],
   [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl
 _AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))])
 
 # AM_AUX_DIR_EXPAND                                         -*- Autoconf -*-
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -1681,7 +1679,7 @@ am_aux_dir=`cd "$ac_aux_dir" && pwd`
 
 # AM_CONDITIONAL                                            -*- Autoconf -*-
 
-# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+# Copyright (C) 1997-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -1712,7 +1710,7 @@ AC_CONFIG_COMMANDS_PRE(
 Usually this means the macro was only invoked conditionally.]])
 fi])])
 
-# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+# Copyright (C) 1999-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -1903,13 +1901,12 @@ _AM_SUBST_NOTMAKE([am__nodep])dnl
 
 # Generate code to set up dependency tracking.              -*- Autoconf -*-
 
-# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+# Copyright (C) 1999-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
 # with or without modifications, as long as this notice is preserved.
 
-
 # _AM_OUTPUT_DEPENDENCY_COMMANDS
 # ------------------------------
 AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS],
@@ -1917,49 +1914,43 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS],
   # Older Autoconf quotes --file arguments for eval, but not when files
   # are listed without --file.  Let's play safe and only enable the eval
   # if we detect the quoting.
-  case $CONFIG_FILES in
+  # TODO: see whether this extra hack can be removed once we start
-  *\'*) eval set x "$CONFIG_FILES" ;;
+  # requiring Autoconf 2.70 or later.
-  *)   set x $CONFIG_FILES ;;
+  AS_CASE([$CONFIG_FILES],
-  esac
+          [*\'*], [eval set x "$CONFIG_FILES"],
+          [*], [set x $CONFIG_FILES])
   shift
-  for mf
+  # Used to flag and report bootstrapping failures.
+  am_rc=0
+  for am_mf
   do
     # Strip MF so we end up with the name of the file.
-    mf=`echo "$mf" | sed -e 's/:.*$//'`
+    am_mf=`AS_ECHO(["$am_mf"]) | sed -e 's/:.*$//'`
-    # Check whether this is an Automake generated Makefile or not.
+    # Check whether this is an Automake generated Makefile which includes
-    # We used to match only the files named 'Makefile.in', but
+    # dependency-tracking related rules and includes.
-    # some people rename them; so instead we look at the file content.
+    # Grep'ing the whole file directly is not great: AIX grep has a line
-    # Grep'ing the first line is not enough: some people post-process
-    # each Makefile.in and add a new line on top of each file to say so.
-    # Grep'ing the whole file is not good either: AIX grep has a line
     # limit of 2048, but all sed's we know have understand at least 4000.
-    if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then
+    sed -n 's,^am--depfiles:.*,X,p' "$am_mf" | grep X >/dev/null 2>&1 \
-      dirpart=`AS_DIRNAME("$mf")`
+      || continue
-    else
+    am_dirpart=`AS_DIRNAME(["$am_mf"])`
-      continue
+    am_filepart=`AS_BASENAME(["$am_mf"])`
-    fi
+    AM_RUN_LOG([cd "$am_dirpart" \
-    # Extract the definition of DEPDIR, am__include, and am__quote
+      && sed -e '/# am--include-marker/d' "$am_filepart" \
-    # from the Makefile without running 'make'.
+        | $MAKE -f - am--depfiles]) || am_rc=$?
-    DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
-    test -z "$DEPDIR" && continue
-    am__include=`sed -n 's/^am__include = //p' < "$mf"`
-    test -z "$am__include" && continue
-    am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
-    # Find all dependency output files, they are included files with
-    # $(DEPDIR) in their names.  We invoke sed twice because it is the
-    # simplest approach to changing $(DEPDIR) to its actual value in the
-    # expansion.
-    for file in `sed -n "
-      s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
-	 sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do
-      # Make sure the directory exists.
-      test -f "$dirpart/$file" && continue
-      fdir=`AS_DIRNAME(["$file"])`
-      AS_MKDIR_P([$dirpart/$fdir])
-      # echo "creating $dirpart/$file"
-      echo '# dummy' > "$dirpart/$file"
-    done
   done
+  if test $am_rc -ne 0; then
+    AC_MSG_FAILURE([Something went wrong bootstrapping makefile fragments
+    for automatic dependency tracking.  If GNU make was not used, consider
+    re-running the configure script with MAKE="gmake" (or whatever is
+    necessary).  You can also try re-running configure with the
+    '--disable-dependency-tracking' option to at least be able to build
+    the package (albeit without support for automatic dependency tracking).])
+  fi
+  AS_UNSET([am_dirpart])
+  AS_UNSET([am_filepart])
+  AS_UNSET([am_mf])
+  AS_UNSET([am_rc])
+  rm -f conftest-deps.mk
 }
 ])# _AM_OUTPUT_DEPENDENCY_COMMANDS
 
@@ -1968,18 +1959,17 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS],
 # -----------------------------
 # This macro should only be invoked once -- use via AC_REQUIRE.
 #
-# This code is only required when automatic dependency tracking
+# This code is only required when automatic dependency tracking is enabled.
-# is enabled.  FIXME.  This creates each '.P' file that we will
+# This creates each '.Po' and '.Plo' makefile fragment that we'll need in
-# need in order to bootstrap the dependency handling code.
+# order to bootstrap the dependency handling code.
 AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS],
 [AC_CONFIG_COMMANDS([depfiles],
      [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS],
-     [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"])
+     [AMDEP_TRUE="$AMDEP_TRUE" MAKE="${MAKE-make}"])])
-])
 
 # Do all the work for Automake.                             -*- Autoconf -*-
 
-# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+# Copyright (C) 1996-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2066,8 +2056,8 @@ AC_REQUIRE([AM_PROG_INSTALL_STRIP])dnl
 AC_REQUIRE([AC_PROG_MKDIR_P])dnl
 # For better backward compatibility.  To be removed once Automake 1.9.x
 # dies out for good.  For more background, see:
-# <http://lists.gnu.org/archive/html/automake/2012-07/msg00001.html>
+# <https://lists.gnu.org/archive/html/automake/2012-07/msg00001.html>
-# <http://lists.gnu.org/archive/html/automake/2012-07/msg00014.html>
+# <https://lists.gnu.org/archive/html/automake/2012-07/msg00014.html>
 AC_SUBST([mkdir_p], ['$(MKDIR_P)'])
 # We need awk for the "check" target (and possibly the TAP driver).  The
 # system "awk" is bad on some platforms.
@@ -2134,7 +2124,7 @@ END
 Aborting the configuration process, to ensure you take notice of the issue.
 
 You can download and install GNU coreutils to get an 'rm' implementation
-that behaves properly: <http://www.gnu.org/software/coreutils/>.
+that behaves properly: <https://www.gnu.org/software/coreutils/>.
 
 If you want to complete the configuration process using your problematic
 'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM
@@ -2176,7 +2166,7 @@ for _am_header in $config_headers :; do
 done
 echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count])
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2197,7 +2187,7 @@ if test x"${install_sh+set}" != xset; then
 fi
 AC_SUBST([install_sh])])
 
-# Copyright (C) 2003-2014 Free Software Foundation, Inc.
+# Copyright (C) 2003-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2218,7 +2208,7 @@ AC_SUBST([am__leading_dot])])
 
 # Check to see how 'make' treats includes.	            -*- Autoconf -*-
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2226,49 +2216,42 @@ AC_SUBST([am__leading_dot])])
 
 # AM_MAKE_INCLUDE()
 # -----------------
-# Check to see how make treats includes.
+# Check whether make has an 'include' directive that can support all
+# the idioms we need for our automatic dependency tracking code.
 AC_DEFUN([AM_MAKE_INCLUDE],
-[am_make=${MAKE-make}
+[AC_MSG_CHECKING([whether ${MAKE-make} supports the include directive])
-cat > confinc << 'END'
+cat > confinc.mk << 'END'
 am__doit:
-	@echo this is the am__doit target
+	@echo this is the am__doit target >confinc.out
 .PHONY: am__doit
 END
-# If we don't find an include directive, just comment out the code.
-AC_MSG_CHECKING([for style of include used by $am_make])
 am__include="#"
 am__quote=
-_am_result=none
+# BSD make does it like this.
-# First try GNU make style include.
+echo '.include "confinc.mk" # ignored' > confmf.BSD
-echo "include confinc" > confmf
+# Other make implementations (GNU, Solaris 10, AIX) do it like this.
-# Ignore all kinds of additional output from 'make'.
+echo 'include confinc.mk # ignored' > confmf.GNU
-case `$am_make -s -f confmf 2> /dev/null` in #(
+_am_result=no
-*the\ am__doit\ target*)
+for s in GNU BSD; do
-  am__include=include
+  AM_RUN_LOG([${MAKE-make} -f confmf.$s && cat confinc.out])
-  am__quote=
+  AS_CASE([$?:`cat confinc.out 2>/dev/null`],
-  _am_result=GNU
+      ['0:this is the am__doit target'],
-  ;;
+      [AS_CASE([$s],
-esac
+          [BSD], [am__include='.include' am__quote='"'],
-# Now try BSD make style include.
+          [am__include='include' am__quote=''])])
-if test "$am__include" = "#"; then
+  if test "$am__include" != "#"; then
-   echo '.include "confinc"' > confmf
+    _am_result="yes ($s style)"
-   case `$am_make -s -f confmf 2> /dev/null` in #(
+    break
-   *the\ am__doit\ target*)
+  fi
-     am__include=.include
+done
-     am__quote="\""
+rm -f confinc.* confmf.*
-     _am_result=BSD
+AC_MSG_RESULT([${_am_result}])
-     ;;
+AC_SUBST([am__include])])
-   esac
+AC_SUBST([am__quote])])
-fi
-AC_SUBST([am__include])
-AC_SUBST([am__quote])
-AC_MSG_RESULT([$_am_result])
-rm -f confinc confmf
-])
 
 # Fake the existence of programs that GNU maintainers use.  -*- Autoconf -*-
 
-# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+# Copyright (C) 1997-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2289,12 +2272,7 @@ AC_DEFUN([AM_MISSING_HAS_RUN],
 [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl
 AC_REQUIRE_AUX_FILE([missing])dnl
 if test x"${MISSING+set}" != xset; then
-  case $am_aux_dir in
+  MISSING="\${SHELL} '$am_aux_dir/missing'"
-  *\ * | *\	*)
-    MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;;
-  *)
-    MISSING="\${SHELL} $am_aux_dir/missing" ;;
-  esac
 fi
 # Use eval to expand $SHELL
 if eval "$MISSING --is-lightweight"; then
@@ -2307,7 +2285,7 @@ fi
 
 # Helper functions for option handling.                     -*- Autoconf -*-
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2336,7 +2314,7 @@ AC_DEFUN([_AM_SET_OPTIONS],
 AC_DEFUN([_AM_IF_OPTION],
 [m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])])
 
-# Copyright (C) 1999-2014 Free Software Foundation, Inc.
+# Copyright (C) 1999-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2383,7 +2361,7 @@ AC_LANG_POP([C])])
 # For backward compatibility.
 AC_DEFUN_ONCE([AM_PROG_CC_C_O], [AC_REQUIRE([AC_PROG_CC])])
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2402,7 +2380,7 @@ AC_DEFUN([AM_RUN_LOG],
 
 # Check to make sure that the build environment is sane.    -*- Autoconf -*-
 
-# Copyright (C) 1996-2014 Free Software Foundation, Inc.
+# Copyright (C) 1996-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2483,7 +2461,7 @@ AC_CONFIG_COMMANDS_PRE(
 rm -f conftest.file
 ])
 
-# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+# Copyright (C) 2009-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2543,7 +2521,7 @@ AC_SUBST([AM_BACKSLASH])dnl
 _AM_SUBST_NOTMAKE([AM_BACKSLASH])dnl
 ])
 
-# Copyright (C) 2001-2014 Free Software Foundation, Inc.
+# Copyright (C) 2001-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2571,7 +2549,7 @@ fi
 INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s"
 AC_SUBST([INSTALL_STRIP_PROGRAM])])
 
-# Copyright (C) 2006-2014 Free Software Foundation, Inc.
+# Copyright (C) 2006-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
@@ -2590,7 +2568,7 @@ AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])
 
 # Check how to create a tarball.                            -*- Autoconf -*-
 
-# Copyright (C) 2004-2014 Free Software Foundation, Inc.
+# Copyright (C) 2004-2020 Free Software Foundation, Inc.
 #
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,

configure.ac

@@ -2,7 +2,7 @@
 #
 
 AC_PREREQ([2.61])
-AC_INIT(PCem, v14, Sarah Walker <pcem@pcem-emulator.co.uk>, pcem)
+AC_INIT(PCem, v17, Sarah Walker <pcem@pcem-emulator.co.uk>, pcem)
 
 AC_CANONICAL_HOST
 
@@ -27,12 +27,12 @@ AC_MSG_CHECKING([whether to enable debugging])
 AC_ARG_ENABLE(debug,
           AC_HELP_STRING([--enable-debug], [build debug executable]))
 if test "$enable_debug" = "yes"; then
-   CFLAGS="-Wall -O0 -g -D_DEBUG"
+   CFLAGS="$CFLAGS -Wall -O0 -g -D_DEBUG -fcommon"
-   CXXFLAGS="-Wall -O0 -g -D_DEBUG"
+   CXXFLAGS="$CXXFLAGS -Wall -O0 -g -D_DEBUG -fcommon"
    AC_MSG_RESULT([yes])
 else
-   CFLAGS="-O3"
+   CFLAGS="$CFLAGS -O3 -fcommon"
-   CXXFLAGS="-O3"
+   CXXFLAGS="$CXXFLAGS -O3 -fcommon"
    AC_MSG_RESULT([no])
 fi
 
@@ -140,6 +140,7 @@ case "$host" in
        LIBS="$LIBS -framework OpenGL"
        LIBS="$LIBS -framework OpenAL"
        build_macosx="yes"
+       CFLAGS="$CFLAGS -DHAVE_UNISTD_H"
        ;;
     *-*-cygwin* | *-*-mingw32*)
        AC_CHECK_LIB([opengl32], [main], [], \
@@ -159,6 +160,20 @@ case "$host" in
            [echo "You need to install the OpenAL library."
            exit -1])
        build_linux="yes"
+       CFLAGS="$CFLAGS -DHAVE_UNISTD_H"
+       ;;
+    *-*-freebsd*)
+       CFLAGS="$CFLAGS -I/usr/local/include"
+       CXXFLAGS="$CXXFLAGS -I/usr/local/include"
+       LDFLAGS="$LDFLAGS -L/usr/local/lib"
+       AC_CHECK_LIB([GL], [glGetError], [], \
+           [echo "You need to install the OpenGL library."
+           exit -1])
+       AC_CHECK_LIB([openal], [alGetError], [], \
+           [echo "You need to install the OpenAL library."
+           exit -1])
+       build_other="yes"
+       CFLAGS="$CFLAGS -DHAVE_UNISTD_H"
        ;;
     *)
        AC_CHECK_LIB([GL], [glGetError], [], \
@@ -171,6 +186,7 @@ case "$host" in
        ;;
 esac
 
+CFLAGS="$CFLAGS $SDL_CFLAGS"
 LIBS="$LIBS $WX_LIBS $SDL_LIBS"
 
 AM_CONDITIONAL(OS_LINUX, [test "$build_linux" = "yes"])

src/386.c

@@ -165,6 +165,8 @@ void exec386(int cycs)
 //                pclog("%i %02X\n", ins, ram[8]);
                 while (cycdiff < cycle_period)
                 {
+                        int ins_cycles = cycles;
+                        
                 cpu_state.oldpc = cpu_state.pc;
                 cpu_state.op32 = use32;
                 
@@ -194,7 +196,7 @@ void exec386(int cycs)
                         flags_rebuild();
 //                        pclog("Abort\n");
 //                        if (CS == 0x228) pclog("Abort at %04X:%04X - %i %i %i\n",CS,pc,notpresent,nullseg,abrt);
-                        tempi = cpu_state.abrt;
+                        tempi = cpu_state.abrt & ABRT_MASK;
                         cpu_state.abrt = 0;
                         x86_doabrt(tempi);
                         if (cpu_state.abrt)
@@ -212,9 +214,13 @@ void exec386(int cycs)
                                 }
                         }
                 }
-                cycdiff=oldcyc-cycles;
 
-                if (trap)
+                if (cpu_state.smi_pending)
+                {
+                        cpu_state.smi_pending = 0;
+                        x86_smi_enter();
+                }
+                else if (trap)
                 {
                         flags_rebuild();
 //                        oldpc=pc;
@@ -281,6 +287,11 @@ void exec386(int cycs)
                 ins++;
                 insc++;
 
+                ins_cycles -= cycles;
+                tsc += ins_cycles;
+
+                cycdiff=oldcyc-cycles;
+
                 if (timetolive)
                 {
                         timetolive--;
@@ -289,7 +300,6 @@ void exec386(int cycs)
                 }
                 }
                 
-                tsc += cycdiff;
 		if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t)tsc))
 			timer_process();
         }

src/386_common.c

@@ -9,6 +9,9 @@ x86seg gdt, ldt, idt, tr;
 uint32_t cr2, cr3, cr4;
 uint32_t dr[8];
 
+uint16_t sysenter_cs;
+uint32_t sysenter_eip, sysenter_esp;
+
 uint32_t use32;
 int stack32;
 int optype;

src/386_common.h

@@ -19,7 +19,10 @@ int checkio(int port);
                                 if (cpu_state.abrt) return 1; \
                                 if (tempi) \
                                 { \
-                                        x86gpf(NULL,0); \
+                                        if (cpu_state.eflags & VM_FLAG) \
+                                                x86gpf_expected(NULL,0); \
+                                        else \
+                                                x86gpf(NULL,0); \
                                         return 1; \
                                 } \
                         }

src/386_dynarec.c

@@ -1,6 +1,9 @@
 #include <stdio.h>
 #include <stdint.h>
 #include <stdlib.h>
+#if defined(__APPLE__) && defined(__aarch64__)
+#include <pthread.h>
+#endif
 #include "ibm.h"
 #include "x86.h"
 #include "x86_ops.h"
@@ -212,6 +215,8 @@ static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int
         }
         
         prefetch_prefixes = 0;
+        if (prefetch_bytes > 16)
+                prefetch_bytes = 16;
 }
 
 static void prefetch_flush()
@@ -236,11 +241,344 @@ static void prefetch_flush()
 #define CACHE_ON() (!(cr0 & (1 << 30)) && !(cpu_state.flags & T_FLAG))
 //#define CACHE_ON() 0
 
-static int cycles_main = 0;
+int cpu_end_block_after_ins = 0;
+
+
+static inline void exec_interpreter(void)
+{
+        cpu_block_end = 0;
+        x86_was_reset = 0;
+//        if (output) pclog("Interpret block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  %04x\n", CS, pc, AX, BX, CX, DX, SI, DI, SP);
+        while (!cpu_block_end)
+        {
+                cpu_state.oldpc = cpu_state.pc;
+                cpu_state.op32 = use32;
+
+                cpu_state.ea_seg = &cpu_state.seg_ds;
+                cpu_state.ssegs = 0;
+
+                fetchdat = fastreadl(cs + cpu_state.pc);
+
+                if (!cpu_state.abrt)
+                {
+                        uint8_t opcode = fetchdat & 0xFF;
+                        fetchdat >>= 8;
+                        trap = cpu_state.flags & T_FLAG;
+
+//                        if (output == 3)
+//                                pclog("int %04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X %f  %02X%02X %02X%02X\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0x8f13f], ram[0x8f13e], ram[0x8f141], ram[0x8f140]);
+
+                        cpu_state.pc++;
+                        x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
+                }
+
+                if (((cs + cpu_state.pc) >> 12) != pccache)
+                        CPU_BLOCK_END();
+
+                if (cpu_state.abrt)
+                        CPU_BLOCK_END();
+                if (cpu_state.smi_pending)
+                        CPU_BLOCK_END();
+                if (trap)
+                        CPU_BLOCK_END();
+                if (nmi && nmi_enable && nmi_mask)
+                        CPU_BLOCK_END();
+                if (cpu_end_block_after_ins)
+                {
+                        cpu_end_block_after_ins--;
+                        if (!cpu_end_block_after_ins)
+                                CPU_BLOCK_END();
+                }
+
+                ins++;
+                insc++;
+        }
+
+        if (trap)
+        {
+                trap = 0;
+                cpu_state.oldpc = cpu_state.pc;
+                x86_int(1);
+        }
+
+        cpu_end_block_after_ins = 0;
+}
+
+static inline void exec_recompiler(void)
+{
+        uint32_t phys_addr = get_phys(cs+cpu_state.pc);
+        int hash = HASH(phys_addr);
+        codeblock_t *block = &codeblock[codeblock_hash[hash]];
+        int valid_block = 0;
+
+        if (!cpu_state.abrt)
+        {
+                page_t *page = &pages[phys_addr >> 12];
+
+                /*Block must match current CS, PC, code segment size,
+                  and physical address. The physical address check will
+                  also catch any page faults at this stage*/
+                valid_block = (block->pc == cs + cpu_state.pc) && (block->_cs == cs) &&
+                              (block->phys == phys_addr) && !((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
+                              ((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
+                if (!valid_block)
+                {
+                        uint64_t mask = (uint64_t)1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
+                        int byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
+                        uint64_t byte_mask = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
+
+                        if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
+                        {
+                                /*Walk page tree to see if we find the correct block*/
+                                codeblock_t *new_block = codeblock_tree_find(phys_addr, cs);
+                                if (new_block)
+                                {
+                                        valid_block = (new_block->pc == cs + cpu_state.pc) && (new_block->_cs == cs) &&
+                                                      (new_block->phys == phys_addr) && !((new_block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
+                                                      ((new_block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
+                                        if (valid_block)
+                                        {
+                                                block = new_block;
+                                                codeblock_hash[hash] = get_block_nr(block);
+                                        }
+                                }
+                        }
+                }
+
+                if (valid_block && (block->page_mask & *block->dirty_mask))
+                {
+                        codegen_check_flush(page, page->dirty_mask, phys_addr);
+                        if (block->pc == BLOCK_PC_INVALID)
+                                valid_block = 0;
+                        else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
+                                block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
+                }
+                if (valid_block && block->page_mask2)
+                {
+                        /*We don't want the second page to cause a page
+                          fault at this stage - that would break any
+                          code crossing a page boundary where the first
+                          page is present but the second isn't. Instead
+                          allow the first page to be interpreted and for
+                          the page fault to occur when the page boundary
+                          is actually crossed.*/
+                        uint32_t phys_addr_2 = get_phys_noabrt(block->pc + ((block->flags & CODEBLOCK_BYTE_MASK) ? 0x40 : 0x400));
+                        page_t *page_2 = &pages[phys_addr_2 >> 12];
+                        if ((block->phys_2 ^ phys_addr_2) & ~0xfff)
+                                valid_block = 0;
+                        else if (block->page_mask2 & *block->dirty_mask2)
+                        {
+                                codegen_check_flush(page_2, page_2->dirty_mask, phys_addr_2);
+                                if (block->pc == BLOCK_PC_INVALID)
+                                        valid_block = 0;
+                                else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
+                                        block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
+                        }
+                }
+                if (valid_block && (block->flags & CODEBLOCK_IN_DIRTY_LIST))
+                {
+                        block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
+                        if (block->flags & CODEBLOCK_BYTE_MASK)
+                                block->flags |= CODEBLOCK_NO_IMMEDIATES;
+                        else
+                                block->flags |= CODEBLOCK_BYTE_MASK;
+                }
+                if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED) && (block->flags & CODEBLOCK_STATIC_TOP) && block->TOP != (cpu_state.TOP & 7))
+                {
+                        /*FPU top-of-stack does not match the value this block was compiled
+                          with, re-compile using dynamic top-of-stack*/
+                        block->flags &= ~(CODEBLOCK_STATIC_TOP | CODEBLOCK_WAS_RECOMPILED);
+                }
+        }
+
+        if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED))
+        {
+                void (*code)() = (void *)&block->data[BLOCK_START];
+
+//                if (output) pclog("Run block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%08x %04x  %08x %08x  %016llx %08x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, get_phys(cs+pc), block->phys, block->page_mask, block->endpc);
+
+                inrecomp=1;
+                code();
+                inrecomp=0;
+
+                cpu_recomp_blocks++;
+        }
+        else if (valid_block && !cpu_state.abrt)
+        {
+                uint32_t start_pc = cs+cpu_state.pc;
+                const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
+
+                cpu_block_end = 0;
+                x86_was_reset = 0;
+
+                cpu_new_blocks++;
+
+#if defined(__APPLE__) && defined(__aarch64__)
+                pthread_jit_write_protect_np(0);
+#endif
+                codegen_block_start_recompile(block);
+                codegen_in_recompile = 1;
+
+//                if (output) pclog("Recompile block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%04x %04x  %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
+                while (!cpu_block_end)
+                {
+                        cpu_state.oldpc = cpu_state.pc;
+                        cpu_state.op32 = use32;
+
+                        cpu_state.ea_seg = &cpu_state.seg_ds;
+                        cpu_state.ssegs = 0;
+
+                        fetchdat = fastreadl(cs + cpu_state.pc);
+
+                        if (!cpu_state.abrt)
+                        {
+                                uint8_t opcode = fetchdat & 0xFF;
+                                fetchdat >>= 8;
+
+//                                if (output == 3)
+//                                        pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X  %08x %08x\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, cs+pc, pccache);
+
+                                cpu_state.pc++;
+
+                                codegen_generate_call(opcode, x86_opcodes[(opcode | cpu_state.op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
+
+                                x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
+
+                                if (x86_was_reset)
+                                        break;
+                        }
+
+                        /*Cap source code at 4000 bytes per block; this
+                          will prevent any block from spanning more than
+                          2 pages. In practice this limit will never be
+                          hit, as host block size is only 2kB*/
+                        if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
+                                CPU_BLOCK_END();
+                        if (cpu_state.flags & T_FLAG)
+                                CPU_BLOCK_END();
+                        if (cpu_state.smi_pending)
+                                CPU_BLOCK_END();
+                        if (nmi && nmi_enable && nmi_mask)
+                                CPU_BLOCK_END();
+
+                        if (cpu_end_block_after_ins)
+                        {
+                                cpu_end_block_after_ins--;
+                                if (!cpu_end_block_after_ins)
+                                        CPU_BLOCK_END();
+                        }
+
+                        if (cpu_state.abrt)
+                        {
+                                if (!(cpu_state.abrt & ABRT_EXPECTED))
+                                        codegen_block_remove();
+                                CPU_BLOCK_END();
+                        }
+
+                        ins++;
+                        insc++;
+                }
+                cpu_end_block_after_ins = 0;
+
+                if ((!cpu_state.abrt || (cpu_state.abrt & ABRT_EXPECTED)) && !x86_was_reset)
+                        codegen_block_end_recompile(block);
+
+                if (x86_was_reset)
+                        codegen_reset();
+
+                codegen_in_recompile = 0;
+#if defined(__APPLE__) && defined(__aarch64__)
+                pthread_jit_write_protect_np(1);
+#endif
+        }
+        else if (!cpu_state.abrt)
+        {
+                /*Mark block but do not recompile*/
+                uint32_t start_pc = cs+cpu_state.pc;
+                const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
+
+                cpu_block_end = 0;
+                x86_was_reset = 0;
+
+                codegen_block_init(phys_addr);
+
+//                if (output) pclog("Recompile block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%04x %04x  %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
+                while (!cpu_block_end)
+                {
+                        cpu_state.oldpc = cpu_state.pc;
+                        cpu_state.op32 = use32;
+
+                        cpu_state.ea_seg = &cpu_state.seg_ds;
+                        cpu_state.ssegs = 0;
+
+                        codegen_endpc = (cs + cpu_state.pc) + 8;
+                        fetchdat = fastreadl(cs + cpu_state.pc);
+
+                        if (!cpu_state.abrt)
+                        {
+                                uint8_t opcode = fetchdat & 0xFF;
+                                fetchdat >>= 8;
+
+//                                if (output == 3)
+//                                        pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X  %08x %08x\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, cs+pc, pccache);
+
+                                cpu_state.pc++;
+
+                                x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
+
+                                if (x86_was_reset)
+                                        break;
+                        }
+
+                        /*Cap source code at 4000 bytes per block; this
+                          will prevent any block from spanning more than
+                          2 pages. In practice this limit will never be
+                          hit, as host block size is only 2kB*/
+                        if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
+                                CPU_BLOCK_END();
+                        if (cpu_state.flags & T_FLAG)
+                                CPU_BLOCK_END();
+                        if (cpu_state.smi_pending)
+                                CPU_BLOCK_END();
+                        if (nmi && nmi_enable && nmi_mask)
+                                CPU_BLOCK_END();
+
+                        if (cpu_end_block_after_ins)
+                        {
+                                cpu_end_block_after_ins--;
+                                if (!cpu_end_block_after_ins)
+                                        CPU_BLOCK_END();
+                        }
+
+                        if (cpu_state.abrt)
+                        {
+                                if (!(cpu_state.abrt & ABRT_EXPECTED))
+                                        codegen_block_remove();
+                                CPU_BLOCK_END();
+                        }
+
+                        ins++;
+                        insc++;
+                }
+                cpu_end_block_after_ins = 0;
+
+//                if (!cpu_state.abrt && !x86_was_reset)
+                if ((!cpu_state.abrt || (cpu_state.abrt & ABRT_EXPECTED)) && !x86_was_reset)
+                        codegen_block_end();
+
+                if (x86_was_reset)
+                        codegen_reset();
+        }
+        else
+                cpu_state.oldpc = cpu_state.pc;
+
+}
+
+
+int cycles_main = 0;
 void exec386_dynarec(int cycs)
 {
         uint8_t temp;
-        uint32_t addr;
         int tempi;
         int cycdiff;
         int oldcyc;
@@ -259,303 +597,14 @@ void exec386_dynarec(int cycs)
                         oldcyc=cycles;
 //                        if (output && CACHE_ON()) pclog("Block %04x:%04x %04x:%08x\n", CS, pc, SS,ESP);
                         if (!CACHE_ON()) /*Interpret block*/
-                        {
+                                exec_interpreter();
-                                cpu_block_end = 0;
-                                x86_was_reset = 0;
-//                                if (output) pclog("Interpret block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  %04x\n", CS, pc, AX, BX, CX, DX, SI, DI, SP);
-                                while (!cpu_block_end)
-                                {
-                                        cpu_state.oldpc = cpu_state.pc;
-                                        cpu_state.op32 = use32;
-
-                                        cpu_state.ea_seg = &cpu_state.seg_ds;
-                                        cpu_state.ssegs = 0;
-                
-                                        fetchdat = fastreadl(cs + cpu_state.pc);
-
-                                        if (!cpu_state.abrt)
-                                        {
-                                                uint8_t opcode = fetchdat & 0xFF;
-                                                fetchdat >>= 8;
-                                                trap = cpu_state.flags & T_FLAG;
-
-//                                                if (output == 3)
-//                                                        pclog("int %04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X %f  %02X%02X %02X%02X\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0x8f13f], ram[0x8f13e], ram[0x8f141], ram[0x8f140]);
-
-                                                cpu_state.pc++;
-                                                x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
-                                        }
-
-                                        if (((cs + cpu_state.pc) >> 12) != pccache)
-                                                CPU_BLOCK_END();
-
-                                        if (cpu_state.abrt)
-                                                CPU_BLOCK_END();
-                                        if (trap)
-                                                CPU_BLOCK_END();
-                                        if (nmi && nmi_enable && nmi_mask)
-                                                CPU_BLOCK_END();
-                                        
-                                        ins++;
-                                        insc++;
-                                }
-                        }
                         else
-                        {
+                                exec_recompiler();
-                                uint32_t phys_addr = get_phys(cs+cpu_state.pc);
-                                int hash = HASH(phys_addr);
-                                codeblock_t *block = &codeblock[codeblock_hash[hash]];
-                                int valid_block = 0;
-
-                                if (!cpu_state.abrt)
-                                {
-                                        page_t *page = &pages[phys_addr >> 12];
-
-                                        /*Block must match current CS, PC, code segment size,
-                                          and physical address. The physical address check will
-                                          also catch any page faults at this stage*/
-                                        valid_block = (block->pc == cs + cpu_state.pc) && (block->_cs == cs) &&
-                                                      (block->phys == phys_addr) && !((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
-                                                      ((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
-                                        if (!valid_block)
-                                        {
-                                                uint64_t mask = (uint64_t)1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
-                                                int byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
-                                                uint64_t byte_mask = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
-
-                                                if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
-                                                {
-                                                        /*Walk page tree to see if we find the correct block*/
-                                                        codeblock_t *new_block = codeblock_tree_find(phys_addr, cs);
-                                                        if (new_block)
-                                                        {
-                                                                valid_block = (new_block->pc == cs + cpu_state.pc) && (new_block->_cs == cs) &&
-                                                                                (new_block->phys == phys_addr) && !((new_block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
-                                                                                ((new_block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
-                                                                if (valid_block)
-                                                                {
-                                                                        block = new_block;
-                                                                        codeblock_hash[hash] = get_block_nr(block);
-                                                                }
-                                                        }
-                                                }
-                                        }
-
-                                        if (valid_block && (block->page_mask & *block->dirty_mask))
-                                        {
-                                                codegen_check_flush(page, page->dirty_mask, phys_addr);
-                                                if (block->pc == BLOCK_PC_INVALID)
-                                                        valid_block = 0;
-                                                else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
-                                                        block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
-                                        }
-                                        if (valid_block && block->page_mask2)
-                                        {
-                                                /*We don't want the second page to cause a page
-                                                  fault at this stage - that would break any
-                                                  code crossing a page boundary where the first
-                                                  page is present but the second isn't. Instead
-                                                  allow the first page to be interpreted and for
-                                                  the page fault to occur when the page boundary
-                                                  is actually crossed.*/
-                                                uint32_t phys_addr_2 = get_phys_noabrt(block->pc + ((block->flags & CODEBLOCK_BYTE_MASK) ? 0x40 : 0x400));
-                                                page_t *page_2 = &pages[phys_addr_2 >> 12];
-                                                if ((block->phys_2 ^ phys_addr_2) & ~0xfff)
-                                                        valid_block = 0;
-                                                else if (block->page_mask2 & *block->dirty_mask2)
-                                                {
-                                                        codegen_check_flush(page_2, page_2->dirty_mask, phys_addr_2);
-                                                        if (block->pc == BLOCK_PC_INVALID)
-                                                                valid_block = 0;
-                                                        else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
-                                                                block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
-                                                }
-                                        }
-                                        if (valid_block && (block->flags & CODEBLOCK_IN_DIRTY_LIST))
-                                        {
-                                                block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
-                                                if (block->flags & CODEBLOCK_BYTE_MASK)
-                                                        block->flags |= CODEBLOCK_NO_IMMEDIATES;
-                                                else
-                                                        block->flags |= CODEBLOCK_BYTE_MASK;
-                                        }
-                                        if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED) && (block->flags & CODEBLOCK_STATIC_TOP) && block->TOP != (cpu_state.TOP & 7))
-                                        {
-                                                /*FPU top-of-stack does not match the value this block was compiled
-                                                  with, re-compile using dynamic top-of-stack*/
-                                                block->flags &= ~(CODEBLOCK_STATIC_TOP | CODEBLOCK_WAS_RECOMPILED);
-                                        }
-                                }
-
-                                if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED))
-                                {
-                                        void (*code)() = (void *)&block->data[BLOCK_START];
-
-//                                        if (output) pclog("Run block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%08x %04x  %08x %08x  %016llx %08x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, get_phys(cs+pc), block->phys, block->page_mask, block->endpc);
-
-                                        inrecomp=1;
-                                        code();
-                                        inrecomp=0;
-
-                                        cpu_recomp_blocks++;
-                                }
-                                else if (valid_block && !cpu_state.abrt)
-                                {
-                                        uint32_t start_pc = cs+cpu_state.pc;
-                                        const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
-                                        
-                                        cpu_block_end = 0;
-                                        x86_was_reset = 0;
-
-                                        cpu_new_blocks++;
-                        
-                                        codegen_block_start_recompile(block);
-                                        codegen_in_recompile = 1;
-
-//                                        if (output) pclog("Recompile block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%04x %04x  %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
-                                        while (!cpu_block_end)
-                                        {
-                                                cpu_state.oldpc = cpu_state.pc;
-                                                cpu_state.op32 = use32;
-
-                                                cpu_state.ea_seg = &cpu_state.seg_ds;
-                                                cpu_state.ssegs = 0;
-                
-                                                fetchdat = fastreadl(cs + cpu_state.pc);
-
-                                                if (!cpu_state.abrt)
-                                                {
-                                                        uint8_t opcode = fetchdat & 0xFF;
-                                                        fetchdat >>= 8;
-                                                        
-                                                        trap = cpu_state.flags & T_FLAG;
-
-//                                                        if (output == 3)
-//                                                                pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X  %08x %08x\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, cs+pc, pccache);
-
-                                                        cpu_state.pc++;
-                                                
-                                                        codegen_generate_call(opcode, x86_opcodes[(opcode | cpu_state.op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
-
-                                                        x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
-
-                                                        if (x86_was_reset)
-                                                                break;
-                                                }
-
-                                                /*Cap source code at 4000 bytes per block; this
-                                                  will prevent any block from spanning more than
-                                                  2 pages. In practice this limit will never be
-                                                  hit, as host block size is only 2kB*/
-                                                if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
-                                                        CPU_BLOCK_END();
-                                        
-                                                if (trap)
-                                                        CPU_BLOCK_END();
-
-                                                if (nmi && nmi_enable && nmi_mask)
-                                                        CPU_BLOCK_END();
-
-                                                if (cpu_state.abrt)
-                                                {
-                                                        codegen_block_remove();
-                                                        CPU_BLOCK_END();
-                                                }
-
-                                                ins++;
-                                                insc++;
-                                        }
-                        
-                                        if (!cpu_state.abrt && !x86_was_reset)
-                                                codegen_block_end_recompile(block);
-                        
-                                        if (x86_was_reset)
-                                                codegen_reset();
-
-                                        codegen_in_recompile = 0;
-                                }
-                                else if (!cpu_state.abrt)
-                                {
-                                        /*Mark block but do not recompile*/
-                                        uint32_t start_pc = cs+cpu_state.pc;
-                                        const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
-
-                                        cpu_block_end = 0;
-                                        x86_was_reset = 0;
-
-                                        codegen_block_init(phys_addr);
-
-//                                        if (output) pclog("Recompile block at %04x:%04x  %04x %04x %04x %04x  %04x %04x  ESP=%04x %04x  %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
-                                        while (!cpu_block_end)
-                                        {
-                                                cpu_state.oldpc = cpu_state.pc;
-                                                cpu_state.op32 = use32;
-
-                                                cpu_state.ea_seg = &cpu_state.seg_ds;
-                                                cpu_state.ssegs = 0;
-                
-                                                codegen_endpc = (cs + cpu_state.pc) + 8;
-                                                fetchdat = fastreadl(cs + cpu_state.pc);
-
-                                                if (!cpu_state.abrt)
-                                                {
-                                                        uint8_t opcode = fetchdat & 0xFF;
-                                                        fetchdat >>= 8;
-
-                                                        trap = cpu_state.flags & T_FLAG;
-
-//                                                        if (output == 3)
-//                                                                pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X  %08X %i %i %02X %02X %02X   %02X %02X  %08x %08x\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, cs+pc, pccache);
-
-                                                        cpu_state.pc++;
-                                                
-                                                        x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
-
-                                                        if (x86_was_reset)
-                                                                break;
-                                                }
-
-                                                /*Cap source code at 4000 bytes per block; this
-                                                  will prevent any block from spanning more than
-                                                  2 pages. In practice this limit will never be
-                                                  hit, as host block size is only 2kB*/
-                                                if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
-                                                        CPU_BLOCK_END();
-                                        
-                                                if (trap)
-                                                        CPU_BLOCK_END();
-
-                                                if (nmi && nmi_enable && nmi_mask)
-                                                        CPU_BLOCK_END();
-
-                                                if (cpu_state.abrt)
-                                                {
-                                                        codegen_block_remove();
-                                                        CPU_BLOCK_END();
-                                                }
-
-                                                ins++;
-                                                insc++;
-                                        }
-                        
-                                        if (!cpu_state.abrt && !x86_was_reset)
-                                                codegen_block_end();
-                        
-                                        if (x86_was_reset)
-                                                codegen_reset();
-                                }
-                                else
-                                        cpu_state.oldpc = cpu_state.pc;
-
-                        }
-
-                        cycdiff=oldcyc-cycles;
-                        tsc += cycdiff;
                 
                         if (cpu_state.abrt)
                         {
                                 flags_rebuild();
-                                tempi = cpu_state.abrt;
+                                tempi = cpu_state.abrt & ABRT_MASK;
                                 cpu_state.abrt = 0;
                                 x86_doabrt(tempi);
                                 if (cpu_state.abrt)
@@ -574,26 +623,10 @@ void exec386_dynarec(int cycs)
                                 }
                         }
                 
-                        if (trap)
+                        if (cpu_state.smi_pending)
                         {
-                                trap = 0;
+                                cpu_state.smi_pending = 0;
-                                flags_rebuild();
+                                x86_smi_enter();
-                                if (msw&1)
-                                {
-                                        pmodeint(1,0);
-                                }
-                                else
-                                {
-                                        writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
-                                        writememw(ss,(SP-4)&0xFFFF,CS);
-                                        writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
-                                        SP-=6;
-                                        addr = (1 << 2) + idt.base;
-                                        cpu_state.flags &= ~I_FLAG;
-                                        cpu_state.flags &= ~T_FLAG;
-                                        cpu_state.pc=readmemw(0,addr);
-                                        loadcs(readmemw(0,addr+2));
-                                }
                         }
                         else if (nmi && nmi_enable && nmi_mask)
                         {
@@ -612,27 +645,14 @@ void exec386_dynarec(int cycs)
                                 temp=picinterrupt();
                                 if (temp!=0xFF)
                                 {
+                                        cpu_state.oldpc = cpu_state.pc;
+                                        x86_int(temp);
 //                                        pclog("IRQ %02X %04X:%04X %04X:%04X\n", temp, SS, SP, CS, pc);
-                                        CPU_BLOCK_END();
-                                        flags_rebuild();
-                                        if (msw&1)
-                                        {
-                                                pmodeint(temp,0);
-                                        }
-                                        else
-                                        {
-                                                writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
-                                                writememw(ss,(SP-4)&0xFFFF,CS);
-                                                writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
-                                                SP-=6;
-                                                addr=temp<<2;
-                                                cpu_state.flags &= ~I_FLAG;
-                                                cpu_state.flags &= ~T_FLAG;
-                                                cpu_state.pc=readmemw(0,addr);
-                                                loadcs(readmemw(0,addr+2));
-                                        }
                                 }
                         }
+
+                        cycdiff=oldcyc-cycles;
+                        tsc += cycdiff;
                 }
         
 		if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t)tsc))

src/386_ops.h

@@ -119,6 +119,7 @@ static int ILLEGAL(uint32_t fetchdat)
 #include "x86_ops_bit.h"
 #include "x86_ops_bitscan.h"
 #include "x86_ops_call.h"
+#include "x86_ops_cyrix.h"
 #include "x86_ops_flag.h"
 #include "x86_ops_fpu.h"
 #include "x86_ops_inc_dec.h"
@@ -280,7 +281,7 @@ OpFn OP_TABLE(386_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -302,7 +303,7 @@ OpFn OP_TABLE(386_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -324,7 +325,7 @@ OpFn OP_TABLE(386_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -346,7 +347,7 @@ OpFn OP_TABLE(386_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -371,7 +372,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -381,7 +382,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
 
 /*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -393,7 +394,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -403,7 +404,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
 
 /*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -415,7 +416,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -425,7 +426,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
 
 /*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -437,7 +438,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -447,7 +448,7 @@ OpFn OP_TABLE(winchip_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
 
 /*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -462,7 +463,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opPREFETCH_a16, opFEMMS,        op3DNOW_a16,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -472,7 +473,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
 
 /*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -484,7 +485,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opPREFETCH_a16, opFEMMS,        op3DNOW_a16,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -494,7 +495,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
 
 /*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -506,7 +507,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opPREFETCH_a32, opFEMMS,        op3DNOW_a32,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -516,7 +517,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
 
 /*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -528,7 +529,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 /*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        opPREFETCH_a32, opFEMMS,        op3DNOW_a32,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -538,7 +539,7 @@ OpFn OP_TABLE(winchip2_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
 
 /*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -563,7 +564,7 @@ OpFn OP_TABLE(pentium_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
 
 /*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -585,7 +586,7 @@ OpFn OP_TABLE(pentium_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
 
 /*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -607,7 +608,7 @@ OpFn OP_TABLE(pentium_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
 
 /*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -629,7 +630,98 @@ OpFn OP_TABLE(pentium_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
+
+/*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+};
+
+OpFn OP_TABLE(c6x86_0f)[1024] =
+{
+        /*16-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     opSMINT,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
+
+/*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     opSMINT,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
+
+/*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*16-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a32,     opRSDC_a32,     opSVLDT_a32,    opRSLDT_a32,    opSVTS_a32,     opRSTS_a32,     opSMINT,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
+
+/*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a32,     opRSDC_a32,     opSVLDT_a32,    opRSLDT_a32,    opSVTS_a32,     opRSTS_a32,     opSMINT,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
 
 /*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -654,7 +746,7 @@ OpFn OP_TABLE(pentiummmx_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
 
 /*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -676,7 +768,7 @@ OpFn OP_TABLE(pentiummmx_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
 
 /*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -698,7 +790,7 @@ OpFn OP_TABLE(pentiummmx_0f)[1024] =
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
 
 /*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -720,7 +812,7 @@ OpFn OP_TABLE(pentiummmx_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
 
 /*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -736,16 +828,16 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
 /*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        opRDSHR_a16,    opWRSHR_a16,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  opCMOVO_w_a16,  opCMOVNO_w_a16, opCMOVB_w_a16,  opCMOVNB_w_a16, opCMOVE_w_a16,  opCMOVNE_w_a16, opCMOVBE_w_a16, opCMOVNBE_w_a16,opCMOVS_w_a16,  opCMOVNS_w_a16, opCMOVP_w_a16,  opCMOVNP_w_a16, opCMOVL_w_a16,  opCMOVNL_w_a16, opCMOVLE_w_a16, opCMOVNLE_w_a16,
 /*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*60*/  opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16,  opPCMPGTW_a16,  opPCMPGTD_a16,  opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
-/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     opMOVD_mm_l_a16_cx,opMOVQ_mm_q_a16,
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
 
 /*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -758,16 +850,16 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
 /*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        opRDSHR_a16,    opWRSHR_a16,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  opCMOVO_l_a16,  opCMOVNO_l_a16, opCMOVB_l_a16,  opCMOVNB_l_a16, opCMOVE_l_a16,  opCMOVNE_l_a16, opCMOVBE_l_a16, opCMOVNBE_l_a16,opCMOVS_l_a16,  opCMOVNS_l_a16, opCMOVP_l_a16,  opCMOVNP_l_a16, opCMOVL_l_a16,  opCMOVNL_l_a16, opCMOVLE_l_a16, opCMOVNLE_l_a16,
 /*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*60*/  opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16,  opPCMPGTW_a16,  opPCMPGTD_a16,  opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
-/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     opMOVD_mm_l_a16_cx,opMOVQ_mm_q_a16,
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
 /*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
 
 /*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -780,16 +872,16 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
 /*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        opRDSHR_a32,    opWRSHR_a32,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  opCMOVO_w_a32,  opCMOVNO_w_a32, opCMOVB_w_a32,  opCMOVNB_w_a32, opCMOVE_w_a32,  opCMOVNE_w_a32, opCMOVBE_w_a32, opCMOVNBE_w_a32,opCMOVS_w_a32,  opCMOVNS_w_a32, opCMOVP_w_a32,  opCMOVNP_w_a32, opCMOVL_w_a32,  opCMOVNL_w_a32, opCMOVLE_w_a32, opCMOVNLE_w_a32,
 /*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*60*/  opPUNPCKLBW_a32,opPUNPCKLWD_a32,opPUNPCKLDQ_a32,opPACKSSWB_a32, opPCMPGTB_a32,  opPCMPGTW_a32,  opPCMPGTD_a32,  opPACKUSWB_a32, opPUNPCKHBW_a32,opPUNPCKHWD_a32,opPUNPCKHDQ_a32,opPACKSSDW_a32, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a32,opMOVQ_q_mm_a32,
-/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a32,  opPCMPEQW_a32,  opPCMPEQD_a32,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a32,opMOVQ_mm_q_a32,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a32,  opPCMPEQW_a32,  opPCMPEQD_a32,  opEMMS,         opSVDC_a32,     opRSDC_a32,     opSVLDT_a32,    opRSLDT_a32,    opSVTS_a32,     opRSTS_a32,     opMOVD_mm_l_a32_cx,opMOVQ_mm_q_a32,
 
 /*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     ILLEGAL,        opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
 
 /*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
@@ -802,7 +894,189 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
 /*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
-/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        ILLEGAL,        ILLEGAL,        opRDSHR_a32,    opWRSHR_a32,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_l_a32,  opCMOVNO_l_a32, opCMOVB_l_a32,  opCMOVNB_l_a32, opCMOVE_l_a32,  opCMOVNE_l_a32, opCMOVBE_l_a32, opCMOVNBE_l_a32,opCMOVS_l_a32,  opCMOVNS_l_a32, opCMOVP_l_a32,  opCMOVNP_l_a32, opCMOVL_l_a32,  opCMOVNL_l_a32, opCMOVLE_l_a32, opCMOVNLE_l_a32,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  opPUNPCKLBW_a32,opPUNPCKLWD_a32,opPUNPCKLDQ_a32,opPACKSSWB_a32, opPCMPGTB_a32,  opPCMPGTW_a32,  opPCMPGTD_a32,  opPACKUSWB_a32, opPUNPCKHBW_a32,opPUNPCKHWD_a32,opPUNPCKHDQ_a32,opPACKSSDW_a32, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a32,opMOVQ_q_mm_a32,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a32,  opPCMPEQW_a32,  opPCMPEQD_a32,  opEMMS,         opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     opMOVD_mm_l_a32_cx,opMOVQ_mm_q_a32,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
+
+/*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        opPSRLW_a32,    opPSRLD_a32,    opPSRLQ_a32,    ILLEGAL,        opPMULLW_a32,   ILLEGAL,        ILLEGAL,        opPSUBUSB_a32,  opPSUBUSW_a32,  NULL,           opPAND_a32,     opPADDUSB_a32,  opPADDUSW_a32,  NULL,           opPANDN_a32,
+/*e0*/  ILLEGAL,        opPSRAW_a32,    opPSRAD_a32,    ILLEGAL,        ILLEGAL,        opPMULHW_a32,   ILLEGAL,        ILLEGAL,        opPSUBSB_a32,   opPSUBSW_a32,   NULL,           opPOR_a32,      opPADDSB_a32,   opPADDSW_a32,   NULL,           opPXOR_a32,
+/*f0*/  ILLEGAL,        opPSLLW_a32,    opPSLLD_a32,    opPSLLQ_a32,    ILLEGAL,        opPMADDWD_a32,  ILLEGAL,        ILLEGAL,        opPSUBB_a32,    opPSUBW_a32,    opPSUBD_a32,    ILLEGAL,        opPADDB_a32,    opPADDW_a32,    opPADDD_a32,    ILLEGAL,
+};
+
+OpFn OP_TABLE(pentiumpro_0f)[1024] =
+{
+        /*16-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_w_a16,  opCMOVNO_w_a16, opCMOVB_w_a16,  opCMOVNB_w_a16, opCMOVE_w_a16,  opCMOVNE_w_a16, opCMOVBE_w_a16, opCMOVNBE_w_a16,opCMOVS_w_a16,  opCMOVNS_w_a16, opCMOVP_w_a16,  opCMOVNP_w_a16, opCMOVL_w_a16,  opCMOVNL_w_a16, opCMOVLE_w_a16, opCMOVNLE_w_a16,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
+
+/*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_l_a16,  opCMOVNO_l_a16, opCMOVB_l_a16,  opCMOVNB_l_a16, opCMOVE_l_a16,  opCMOVNE_l_a16, opCMOVBE_l_a16, opCMOVNBE_l_a16,opCMOVS_l_a16,  opCMOVNS_l_a16, opCMOVP_l_a16,  opCMOVNP_l_a16, opCMOVL_l_a16,  opCMOVNL_l_a16, opCMOVLE_l_a16, opCMOVNLE_l_a16,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
+
+/*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*16-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_w_a32,  opCMOVNO_w_a32, opCMOVB_w_a32,  opCMOVNB_w_a32, opCMOVE_w_a32,  opCMOVNE_w_a32, opCMOVBE_w_a32, opCMOVNBE_w_a32,opCMOVS_w_a32,  opCMOVNS_w_a32, opCMOVP_w_a32,  opCMOVNP_w_a32, opCMOVL_w_a32,  opCMOVNL_w_a32, opCMOVLE_w_a32, opCMOVNLE_w_a32,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
+
+/*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        ILLEGAL,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_l_a32,  opCMOVNO_l_a32, opCMOVB_l_a32,  opCMOVNB_l_a32, opCMOVE_l_a32,  opCMOVNE_l_a32, opCMOVBE_l_a32, opCMOVNBE_l_a32,opCMOVS_l_a32,  opCMOVNS_l_a32, opCMOVP_l_a32,  opCMOVNP_l_a32, opCMOVL_l_a32,  opCMOVNL_l_a32, opCMOVLE_l_a32, opCMOVNLE_l_a32,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
+
+/*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+};
+
+OpFn OP_TABLE(pentium2_0f)[1024] =
+{
+        /*16-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_w_a16,  opCMOVNO_w_a16, opCMOVB_w_a16,  opCMOVNB_w_a16, opCMOVE_w_a16,  opCMOVNE_w_a16, opCMOVBE_w_a16, opCMOVNBE_w_a16,opCMOVS_w_a16,  opCMOVNS_w_a16, opCMOVP_w_a16,  opCMOVNP_w_a16, opCMOVL_w_a16,  opCMOVNL_w_a16, opCMOVLE_w_a16, opCMOVNLE_w_a16,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16,  opPCMPGTW_a16,  opPCMPGTD_a16,  opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
+
+/*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        opPSRLW_a16,    opPSRLD_a16,    opPSRLQ_a16,    ILLEGAL,        opPMULLW_a16,   ILLEGAL,        ILLEGAL,        opPSUBUSB_a16,  opPSUBUSW_a16,  NULL,           opPAND_a16,     opPADDUSB_a16,  opPADDUSW_a16,  NULL,           opPANDN_a16,
+/*e0*/  ILLEGAL,        opPSRAW_a16,    opPSRAD_a16,    ILLEGAL,        ILLEGAL,        opPMULHW_a16,   ILLEGAL,        ILLEGAL,        opPSUBSB_a16,   opPSUBSW_a16,   NULL,           opPOR_a16,      opPADDSB_a16,   opPADDSW_a16,   NULL,           opPXOR_a16,
+/*f0*/  ILLEGAL,        opPSLLW_a16,    opPSLLD_a16,    opPSLLQ_a16,    ILLEGAL,        opPMADDWD_a16,  ILLEGAL,        ILLEGAL,        opPSUBB_a16,    opPSUBW_a16,    opPSUBD_a16,    ILLEGAL,        opPADDB_a16,    opPADDW_a16,    opPADDD_a16,    ILLEGAL,
+
+        /*32-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,  opHINTNOP_a16,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_l_a16,  opCMOVNO_l_a16, opCMOVB_l_a16,  opCMOVNB_l_a16, opCMOVE_l_a16,  opCMOVNE_l_a16, opCMOVBE_l_a16, opCMOVNBE_l_a16,opCMOVS_l_a16,  opCMOVNS_l_a16, opCMOVP_l_a16,  opCMOVNP_l_a16, opCMOVL_l_a16,  opCMOVNL_l_a16, opCMOVLE_l_a16, opCMOVNLE_l_a16,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16,  opPCMPGTW_a16,  opPCMPGTD_a16,  opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a16,  opPCMPEQW_a16,  opPCMPEQD_a16,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
+
+/*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a16,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        opPSRLW_a16,    opPSRLD_a16,    opPSRLQ_a16,    ILLEGAL,        opPMULLW_a16,   ILLEGAL,        ILLEGAL,        opPSUBUSB_a16,  opPSUBUSW_a16,  NULL,           opPAND_a16,     opPADDUSB_a16,  opPADDUSW_a16,  NULL,           opPANDN_a16,
+/*e0*/  ILLEGAL,        opPSRAW_a16,    opPSRAD_a16,    ILLEGAL,        ILLEGAL,        opPMULHW_a16,   ILLEGAL,        ILLEGAL,        opPSUBSB_a16,   opPSUBSW_a16,   NULL,           opPOR_a16,      opPADDSB_a16,   opPADDSW_a16,   NULL,           opPXOR_a16,
+/*f0*/  ILLEGAL,        opPSLLW_a16,    opPSLLD_a16,    opPSLLQ_a16,    ILLEGAL,        opPMADDWD_a16,  ILLEGAL,        ILLEGAL,        opPSUBB_a16,    opPSUBW_a16,    opPSUBD_a16,    ILLEGAL,        opPADDB_a16,    opPADDW_a16,    opPADDD_a16,    ILLEGAL,
+
+        /*16-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  opCMOVO_w_a32,  opCMOVNO_w_a32, opCMOVB_w_a32,  opCMOVNB_w_a32, opCMOVE_w_a32,  opCMOVNE_w_a32, opCMOVBE_w_a32, opCMOVNBE_w_a32,opCMOVS_w_a32,  opCMOVNS_w_a32, opCMOVP_w_a32,  opCMOVNP_w_a32, opCMOVL_w_a32,  opCMOVNL_w_a32, opCMOVLE_w_a32, opCMOVNLE_w_a32,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  opPUNPCKLBW_a32,opPUNPCKLWD_a32,opPUNPCKLDQ_a32,opPACKSSWB_a32, opPCMPGTB_a32,  opPCMPGTW_a32,  opPCMPGTD_a32,  opPACKUSWB_a32, opPUNPCKHBW_a32,opPUNPCKHWD_a32,opPUNPCKHDQ_a32,opPACKSSDW_a32, ILLEGAL,        ILLEGAL,        opMOVD_l_mm_a32,opMOVQ_q_mm_a32,
+/*70*/  ILLEGAL,        opPSxxW_imm,    opPSxxD_imm,    opPSxxQ_imm,    opPCMPEQB_a32,  opPCMPEQW_a32,  opPCMPEQD_a32,  opEMMS,         ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opMOVD_mm_l_a32,opMOVQ_mm_q_a32,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
+
+/*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        opPSRLW_a32,    opPSRLD_a32,    opPSRLQ_a32,    ILLEGAL,        opPMULLW_a32,   ILLEGAL,        ILLEGAL,        opPSUBUSB_a32,  opPSUBUSW_a32,  NULL,           opPAND_a32,     opPADDUSB_a32,  opPADDUSW_a32,  NULL,           opPANDN_a32,
+/*e0*/  ILLEGAL,        opPSRAW_a32,    opPSRAD_a32,    ILLEGAL,        ILLEGAL,        opPMULHW_a32,   ILLEGAL,        ILLEGAL,        opPSUBSB_a32,   opPSUBSW_a32,   NULL,           opPOR_a32,      opPADDSB_a32,   opPADDSW_a32,   NULL,           opPXOR_a32,
+/*f0*/  ILLEGAL,        opPSLLW_a32,    opPSLLD_a32,    opPSLLQ_a32,    ILLEGAL,        opPMADDWD_a32,  ILLEGAL,        ILLEGAL,        opPSUBB_a32,    opPSUBW_a32,    opPSUBD_a32,    ILLEGAL,        opPADDB_a32,    opPADDW_a32,    opPADDD_a32,    ILLEGAL,
+
+        /*32-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/
+/*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         ILLEGAL,        opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,  opHINTNOP_a32,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  opWRMSR,        opRDTSC,        opRDMSR,        opRDPMC,        opSYSENTER,     opSYSEXIT,      ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 
 /*40*/  opCMOVO_l_a32,  opCMOVNO_l_a32, opCMOVB_l_a32,  opCMOVNB_l_a32, opCMOVE_l_a32,  opCMOVNE_l_a32, opCMOVBE_l_a32, opCMOVNBE_l_a32,opCMOVS_l_a32,  opCMOVNS_l_a32, opCMOVP_l_a32,  opCMOVNP_l_a32, opCMOVL_l_a32,  opCMOVNL_l_a32, opCMOVLE_l_a32, opCMOVNLE_l_a32,
 /*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
@@ -811,7 +1085,7 @@ OpFn OP_TABLE(c6x86mx_0f)[1024] =
 
 /*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
 /*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
-/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     ILLEGAL,        opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
 /*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
 
 /*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opCMPXCHG8B_a32,opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,

src/8087.h

@@ -0,0 +1,98 @@
+/*This file is a series of macros to get the 386+ based x87 emulation working with
+  the 808x emulation*/
+#define X8087
+#define OP_TABLE(name) ops_808x_ ## name
+
+#define CLOCK_CYCLES(c) cycles -= (c)
+#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
+
+#define fetch_ea_16(fetchdat)
+#define fetch_ea_32(fetchdat)
+#define SEG_CHECK_READ(seg)
+#define SEG_CHECK_WRITE(seg)
+#define CHECK_WRITE(seg, addr_lo, addr_hi)
+#define PREFETCH_RUN(timing, bytes, rmdat, a, b, c, d, e)
+
+static uint32_t readmeml(uint32_t seg, uint32_t addr)
+{
+        return readmemw(seg, addr) | (readmemw(seg, addr+2) << 16);
+}
+static uint64_t readmemq(uint32_t seg, uint32_t addr)
+{
+        return (uint64_t)readmemw(seg, addr) | ((uint64_t)readmemw(seg, addr+2) << 16) |
+                        ((uint64_t)readmemw(seg, addr+4) << 32) |
+                        ((uint64_t)readmemw(seg, addr+6) << 48);
+}
+
+static void writememb_8087(uint32_t seg, uint32_t addr, uint8_t val)
+{
+        writememb(seg+addr, val);
+}
+static void writememl(uint32_t seg, uint32_t addr, uint32_t val)
+{
+        writememw(seg, addr, val & 0xffff);
+        writememw(seg, addr+2, (val >> 16) & 0xffff);
+}
+static void writememq(uint32_t seg, uint32_t addr, uint64_t val)
+{
+        writememw(seg, addr, val & 0xffff);
+        writememw(seg, addr+2, (val >> 16) & 0xffff);
+        writememw(seg, addr+4, (val >> 32) & 0xffff);
+        writememw(seg, addr+6, (val >> 48) & 0xffff);
+}
+
+static inline uint32_t geteal()
+{
+        if (cpu_mod == 3)
+                fatal("geteal cpu_mod==3\n");
+        return readmeml(easeg, cpu_state.eaaddr);
+}
+static inline uint64_t geteaq()
+{
+        if (cpu_mod == 3)
+                fatal("geteaq cpu_mod==3\n");
+        return readmemq(easeg, cpu_state.eaaddr);
+}
+static inline void seteal(uint32_t val)
+{
+        if (cpu_mod == 3)
+                fatal("seteal cpu_mod==3\n");
+        else
+                writememl(easeg, cpu_state.eaaddr, val);
+}
+static inline void seteaq(uint64_t val)
+{
+        if (cpu_mod == 3)
+                fatal("seteaq cpu_mod==3\n");
+        else
+                writememq(easeg, cpu_state.eaaddr, val);
+}
+
+#define flags_rebuild()
+
+#define CF_SET() (cpu_state.flags & C_FLAG)
+#define NF_SET() (cpu_state.flags & N_FLAG)
+#define PF_SET() (cpu_state.flags & P_FLAG)
+#define VF_SET() (cpu_state.flags & V_FLAG)
+#define ZF_SET() (cpu_state.flags & Z_FLAG)
+
+#define cond_O   ( VF_SET())
+#define cond_NO  (!VF_SET())
+#define cond_B   ( CF_SET())
+#define cond_NB  (!CF_SET())
+#define cond_E   ( ZF_SET())
+#define cond_NE  (!ZF_SET())
+#define cond_BE  ( CF_SET() ||  ZF_SET())
+#define cond_NBE (!CF_SET() && !ZF_SET())
+#define cond_S   ( NF_SET())
+#define cond_NS  (!NF_SET())
+#define cond_P   ( PF_SET())
+#define cond_NP  (!PF_SET())
+#define cond_L   (((NF_SET()) ? 1 : 0) != ((VF_SET()) ? 1 : 0))
+#define cond_NL  (((NF_SET()) ? 1 : 0) == ((VF_SET()) ? 1 : 0))
+#define cond_LE  (((NF_SET()) ? 1 : 0) != ((VF_SET()) ? 1 : 0) ||  (ZF_SET()))
+#define cond_NLE (((NF_SET()) ? 1 : 0) == ((VF_SET()) ? 1 : 0) && (!ZF_SET()))
+
+#define writememb writememb_8087
+#include "x87_ops.h"
+#undef writememb

src/808x.c

@@ -583,6 +583,7 @@ void dumpregs()
         {
                 printf("386 in %s mode   stack in %s mode\n",(use32)?"32-bit":"16-bit",(stack32)?"32-bit":"16-bit");
                 printf("CR0=%08X CR2=%08X CR3=%08X CR4=%08x\n",cr0,cr2,cr3, cr4);
+                pclog("SMBASE=%08x\n", cpu_state.smbase);
         }
         printf("Entries in readlookup : %i    writelookup : %i\n",readlnum,writelnum);
         for (c=0;c<1024*1024;c++)
@@ -641,6 +642,7 @@ void resetx86()
         x86seg_reset();
         codegen_reset();
         x86_was_reset = 1;
+        cpu_state.smbase = 0x30000;
 }
 
 void softresetx86()
@@ -677,11 +679,19 @@ void softresetx86()
         //rammask=0xFFFFFFFF;
         cpu_state.flags=2;
         idt.base = 0;
-        idt.limit = is386 ? 0x03FF : 0xFFFF;
+        if (is386)
-        EAX = EBX = ECX = EDX = ESI = EDI = EBP = ESP = 0;
+        {
+                idt.limit = 0x03FF;
+                EAX = EBX = ECX = EDX = ESI = EDI = EBP = ESP = 0;
+        }
+        else
+        {
+                idt.limit = 0xFFFF;
+        }
         x86seg_reset();
         flushmmucache();
         x86_was_reset = 1;
+        FETCHCLEAR();
 }
 
 static void setznp8(uint8_t val)
@@ -1104,6 +1114,8 @@ static void rep(int fv)
 static int inhlt=0;
 static int skipnextprint=0;
 
+#include "8087.h"
+
 void execx86(int cycs)
 {
         uint8_t temp,temp2;
@@ -2945,10 +2957,78 @@ void execx86(int cycs)
                         AL=readmemb(ds+addr);
                         cycles-=11;
                         break;
-                        case 0xD9: case 0xDA: case 0xDB: case 0xDD: /*ESCAPE*/
+                        
-                        case 0xDC: case 0xDE: case 0xDF: case 0xD8:
+                        case 0xd8:
                         fetchea();
-                        geteab();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_d8_a16[rmdat >> 3](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xd9:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_d9_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xda:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_da_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xdb:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_db_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xdc:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_dc_a16[rmdat >> 3](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xdd:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_dd_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xde:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_de_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
+                        break;
+                        case 0xdf:
+                        fetchea();
+                        if (hasfpu)
+                        {
+                                uint16_t save_pc = cpu_state.pc;
+                                ops_808x_fpu_df_a16[rmdat](rmdat);
+                                cpu_state.pc = save_pc;
+                        }
                         break;
 
                         case 0xE0: /*LOOPNE*/
@@ -3494,14 +3574,6 @@ void execx86(int cycs)
                // if (instime) printf("%i %i %i %i\n",cycdiff,cycles,memcycs,fetchclocks);
                 FETCHADD(((cycdiff-cycles)-memcycs)-fetchclocks);
                 if ((cycdiff-cycles)<memcycs) cycles-=(memcycs-(cycdiff-cycles));
-                if (romset==ROM_IBMPC)
-                {
-                        if ((cs+cpu_state.pc)==0xFE4A7) /*You didn't seriously think I was going to emulate the cassette, did you?*/
-                        {
-                                CX=1;
-                                BX=0x500;
-                        }
-                }
                 memcycs=0;
 
                 insc++;

src/82091aa.c

@@ -0,0 +1,196 @@
+#include "ibm.h"
+#include "82091aa.h"
+#include "fdc.h"
+#include "io.h"
+#include "lpt.h"
+#include "serial.h"
+
+#define AIP_AIPID   0x00
+#define AIP_AIPREV  0x01
+#define AIP_AIPCFG1 0x02
+#define AIP_AIPCFG2 0x03
+#define AIP_FCFG1   0x10
+#define AIP_FCFG2   0x11
+#define AIP_PCFG1   0x20
+#define AIP_PCFG2   0x21
+#define AIP_SACFG1  0x30
+#define AIP_SACFG2  0x31
+#define AIP_SBCFG1  0x40
+#define AIP_SBCFG2  0x41
+#define AIP_IDECFG  0x50
+
+#define FCFG1_FDC_ENA  (1 << 0)
+#define FCFG1_FDC_ADDR (1 << 1)
+
+#define PCFG1_PP_ENA   (1 << 0)
+#define PCFG1_PP_ADDR  (3 << 1)
+#define PCFG1_PP_ADDR_378 (0 << 1)
+#define PCFG1_PP_ADDR_278 (1 << 1)
+#define PCFG1_PP_ADDR_3BC (2 << 1)
+
+#define SxCFG1_ENA     (1 << 0)
+#define SxCFG1_ADDR    (7 << 1)
+#define SxCFG1_ADDR_3F8 (0 << 1)
+#define SxCFG1_ADDR_2F8 (1 << 1)
+#define SxCFG1_ADDR_220 (2 << 1)
+#define SxCFG1_ADDR_228 (3 << 1)
+#define SxCFG1_ADDR_238 (4 << 1)
+#define SxCFG1_ADDR_2E8 (5 << 1)
+#define SxCFG1_ADDR_338 (6 << 1)
+#define SxCFG1_ADDR_3E8 (7 << 1)
+#define SxCFG1_IRQ     (1 << 4)
+#define SxCFG1_IRQ_3    (0 << 4)
+#define SxCFG1_IRQ_4    (1 << 4)
+
+static struct
+{
+        int idx;
+        uint8_t regs[256];
+} aip;
+
+static uint8_t aip_read(uint16_t addr, void *p)
+{
+        uint8_t temp;
+
+        if (!(addr & 1))
+                temp = aip.idx;
+        else
+                temp = aip.regs[aip.idx];
+
+//        pclog("aip_read: addr=%04x val=%02x\n", addr, temp);
+        return temp;
+}
+
+static void aip_write(uint16_t addr, uint8_t val, void *p)
+{
+//        pclog("aip_write: addr=%04x val=%02x\n", addr, val);
+        if (!(addr & 1))
+                aip.idx = val;
+        else
+        {
+//                pclog("AIP register write: idx=%02x val=%02x\n", aip.idx, val);
+                switch (aip.idx)
+                {
+                        case AIP_AIPCFG1:
+                        aip.regs[AIP_AIPCFG1] = (val & ~0x4e) | (aip.regs[AIP_AIPCFG1] & 0x48);
+                        break;
+                        case AIP_AIPCFG2:
+                        aip.regs[AIP_AIPCFG2] = val & 0xf8;
+                        break;
+                        case AIP_FCFG1:
+                        aip.regs[AIP_FCFG1] = val & 0x83;
+                        fdc_remove();
+                        if ((aip.regs[AIP_FCFG1] & FCFG1_FDC_ENA) && !(aip.regs[AIP_FCFG1] & FCFG1_FDC_ADDR))
+                                fdc_add();
+                        break;
+                        case AIP_FCFG2:
+                        aip.regs[AIP_FCFG2] = (val & 0x0d) | (aip.regs[AIP_FCFG2] & 0x02);
+                        break;
+                        case AIP_PCFG1:
+                        aip.regs[AIP_PCFG1] = val & 0xef;
+                        lpt1_remove();
+                        if (aip.regs[AIP_PCFG1] & PCFG1_PP_ENA)
+                        {
+                                switch (aip.regs[AIP_PCFG1] & PCFG1_PP_ADDR)
+                                {
+                                        case PCFG1_PP_ADDR_378:
+                                        lpt1_init(0x378);
+                                        break;
+                                        case PCFG1_PP_ADDR_278:
+                                        lpt1_init(0x278);
+                                        break;
+                                        case PCFG1_PP_ADDR_3BC:
+                                        lpt1_init(0x3bc);
+                                        break;
+                                }
+                        }
+                        break;
+                        case AIP_PCFG2:
+                        aip.regs[AIP_PCFG2] = (val & 0x0d) | (aip.regs[AIP_PCFG2] & 0x22);
+                        break;
+                        case AIP_SACFG1:
+                        aip.regs[AIP_SACFG1] = val & 0x9f;
+                        serial1_remove();
+                        if (aip.regs[AIP_SACFG1] & SxCFG1_ENA)
+                        {
+                                uint16_t base = 0;
+                                int irq = 0;
+                                
+                                switch (aip.regs[AIP_SACFG1] & SxCFG1_ADDR)
+                                {
+                                        case SxCFG1_ADDR_3F8: base = 0x3f8; break;
+                                        case SxCFG1_ADDR_2F8: base = 0x2f8; break;
+                                        case SxCFG1_ADDR_220: base = 0x220; break;
+                                        case SxCFG1_ADDR_228: base = 0x228; break;
+                                        case SxCFG1_ADDR_238: base = 0x238; break;
+                                        case SxCFG1_ADDR_2E8: base = 0x2e8; break;
+                                        case SxCFG1_ADDR_338: base = 0x338; break;
+                                        case SxCFG1_ADDR_3E8: base = 0x3e8; break;
+                                }
+                                switch (aip.regs[AIP_SACFG1] & SxCFG1_IRQ)
+                                {
+                                        case SxCFG1_IRQ_3: irq = 3; break;
+                                        case SxCFG1_IRQ_4: irq = 4; break;
+                                }
+                                serial1_set(base, irq);
+                        }
+                        break;
+                        case AIP_SACFG2:
+                        aip.regs[AIP_SACFG2] = (val & 0x01d) | (aip.regs[AIP_SACFG2] & 0x02);
+                        break;
+                        case AIP_SBCFG1:
+                        aip.regs[AIP_SBCFG1] = val & 0x9f;
+                        serial2_remove();
+                        if (aip.regs[AIP_SBCFG1] & SxCFG1_ENA)
+                        {
+                                uint16_t base = 0;
+                                int irq = 0;
+
+                                switch (aip.regs[AIP_SBCFG1] & SxCFG1_ADDR)
+                                {
+                                        case SxCFG1_ADDR_3F8: base = 0x3f8; break;
+                                        case SxCFG1_ADDR_2F8: base = 0x2f8; break;
+                                        case SxCFG1_ADDR_220: base = 0x220; break;
+                                        case SxCFG1_ADDR_228: base = 0x228; break;
+                                        case SxCFG1_ADDR_238: base = 0x238; break;
+                                        case SxCFG1_ADDR_2E8: base = 0x2e8; break;
+                                        case SxCFG1_ADDR_338: base = 0x338; break;
+                                        case SxCFG1_ADDR_3E8: base = 0x3e8; break;
+                                }
+                                switch (aip.regs[AIP_SBCFG1] & SxCFG1_IRQ)
+                                {
+                                        case SxCFG1_IRQ_3: irq = 3; break;
+                                        case SxCFG1_IRQ_4: irq = 4; break;
+                                }
+                                serial2_set(base, irq);
+                        }
+                        break;
+                        case AIP_SBCFG2:
+                        aip.regs[AIP_SACFG2] = (val & 0x01d) | (aip.regs[AIP_SACFG2] & 0x02);
+                        break;
+                        case AIP_IDECFG:
+                        aip.regs[AIP_IDECFG] = val & 0x07;
+                        break;
+                }
+        }
+}
+
+void aip_82091aa_init(uint16_t base)
+{
+        io_sethandler(base, 0x0002, aip_read, NULL, NULL, aip_write, NULL, NULL,  NULL);
+        
+        memset(&aip.regs, 0xff, sizeof(aip.regs));
+        aip.regs[AIP_AIPID]   = 0xa0;
+        aip.regs[AIP_AIPREV]  = 0x00;
+        aip.regs[AIP_AIPCFG1] = 0x40;
+        aip.regs[AIP_AIPCFG2] = 0x00;
+        aip.regs[AIP_FCFG1]   = 0x01;
+        aip.regs[AIP_FCFG2]   = 0x00;
+        aip.regs[AIP_PCFG1]   = 0x00;
+        aip.regs[AIP_PCFG2]   = 0x00;
+        aip.regs[AIP_SACFG1]  = 0x00;
+        aip.regs[AIP_SACFG2]  = 0x02;
+        aip.regs[AIP_SBCFG1]  = 0x00;
+        aip.regs[AIP_SBCFG2]  = 0x02;
+        aip.regs[AIP_IDECFG]  = 0x01;
+}

src/82091aa.h

@@ -0,0 +1 @@
+void aip_82091aa_init(uint16_t base);

src/Makefile.am

@@ -23,26 +23,35 @@ wx-resources.cpp : pc.xrc
 	-wxrc -c pc.xrc -o wx-resources.cpp
 
 # PCem
-pcem_SOURCES = 386.c 386_common.c 386_dynarec.c 386_dynarec_ops.c 808x.c acc2036.c acer386sx.c ali1429.c  amstrad.c cbm_io.c cdrom-image.cc cdrom-null.c \
+pcem_SOURCES = 386.c 386_common.c 386_dynarec.c 386_dynarec_ops.c 808x.c 82091aa.c acc2036.c acc2168.c acc3221.c acer386sx.c \
-cmd640.c codegen.c codegen_accumulate.c codegen_allocator.c codegen_backend.c codegen_ir.c codegen_ops.c codegen_ops_3dnow.c codegen_ops_arith.c codegen_ops_branch.c codegen_ops_fpu_arith.c codegen_ops_fpu_constant.c codegen_ops_fpu_loadstore.c codegen_ops_fpu_misc.c codegen_ops_helpers.c codegen_ops_jump.c codegen_ops_logic.c codegen_ops_shift.c \
+ali1429.c amstrad.c cassette.c cbm_io.c cdrom-image.cc cdrom-null.c cmd640.c codegen.c codegen_accumulate.c \
-codegen_ops_misc.c codegen_ops_mov.c codegen_ops_stack.c codegen_reg.c codegen_timing_486.c codegen_timing_686.c codegen_timing_common.c codegen_timing_k6.c codegen_timing_pentium.c codegen_timing_winchip.c codegen_timing_winchip2.c compaq.c config.c cpu.c \
+codegen_allocator.c codegen_block.c codegen_ir.c codegen_ops.c codegen_ops_3dnow.c codegen_ops_arith.c \
-cpu_tables.c dells200.c device.c disc.c disc_fdi.c disc_img.c disc_sector.c dma.c esdi_at.c fdc.c fdc37c665.c fdd.c fdi2raw.c gameport.c \
+codegen_ops_branch.c codegen_ops_fpu_arith.c codegen_ops_fpu_constant.c codegen_ops_fpu_loadstore.c \
-hdd.c hdd_esdi.c hdd_file.c headland.c i430lx.c i430fx.c i430vx.c ide.c ide_atapi.c ide_sff8038i.c intel.c intel_flash.c io.c jim.c joystick_ch_flightstick_pro.c joystick_standard.c joystick_sw_pad.c \
+codegen_ops_fpu_misc.c codegen_ops_mmx_arith.c codegen_ops_mmx_cmp.c codegen_ops_mmx_loadstore.c \
-joystick_tm_fcs.c keyboard.c keyboard_amstrad.c keyboard_at.c keyboard_olim24.c keyboard_pcjr.c keyboard_xt.c \
+codegen_ops_mmx_logic.c codegen_ops_mmx_pack.c codegen_ops_mmx_shift.c codegen_ops_helpers.c codegen_ops_jump.c \
-laserxt.c lpt.c lpt_dac.c lpt_dss.c mca.c mcr.c mem.c mem_bios.c mfm_at.c mfm_xebec.c model.c mouse.c mouse_msystems.c mouse_ps2.c mouse_serial.c mvp3.c neat.c nmi.c nvr.c olivetti_m24.c \
+codegen_ops_logic.c codegen_ops_shift.c codegen_ops_misc.c codegen_ops_mov.c codegen_ops_stack.c codegen_reg.c \
-opti495.c paths.c pc.c pc87306.c pci.c pic.c piix.c pit.c ppi.c ps1.c ps2.c ps2_mca.c ps2_nvr.c nvr_tc8521.c rom.c rtc.c rtc_tc8521.c scat.c scsi.c scsi_53c400.c scsi_aha1540.c scsi_cd.c scsi_hd.c scsi_zip.c \
+codegen_timing_486.c codegen_timing_686.c codegen_timing_common.c codegen_timing_cyrixiii.c codegen_timing_k6.c codegen_timing_p6.c codegen_timing_pentium.c \
-serial.c sio.c sis496.c sl82c460.c sound.c sound_ad1848.c sound_adlib.c sound_adlibgold.c sound_audiopci.c sound_cms.c sound_emu8k.c sound_gus.c \
+codegen_timing_winchip.c codegen_timing_winchip2.c compaq.c config.c cpu.c cpu_tables.c cs8230.c dells200.c device.c disc.c \
-sound_mpu401_uart.c sound_opl.c sound_pas16.c sound_ps1.c sound_pssj.c sound_sb.c sound_sb_dsp.c sound_sn76489.c \
+disc_fdi.c disc_img.c disc_sector.c dma.c esdi_at.c f82c710_upc.c fdc.c fdc37c665.c fdc37c93x.c fdd.c fdi2raw.c gameport.c hdd.c hdd_esdi.c \
-sound_speaker.c sound_ssi2001.c sound_wss.c sound_ym7128.c soundopenal.c sst39sf010.c tandy_eeprom.c tandy_rom.c \
+hdd_file.c headland.c i430lx.c i430fx.c i430hx.c i430vx.c i440fx.c i440bx.c ide.c ide_atapi.c ide_sff8038i.c intel.c intel_flash.c io.c \
-t1000.c t3100e.c \
+jim.c joystick_ch_flightstick_pro.c joystick_standard.c joystick_sw_pad.c joystick_tm_fcs.c keyboard.c \
-timer.c um8669f.c um8881f.c vid_ati_eeprom.c vid_ati_mach64.c vid_ati18800.c vid_ati28800.c \
+keyboard_amstrad.c keyboard_at.c keyboard_olim24.c keyboard_pcjr.c keyboard_xt.c laserxt.c lpt.c lpt_dac.c lpt_dss.c \
-vid_ati68860_ramdac.c vid_cga.c vid_cl5429.c vid_colorplus.c vid_compaq_cga.c vid_ega.c vid_et4000.c vid_et4000w32.c vid_genius.c vid_hercules.c \
+mca.c mcr.c mem.c mem_bios.c mfm_at.c mfm_xebec.c model.c mouse.c mouse_msystems.c mouse_ps2.c mouse_serial.c mvp3.c \
-vid_icd2061.c vid_ics2595.c vid_incolor.c vid_mda.c vid_olivetti_m24.c vid_oti037.c vid_oti067.c vid_paradise.c vid_pc200.c \
+neat.c nmi.c nvr.c olivetti_m24.c opti495.c paths.c pc.c pc87306.c pc87307.c pci.c pic.c piix.c piix_pm.c pit.c ppi.c ps1.c ps2.c ps2_mca.c \
-vid_pc1512.c vid_pc1640.c vid_pcjr.c vid_ps1_svga.c vid_s3.c vid_s3_virge.c vid_sdac_ramdac.c \
+ps2_nvr.c nvr_tc8521.c pzx.c rom.c rtc.c rtc_tc8521.c scamp.c scat.c scsi.c scsi_53c400.c scsi_aha1540.c scsi_cd.c scsi_hd.c \
+scsi_ibm.c scsi_zip.c serial.c sio.c sis496.c sl82c460.c sound.c sound_ad1848.c sound_adlib.c sound_adlibgold.c sound_audiopci.c \
+sound_azt2316a.c sound_cms.c sound_emu8k.c sound_gus.c sound_mpu401_uart.c sound_opl.c sound_pas16.c sound_ps1.c sound_pssj.c \
+sound_sb.c sound_sb_dsp.c sound_sn76489.c sound_speaker.c sound_ssi2001.c sound_wss.c sound_ym7128.c soundopenal.c \
+sst39sf010.c superxt.c tandy_eeprom.c tandy_rom.c t1000.c t3100e.c timer.c um8669f.c um8881f.c vid_ati_eeprom.c vid_ati_mach64.c \
+vid_ati18800.c vid_ati28800.c vid_ati68860_ramdac.c vid_cga.c vid_cl5429.c vid_colorplus.c vid_compaq_cga.c vid_ddc.c vid_ega.c \
+vid_et4000.c vid_et4000w32.c vid_genius.c vid_hercules.c vid_ht216.c vid_icd2061.c vid_ics2595.c vid_im1024.c \
+vid_incolor.c vid_mda.c vid_mga.c vid_olivetti_m24.c vid_oti037.c vid_oti067.c vid_paradise.c vid_pc200.c vid_pc1512.c \
+vid_pc1640.c vid_pcjr.c vid_pgc.c vid_ps1_svga.c vid_s3.c vid_s3_virge.c vid_sdac_ramdac.c vid_sigma.c \
 vid_stg_ramdac.c vid_svga.c vid_svga_render.c vid_t1000.c vid_t3100e.c vid_tandy.c vid_tandysl.c vid_tgui9440.c \
-vid_tkd8001_ramdac.c vid_tvga.c vid_unk_ramdac.c vid_vga.c vid_voodoo.c video.c wd76c10.c vid_wy700.c vt82c586b.c \
+vid_tkd8001_ramdac.c vid_tvga.c vid_unk_ramdac.c vid_vga.c vid_voodoo.c vid_voodoo_banshee.c vid_voodoo_banshee_blitter.c \
-w83877tf.c x86seg.c x87.c xi8088.c xtide.c sound_dbopl.cc sound_resid.cc \
+vid_voodoo_blitter.c vid_voodoo_display.c vid_voodoo_fb.c vid_voodoo_fifo.c vid_voodoo_reg.c \
-codegen_ops_mmx_arith.c codegen_ops_mmx_cmp.c codegen_ops_mmx_loadstore.c codegen_ops_mmx_logic.c codegen_ops_mmx_pack.c codegen_ops_mmx_shift.c
+vid_voodoo_render.c vid_voodoo_setup.c vid_voodoo_texture.c video.c wd76c10.c vid_wy700.c vt82c586b.c \
+vl82c480.c w83877tf.c w83977tf.c x86seg.c x87.c x87_timings.c xi8088.c xtide.c zenith.c sound_dbopl.cc sound_resid.cc
 
 # DOSBox
 pcem_SOURCES += dosbox/cdrom_image.cpp dosbox/dbopl.cpp dosbox/nukedopl.cpp dosbox/vid_cga_comp.c
@@ -55,6 +64,10 @@ resid-fp/wave6581_P_T.cc resid-fp/wave6581__ST.cc resid-fp/wave8580_PS_.cc \
 resid-fp/wave8580_PST.cc resid-fp/wave8580_P_T.cc resid-fp/wave8580__ST.cc \
 resid-fp/wave.cc
 
+#MiniVHD
+pcem_SOURCES += minivhd/cwalk.c minivhd/libxml2_encoding.c minivhd/minivhd_convert.c minivhd/minivhd_create.c \
+minivhd/minivhd_io.c minivhd/minivhd_manage.c minivhd/minivhd_struct_rw.c minivhd/minivhd_util.c
+
 pcem_CFLAGS = $(subst -fpermissive,,$(shell $(WX_CONFIG_PATH) --cxxflags) $(shell sdl2-config --cflags))
 pcem_CXXFLAGS = $(shell $(WX_CONFIG_PATH) --cxxflags) $(shell sdl2-config --cflags)
 pcem_LDADD = @LIBS@
@@ -124,7 +137,7 @@ pcem_LDADD += wx.res
 endif
 
 if !HAS_OFF64T
-#pcem_CFLAGS += -Doff64_t=off_t -Dfopen64=fopen -Dfseeko64=fseek -Dftello64=ftell
+pcem_CFLAGS += -Doff64_t=off_t -Dfopen64=fopen -Dfseeko64=fseeko -Dftello64=ftello
 endif
 
 if RELEASE_BUILD
@@ -132,8 +145,8 @@ pcem_CFLAGS += -DRELEASE_BUILD
 pcem_CXXFLAGS += -DRELEASE_BUILD
 endif
 
-pcem_CFLAGS += -mtune=cortex-a53
+#pcem_CFLAGS += -mtune=cortex-a53
-pcem_CXXFLAGS += -mtune=cortex-a53
+#pcem_CXXFLAGS += -mtune=cortex-a53
 #pcem_LDFLAGS = -flto -O3 -mtune=cortex-a15
 
 # pcem_CFLAGS += -fprofile-use

src/Makefile.linux32-wx-sdl2

@@ -1,52 +0,0 @@
-VPATH = . dosbox resid-fp
-CPP  = g++
-CC   = gcc
-WXRC = wxrc
-CFLAGS = -O3 -fomit-frame-pointer -msse2 -m32 $(shell wx-config --cxxflags) $(shell sdl2-config --cflags)
-CXXFLAGS = $(CFLAGS)
-OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer386sx.o ali1429.o amstrad.o cbm_io.o cdrom-ioctl-linux.o cdrom-image.o cdrom-null.o \
-cmd640.o codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_common.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86.c compaq.o config.o cpu.o \
-dells200.o device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o \
-hdd.o hdd_esdi.o hdd_file.o headland.o i430lx.o i430fx.o i430vx.o ide.o ide_atapi.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o joystick_standard.o joystick_sw_pad.o \
-joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o \
-laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o mouse_serial.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o \
-opti495.o paths.o pc.o pc87306.o pci.o pic.o piix.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o rom.o rtc.o rtc_tc8521.o scat.o scsi.o scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_zip.o \
-serial.o sio.o sis496.o sl82c460.o sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_cms.o sound_emu8k.o sound_gus.o \
-sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o sound_sb.o sound_sb_dsp.o sound_sn76489.o \
-sound_speaker.o sound_ssi2001.o sound_wss.o sound_ym7128.o soundopenal.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o \
-timer.o um8669f.o um8881f.o vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o vid_ati28800.o \
-vid_ati68860_ramdac.o vid_cga.o vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ega.o vid_et4000.o vid_et4000w32.o vid_genius.o vid_hercules.o \
-vid_icd2061.o vid_ics2595.o vid_incolor.o vid_mda.o vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc200.o \
-vid_pc1512.o vid_pc1640.o vid_pcjr.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o \
-vid_stg_ramdac.o vid_svga.o vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o \
-vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_wy700.o video.o wd76c10.o \
-x86seg.o x87.o xi8088.c xtide.o sound_dbopl.o sound_resid.o \
-wx-main.o wx-config_sel.o wx-dialogbox.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o wx-sdl2-keyboard.o wx-sdl2-video.o wx-sdl2-midi.o \
-wx-sdl2.o wx-config.o wx-deviceconfig.o wx-status.o wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display.o \
-wx-sdl2-video-renderer.o wx-sdl2-video-gl3.o wx-glslp-parser.o wx-shader_man.o wx-shaderconfig.o wx-joystickconfig.o wx-createdisc.o
-DBOBJ = cdrom_image.o dbopl.o nukedopl.o vid_cga_comp.o
-SIDOBJ = convolve.o convolve-sse.o envelope.o extfilt.o filter.o pot.o sid.o voice.o wave6581__ST.o wave6581_P_T.o wave6581_PS_.o wave6581_PST.o wave8580__ST.o wave8580_P_T.o wave8580_PS_.o wave8580_PST.o wave.o
-
-LIBS = -lopenal -lstdc++ -lpthread -lm $(shell wx-config --libs) $(shell sdl2-config --libs) -lGL
-
-PCem-wx-SDL2: $(OBJ) $(DBOBJ) $(SIDOBJ)
-	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) -o "PCem-wx-SDL2" $(LIBS)
-
-all : PCem-wx-SDL2
-
-clean :
-	rm *.o
-	rm PCem-wx-SDL2
-	
-wx-resources.o : pc.xrc
-	$(WXRC) -c pc.xrc -o wx-resources.cpp
-	$(CPP) $(CFLAGS) -c wx-resources.cpp
-
-%.o : %.c
-	$(CC) $(CFLAGS) -c $<
-
-%.o : %.cc
-	$(CPP) $(CXXFLAGS) -c $<
-
-%.o : %.cpp
-	$(CPP) $(CXXFLAGS) -c $<

src/Makefile.linux64-wx-sdl2

@@ -1,52 +0,0 @@
-VPATH = . dosbox resid-fp
-CPP  = g++
-CC   = gcc
-WXRC = wxrc
-CFLAGS = -O3 -fomit-frame-pointer -msse2 -m64 $(shell wx-config --cxxflags) $(shell sdl2-config --cflags)
-CXXFLAGS = $(CFLAGS)
-OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer386sx.o ali1429.o amstrad.o cbm_io.o cdrom-ioctl-linux.o cdrom-image.o cdrom-null.o \
-cmd640.o codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_common.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86-64.c compaq.o config.o cpu.o \
-dells200.o device.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o \
-hdd.o hdd_esdi.o hdd_file.o headland.o i430lx.o i430fx.o i430vx.o ide.o ide_atapi.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o joystick_standard.o joystick_sw_pad.o \
-joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o \
-laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o mouse_serial.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o \
-opti495.o paths.o pc.o pc87306.o pci.o pic.o piix.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o rom.o rtc.o rtc_tc8521.o scat.o scsi.o scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_zip.o \
-serial.o sio.o sis496.o sl82c460.o sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_cms.o sound_emu8k.o sound_gus.o \
-sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o sound_sb.o sound_sb_dsp.o sound_sn76489.o \
-sound_speaker.o sound_ssi2001.o sound_wss.o sound_ym7128.o soundopenal.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o \
-timer.o um8669f.o um8881f.o vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o vid_ati28800.o \
-vid_ati68860_ramdac.o vid_cga.o vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ega.o vid_et4000.o vid_et4000w32.o vid_genius.o vid_hercules.o \
-vid_icd2061.o vid_ics2595.o vid_incolor.o vid_mda.o vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc200.o \
-vid_pc1512.o vid_pc1640.o vid_pcjr.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o \
-vid_stg_ramdac.o vid_svga.o vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o \
-vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_wy700.o video.o wd76c10.o \
-x86seg.o x87.o xi8088.c xtide.o sound_dbopl.o sound_resid.o \
-wx-main.o wx-config_sel.o wx-dialogbox.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o wx-sdl2-keyboard.o wx-sdl2-video.o wx-sdl2-midi.o \
-wx-sdl2.o wx-config.o wx-deviceconfig.o wx-status.o wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display.o \
-wx-sdl2-video-renderer.o wx-sdl2-video-gl3.o wx-glslp-parser.o wx-shader_man.o wx-shaderconfig.o wx-joystickconfig.o wx-createdisc.o
-DBOBJ = cdrom_image.o dbopl.o nukedopl.o vid_cga_comp.o
-SIDOBJ = convolve.o convolve-sse.o envelope.o extfilt.o filter.o pot.o sid.o voice.o wave6581__ST.o wave6581_P_T.o wave6581_PS_.o wave6581_PST.o wave8580__ST.o wave8580_P_T.o wave8580_PS_.o wave8580_PST.o wave.o
-
-LIBS = -lopenal -lstdc++ -lpthread -lm $(shell wx-config --libs) $(shell sdl2-config --libs) -lGL
-
-PCem64-wx-SDL2: $(OBJ) $(DBOBJ) $(SIDOBJ)
-	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) -o "PCem64-wx-SDL2" $(LIBS)
-
-all : PCem64-wx-SDL2
-
-clean :
-	rm *.o
-	rm PCem64-wx-SDL2
-	
-wx-resources.o : pc.xrc
-	$(WXRC) -c pc.xrc -o wx-resources.cpp
-	$(CPP) $(CFLAGS) -c wx-resources.cpp
-
-%.o : %.c
-	$(CC) $(CFLAGS) -c $<
-
-%.o : %.cc
-	$(CPP) $(CXXFLAGS) -c $<
-
-%.o : %.cpp
-	$(CPP) $(CXXFLAGS) -c $<

src/Makefile.mingw-wx-sdl2

@@ -1,4 +1,4 @@
-VPATH = . dosbox resid-fp
+VPATH = . dosbox resid-fp minivhd
 CPP  = g++
 CC   = gcc
 WINDRES = windres.exe
@@ -6,38 +6,40 @@ WXVERSION = 31
 WXINCLUDE = e:/MinGWget/include/wx/
 CFLAGS = -O3 -march=i686 -fomit-frame-pointer -msse2 -mstackrealign -Werror -fno-strict-aliasing
 CXXFLAGS = $(CFLAGS)
-OBJ = 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer386sx.o ali1429.o amstrad.o \
+OBJ = 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o 808x.o 82091aa.o acc2036.o acc2168.o acc3221.o acer386sx.o ali1429.o amstrad.o cassette.o \
 	cbm_io.o cdrom-ioctl.o cdrom-image.o cmd640.o codegen.o codegen_accumulate.o codegen_allocator.o \
-	codegen_backend.o codegen_backend_x86.o codegen_backend_x86_ops.o codegen_backend_x86_ops_fpu.o \
+	codegen_backend_x86.o codegen_backend_x86_ops.o codegen_backend_x86_ops_fpu.o codegen_backend_x86_ops_sse.o \
-	codegen_backend_x86_ops_sse.o codegen_backend_x86_uops.o codegen_ir.o codegen_ops.o \
+	codegen_backend_x86_uops.o codegen_block.o codegen_ir.o codegen_ops.o \
 	codegen_ops_3dnow.o codegen_ops_branch.o codegen_ops_arith.o codegen_ops_fpu_arith.o \
 	codegen_ops_fpu_constant.o codegen_ops_fpu_loadstore.o codegen_ops_fpu_misc.o codegen_ops_helpers.o codegen_ops_jump.o \
 	codegen_ops_logic.o codegen_ops_misc.o codegen_ops_mmx_arith.o codegen_ops_mmx_cmp.o \
 	codegen_ops_mmx_loadstore.o codegen_ops_mmx_logic.o codegen_ops_mmx_pack.o codegen_ops_mmx_shift.o \
 	codegen_ops_mov.o codegen_ops_shift.o codegen_ops_stack.o codegen_reg.o codegen_timing_486.o \
-	codegen_timing_686.o codegen_timing_common.o codegen_timing_k6.o codegen_timing_pentium.o \
+	codegen_timing_686.o codegen_timing_common.o codegen_timing_cyrixiii.o codegen_timing_k6.o codegen_timing_p6.o codegen_timing_pentium.o \
-	codegen_timing_winchip.o codegen_timing_winchip2.o compaq.o config.o cpu.o cpu_tables.o device.o \
+	codegen_timing_winchip.o codegen_timing_winchip2.o compaq.o config.o cpu.o cpu_tables.o cs8230.o device.o \
-	dells200.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o fdc.o fdc37c665.o fdd.o \
+	dells200.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o f82c710_upc.o fdc.o fdc37c665.o fdc37c93x.o fdd.o \
-	fdi2raw.o gameport.o hdd.o hdd_esdi.o hdd_file.o headland.o i430lx.o i430fx.o i430vx.o ide.o \
+	fdi2raw.o gameport.o hdd.o hdd_esdi.o hdd_file.o headland.o i430hx.o i430lx.o i430fx.o i430vx.o i440fx.o i440bx.o ide.o \
 	ide_atapi.o ide_sff8038i.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o \
 	joystick_standard.o joystick_sw_pad.o joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o \
 	keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o \
 	mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o mouse_serial.o \
-	mvp3.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o opti495.o paths.o pc.o pc87306.o pci.o pic.o \
+	mvp3.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o opti495.o paths.o pc.o pc87306.o pc87307.o pci.o pic.o \
-	piix.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o rom.o rtc.o rtc_tc8521.o scat.o scsi.o \
+	piix.o piix_pm.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o pzx.o rom.o rtc.o rtc_tc8521.o scamp.o scat.o scsi.o \
-	scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_zip.o serial.o sio.o sis496.o sl82c460.o \
+	scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_ibm.o scsi_zip.o serial.o sio.o sis496.o sl82c460.o \
-	sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_cms.o sound_dbopl.o \
+	sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_azt2316a.o sound_cms.o sound_dbopl.o \
 	sound_emu8k.o sound_gus.o sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o \
 	sound_resid.o sound_sb.o sound_sb_dsp.o sound_sn76489.o sound_speaker.o sound_ssi2001.o sound_wss.o \
-	sound_ym7128.o soundopenal.o sst39sf010.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o timer.o um8881f.o um8669f.o \
+	sound_ym7128.o soundopenal.o sst39sf010.o superxt.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o timer.o um8881f.o um8669f.o \
 	vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o vid_ati28800.o vid_ati68860_ramdac.o vid_cga.o \
-	vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ega.o vid_et4000.o vid_et4000w32.o \
+	vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ddc.o vid_ega.o vid_et4000.o vid_et4000w32.o \
-	vid_et4000w32i.o vid_genius.o vid_hercules.o vid_icd2061.o vid_ics2595.o vid_incolor.o vid_mda.o \
+	vid_et4000w32i.o vid_genius.o vid_hercules.o vid_ht216.o vid_icd2061.o vid_ics2595.o vid_im1024.o vid_incolor.o vid_mda.o \
-	vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc1512.o vid_pc1640.o vid_pc200.o \
+	vid_mga.o vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc1512.o vid_pc1640.o vid_pc200.o \
-	vid_pcjr.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o vid_stg_ramdac.o vid_svga.o \
+	vid_pcjr.o vid_pgc.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o vid_sigma.o vid_stg_ramdac.o vid_svga.o \
 	vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o \
-	vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_wy700.o video.o \
+	vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_voodoo_banshee.o vid_voodoo_banshee_blitter.o \
-	vt82c586b.o w83877tf.o wd76c10.o x86seg.o x87.o xi8088.c xtide.o win-midi.o wx-main.o \
+	vid_voodoo_blitter.o vid_voodoo_display.o vid_voodoo_fb.o vid_voodoo_fifo.o vid_voodoo_reg.o \
+	vid_voodoo_render.o vid_voodoo_setup.o vid_voodoo_texture.o vid_wy700.o video.o vl82c480.o \
+	vt82c586b.o w83877tf.o w83977tf.o wd76c10.o x86seg.o x87.o x87_timings.o xi8088.c xtide.o zenith.o win-midi.o wx-main.o \
 	wx-config_sel.o wx-dialogbox.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o \
 	wx-sdl2-keyboard.o wx-sdl2-video.o wx-sdl2.o wx-config.o wx-deviceconfig.o wx-status.o \
 	wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display-win.o \
@@ -45,11 +47,12 @@ OBJ = 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer38
 	wx-joystickconfig.o wx-createdisc.o wx.res
 DBOBJ = cdrom_image.o dbopl.o nukedopl.o vid_cga_comp.o
 SIDOBJ = convolve.o convolve-sse.o envelope.o extfilt.o filter.o pot.o sid.o voice.o wave6581__ST.o wave6581_P_T.o wave6581_PS_.o wave6581_PST.o wave8580__ST.o wave8580_P_T.o wave8580_PS_.o wave8580_PST.o wave.o
+MVHDOBJ = cwalk.o libxml2_encoding.o minivhd_convert.o minivhd_create.o minivhd_io.o minivhd_manage.o minivhd_struct_rw.o minivhd_util.o
 
 LIBS = -Wl,--subsystem,windows -mthreads -mwindows -lwxmsw$(WXVERSION)u_xrc -lwxmsw$(WXVERSION)u_html -lwxmsw$(WXVERSION)u_adv -lwxbase$(WXVERSION)u_xml -lwxmsw$(WXVERSION)u_core -lwxbase$(WXVERSION)u -lwxtiff -lwxjpeg -lwxpng -lwxzlib -lwxregexu -lwxexpat -lkernel32 -lcomdlg32 -lwinspool -lcomctl32 -lole32 -loleaut32 -luuid -lrpcrt4 -ladvapi32 -lmingw32 -lopengl32 -lopenal32 -lstdc++ -lSDL2main -lSDL2 -lm -ldinput8 -ldxguid -ldxerr8 -luser32 -lgdi32 -lwinmm -limm32 -lole32 -loleaut32 -lshell32 -lversion -luuid -static-libgcc
 
-PCem-wx-SDL2.exe: $(OBJ) $(DBOBJ) $(SIDOBJ)
+PCem-wx-SDL2.exe: $(OBJ) $(DBOBJ) $(SIDOBJ) $(MVHDOBJ)
-	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) -o "PCem-wx-SDL2.exe" $(LIBS)
+	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) $(MVHDOBJ) -o "PCem-wx-SDL2.exe" $(LIBS)
 	strip -s PCem-wx-SDL2.exe
 
 all : PCem-wx-SDL2.exe

src/Makefile.mingw-wx-sdl2-network

@@ -1,4 +1,4 @@
-VPATH = . dosbox resid-fp
+VPATH = . dosbox resid-fp minivhd
 CPP  = g++
 CC   = gcc
 WINDRES = windres.exe
@@ -6,33 +6,54 @@ WXVERSION = 31
 WXINCLUDE = e:/mingwget/include/wx/
 CFLAGS = -O3 -march=i686 -fomit-frame-pointer -msse2 -mstackrealign -Werror -fno-strict-aliasing -DUSE_NETWORKING
 CXXFLAGS = $(CFLAGS)
-OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer386sx.o ali1429.o amstrad.o cbm_io.o cdrom-ioctl.o cdrom-image.o \
+OBJ = 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o 808x.o 82091aa.o acc2036.o acc2168.o acc3221.o acer386sx.o ali1429.o amstrad.o cassette.o \
-	cmd640.o codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_common.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86.o compaq.o config.o cpu.o \
+	cbm_io.o cdrom-ioctl.o cdrom-image.o cmd640.o codegen.o codegen_accumulate.o codegen_allocator.o \
-	device.o dells200.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o hdd.o hdd_esdi.o hdd_file.o headland.o i430lx.o i430fx.o \
+	codegen_backend_x86.o codegen_backend_x86_ops.o codegen_backend_x86_ops_fpu.o codegen_backend_x86_ops_sse.o \
-	i430vx.o ide.o ide_atapi.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o joystick_standard.o joystick_sw_pad.o joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o \
+	codegen_backend_x86_uops.o codegen_block.o codegen_ir.o codegen_ops.o \
-	keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o \
+	codegen_ops_3dnow.o codegen_ops_branch.o codegen_ops_arith.o codegen_ops_fpu_arith.o \
-	mouse_serial.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o opti495.o paths.o pc.o pc87306.o pci.o pic.o piix.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o rom.o rtc.o rtc_tc8521.o \
+	codegen_ops_fpu_constant.o codegen_ops_fpu_loadstore.o codegen_ops_fpu_misc.o codegen_ops_helpers.o codegen_ops_jump.o \
-	scat.o scsi.o scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_zip.o serial.o sio.o sis496.o sl82c460.o sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_cms.o sound_dbopl.o \
+	codegen_ops_logic.o codegen_ops_misc.o codegen_ops_mmx_arith.o codegen_ops_mmx_cmp.o \
-	sound_emu8k.o sound_gus.o sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o sound_resid.o \
+	codegen_ops_mmx_loadstore.o codegen_ops_mmx_logic.o codegen_ops_mmx_pack.o codegen_ops_mmx_shift.o \
-	sound_sb.o sound_sb_dsp.o sound_sn76489.o sound_speaker.o sound_ssi2001.o sound_wss.o \
+	codegen_ops_mov.o codegen_ops_shift.o codegen_ops_stack.o codegen_reg.o codegen_timing_486.o \
-	sound_ym7128.o soundopenal.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o timer.o um8881f.o um8669f.o vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o \
+	codegen_timing_686.o codegen_timing_common.o codegen_timing_cyrixiii.o codegen_timing_k6.o codegen_timing_p6.o codegen_timing_pentium.o \
-	vid_ati28800.o vid_ati68860_ramdac.o vid_cga.o vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ega.o vid_et4000.o \
+	codegen_timing_winchip.o codegen_timing_winchip2.o compaq.o config.o cpu.o cpu_tables.o cs8230.o device.o \
-	vid_et4000w32.o vid_et4000w32i.o vid_genius.o vid_hercules.o vid_icd2061.o vid_ics2595.o vid_incolor.o vid_mda.o \
+	dells200.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o f82c710_upc.o fdc.o fdc37c665.o fdc37c93x.o fdd.o \
-	vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc1512.o vid_pc1640.o vid_pc200.o \
+	fdi2raw.o gameport.o hdd.o hdd_esdi.o hdd_file.o headland.o i430hx.o i430lx.o i430fx.o i430vx.o i440fx.o i440bx.o ide.o \
-	vid_pcjr.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o vid_stg_ramdac.o vid_svga.o \
+	ide_atapi.o ide_sff8038i.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o \
-	vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o \
+	joystick_standard.o joystick_sw_pad.o joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o \
-	vid_vga.o vid_voodoo.o vid_wy700.o video.o wd76c10.o x86seg.o x87.o xi8088.c xtide.o win-midi.o \
+	keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o \
-	wx-main.o wx-config_sel.o wx-dialogbox.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o wx-sdl2-keyboard.o wx-sdl2-video.o \
+	mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o mouse_serial.o \
-	wx-sdl2.o wx-config.o wx-deviceconfig.o wx-hostconfig.o wx-status.o wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display-win.o \
+	mvp3.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o opti495.o paths.o pc.o pc87306.o pc87307.o pci.o pic.o \
-	wx-sdl2-video-renderer.o wx-sdl2-video-gl3.o wx-glslp-parser.o wx-shader_man.o wx-shaderconfig.o wx-joystickconfig.o wx-createdisc.o wx.res
+	piix.o piix_pm.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o pzx.o rom.o rtc.o rtc_tc8521.o scamp.o scat.o scsi.o \
+	scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_ibm.o scsi_zip.o serial.o sio.o sis496.o sl82c460.o \
+	sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_azt2316a.o sound_cms.o sound_dbopl.o \
+	sound_emu8k.o sound_gus.o sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o \
+	sound_resid.o sound_sb.o sound_sb_dsp.o sound_sn76489.o sound_speaker.o sound_ssi2001.o sound_wss.o \
+	sound_ym7128.o soundopenal.o sst39sf010.o superxt.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o timer.o um8881f.o um8669f.o \
+	vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o vid_ati28800.o vid_ati68860_ramdac.o vid_cga.o \
+	vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ddc.o vid_ega.o vid_et4000.o vid_et4000w32.o \
+	vid_et4000w32i.o vid_genius.o vid_hercules.o vid_ht216.o vid_icd2061.o vid_ics2595.o vid_im1024.o vid_incolor.o vid_mda.o \
+	vid_mga.o vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc1512.o vid_pc1640.o vid_pc200.o \
+	vid_pcjr.o vid_pgc.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o vid_sigma.o vid_stg_ramdac.o vid_svga.o \
+	vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o \
+	vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_voodoo_banshee.o vid_voodoo_banshee_blitter.o \
+	vid_voodoo_blitter.o vid_voodoo_display.o vid_voodoo_fb.o vid_voodoo_fifo.o vid_voodoo_reg.o \
+	vid_voodoo_render.o vid_voodoo_setup.o vid_voodoo_texture.o vid_wy700.o video.o vl82c480.o \
+	vt82c586b.o w83877tf.o w83977tf.o wd76c10.o x86seg.o x87.o x87_timings.o xi8088.c xtide.o zenith.o win-midi.o wx-main.o \
+	wx-config_sel.o wx-dialogbox.o wx-hostconfig.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o \
+	wx-sdl2-keyboard.o wx-sdl2-video.o wx-sdl2.o wx-config.o wx-deviceconfig.o wx-status.o \
+	wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display-win.o \
+	wx-sdl2-video-renderer.o wx-sdl2-video-gl3.o wx-glslp-parser.o wx-shader_man.o wx-shaderconfig.o \
+	wx-joystickconfig.o wx-createdisc.o wx.res
 DBOBJ = cdrom_image.o dbopl.o nukedopl.o vid_cga_comp.o
 SIDOBJ = convolve.o convolve-sse.o envelope.o extfilt.o filter.o pot.o sid.o voice.o wave6581__ST.o wave6581_P_T.o wave6581_PS_.o wave6581_PST.o wave8580__ST.o wave8580_P_T.o wave8580_PS_.o wave8580_PST.o wave.o
+MVHDOBJ = cwalk.o libxml2_encoding.o minivhd_convert.o minivhd_create.o minivhd_io.o minivhd_manage.o minivhd_struct_rw.o minivhd_util.o
 NETOBJ = ne2000.o nethandler.o
 
 LIBS = -Wl,--subsystem,windows -mthreads -mwindows -lwxmsw$(WXVERSION)u_xrc -lwxmsw$(WXVERSION)u_html -lwxmsw$(WXVERSION)u_adv -lwxbase$(WXVERSION)u_xml -lwxmsw$(WXVERSION)u_core -lwxbase$(WXVERSION)u -lwxtiff -lwxjpeg -lwxpng -lwxzlib -lwxregexu -lwxexpat -lkernel32 -lcomdlg32 -lwinspool -lcomctl32 -lole32 -loleaut32 -luuid -lrpcrt4 -ladvapi32 -lmingw32 -lopengl32 -lopenal32 -lstdc++ -lSDL2main -lSDL2 -lm -ldinput8 -ldxguid -ldxerr8 -luser32 -lgdi32 -lwinmm -limm32 -lole32 -loleaut32 -lshell32 -lversion -luuid -static-libgcc -lwsock32 -liphlpapi
 
-PCem-wx-SDL2.exe: $(OBJ) $(DBOBJ) $(SIDOBJ) $(NETOBJ) libslirp.a
+PCem-wx-SDL2.exe: $(OBJ) $(DBOBJ) $(SIDOBJ) $(MVHDOBJ) $(NETOBJ) libslirp.a
-	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) $(NETOBJ) slirp/libslirp.a -o "PCem-wx-SDL2.exe" $(LIBS)
+	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) $(MVHDOBJ) $(NETOBJ) slirp/libslirp.a -o "PCem-wx-SDL2.exe" $(LIBS)
 	strip -s PCem-wx-SDL2.exe
 
 libslirp.a:

src/Makefile.osx64-wx-sdl2

@@ -1,51 +0,0 @@
-VPATH = . dosbox resid-fp
-CPP  = g++
-CC   = gcc
-WXRC = wxrc
-CFLAGS = -D__unix=1 -DPCEM_RENDER_WITH_TIMER -DPCEM_RENDER_TIMER_LOOP -Dfopen64=fopen -Dfseeko64=fseeko -Dftello64=ftello -Doff64_t=off_t -O3 -fomit-frame-pointer -msse2 -m64 $(shell wx-config --cxxflags) $(shell sdl2-config --cflags) -I/usr/local/opt/openal-soft/include -I/usr/local/include
-OBJ = 386.o 386_dynarec.o 386_dynarec_ops.o 808x.o acc2036.o acer386sx.o ali1429.o amstrad.o cbm_io.o cdrom-ioctl-osx.o cdrom-image.o cdrom-null.o \
-cmd640.o codegen.o codegen_ops.o codegen_timing_486.o codegen_timing_686.o codegen_timing_common.o codegen_timing_pentium.o codegen_timing_winchip.o codegen_x86-64.c compaq.o config.o cpu.o \
-device.o dells200.o disc.o disc_fdi.o disc_img.o disc_sector.o dma.o esdi_at.o fdc.o fdc37c665.o fdd.o fdi2raw.o gameport.o \
-hdd.o hdd_esdi.o hdd_file.o headland.o i430lx.o i430fx.o i430vx.o ide.o ide_atapi.o intel.o intel_flash.o io.o jim.o joystick_ch_flightstick_pro.o joystick_standard.o joystick_sw_pad.o \
-joystick_tm_fcs.o keyboard.o keyboard_amstrad.o keyboard_at.o keyboard_olim24.o keyboard_pcjr.o keyboard_xt.o \
-laserxt.o lpt.o lpt_dac.o lpt_dss.o mca.o mcr.o mem.o mem_bios.o mfm_at.o mfm_xebec.o model.o mouse.o mouse_msystems.o mouse_ps2.o mouse_serial.o neat.o nmi.o nvr.o nvr_tc8521.o olivetti_m24.o \
-opti495.o paths.o pc.o pc87306.o pci.o pic.o piix.o pit.o ppi.o ps1.o ps2.o ps2_mca.o ps2_nvr.o rom.o rtc.o rtc_tc8521.o scat.o scsi.o scsi_53c400.o scsi_aha1540.o scsi_cd.o scsi_hd.o scsi_zip.o \
-serial.o sio.o sis496.o sl82c460.o sound.o sound_ad1848.o sound_adlib.o sound_adlibgold.o sound_audiopci.o sound_cms.o sound_emu8k.o sound_gus.o \
-sound_mpu401_uart.o sound_opl.o sound_pas16.o sound_ps1.o sound_pssj.o sound_sb.o sound_sb_dsp.o sound_sn76489.o \
-sound_speaker.o sound_ssi2001.o sound_wss.o sound_ym7128.o soundopenal.o t1000.o t3100e.o tandy_eeprom.o tandy_rom.o \
-timer.o um8669f.o um8881f.o vid_ati_eeprom.o vid_ati_mach64.o vid_ati18800.o vid_ati28800.o \
-vid_ati68860_ramdac.o vid_cga.o vid_cl5429.o vid_colorplus.o vid_compaq_cga.o vid_ega.o vid_et4000.o vid_et4000w32.o vid_genius.o vid_hercules.o \
-vid_icd2061.o vid_ics2595.o vid_incolor.o vid_mda.o vid_olivetti_m24.o vid_oti037.c vid_oti067.o vid_paradise.o vid_pc200.o \
-vid_pc1512.o vid_pc1640.o vid_pcjr.o vid_ps1_svga.o vid_s3.o vid_s3_virge.o vid_sdac_ramdac.o \
-vid_stg_ramdac.o vid_svga.o vid_svga_render.o vid_t1000.o vid_t3100e.o vid_tandy.o vid_tandysl.o vid_tgui9440.o \
-vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o vid_voodoo.o vid_wy700.o video.o wd76c10.o \
-x86seg.o x87.o xi8088.c xtide.o sound_dbopl.o sound_resid.o \
-wx-main.o wx-config_sel.o wx-dialogbox.o wx-utils.o wx-app.o wx-sdl2-joystick.o wx-sdl2-mouse.o wx-sdl2-keyboard.o wx-sdl2-video.o wx-sdl2-midi.o \
-wx-sdl2.o wx-config.o wx-deviceconfig.o wx-status.o wx-sdl2-status.o wx-resources.o wx-thread.o wx-common.o wx-sdl2-display.o \
-wx-sdl2-video-renderer.o wx-sdl2-video-gl3.o wx-glslp-parser.o wx-shader_man.o wx-shaderconfig.o wx-joystickconfig.o wx-createdisc.o
-DBOBJ = cdrom_image.o dbopl.o nukedopl.o vid_cga_comp.o
-SIDOBJ = convolve.o convolve-sse.o envelope.o extfilt.o filter.o pot.o sid.o voice.o wave6581__ST.o wave6581_P_T.o wave6581_PS_.o wave6581_PST.o wave8580__ST.o wave8580_P_T.o wave8580_PS_.o wave8580_PST.o wave.o
-
-LIBS = -lopenal -lstdc++ -lpthread -lm $(shell wx-config --libs) $(shell sdl2-config --libs) -L/usr/local/opt/openal-soft/lib -framework OpenGL
-
-PCem64-wx-SDL2: $(OBJ) $(DBOBJ) $(SIDOBJ)
-	$(CC) $(OBJ) $(DBOBJ) $(SIDOBJ) -o "PCem64-wx-SDL2" $(LIBS)
-
-all : PCem64-wx-SDL2
-
-clean :
-	rm *.o
-	rm PCem64-wx-SDL2
-	
-wx-resources.o : pc.xrc
-	$(WXRC) -c pc.xrc -o wx-resources.cpp
-	$(CPP) $(CFLAGS) -c wx-resources.cpp
-
-%.o : %.c
-	$(CC) $(CFLAGS) -c $<
-
-%.o : %.cc
-	$(CPP) $(CFLAGS) -c $<
-
-%.o : %.cpp
-	$(CPP) $(CFLAGS) -c $<

src/acc2036.c

@@ -89,6 +89,9 @@ static uint8_t acc2036_read(uint16_t addr, void *p)
         if (!(addr & 1))
                 return acc2036.reg_idx;
 
+        if (acc2036.reg_idx >= 0xbc)
+                return 0xff;
+                
         return acc2036.regs[acc2036.reg_idx];
 }
 

src/acc2168.c

@@ -0,0 +1,119 @@
+#include "ibm.h"
+#include "acc2168.h"
+#include "cpu.h"
+#include "io.h"
+#include "mem.h"
+#include "x86.h"
+
+static struct
+{
+        int reg_idx;
+        uint8_t regs[256];
+        uint8_t port_62;
+} acc2168;
+
+static void acc2168_shadow_recalc()
+{
+        if (acc2168.regs[0x02] & 8)
+        {
+                switch (acc2168.regs[0x02] & 0x30)
+                {
+                        case 0x00:
+                        mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
+                        break;
+                        case 0x10:
+                        mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        break;
+                        case 0x20:
+                        mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        break;
+                        case 0x30:
+                        mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
+                        break;
+                }
+        }
+        else
+                mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+
+        if (acc2168.regs[0x02] & 4)
+        {
+                switch (acc2168.regs[0x02] & 0x30)
+                {
+                        case 0x00:
+                        mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
+                        break;
+                        case 0x10:
+                        mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        break;
+                        case 0x20:
+                        mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        break;
+                        case 0x30:
+                        mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
+                        break;
+                }
+        }
+        else
+                mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+}
+
+static void acc2168_write(uint16_t addr, uint8_t val, void *p)
+{
+//        pclog("acc2168_write: addr=%04x val=%02x\n", addr, val);
+        if (!(addr & 1))
+                acc2168.reg_idx = val;
+        else
+        {
+                acc2168.regs[acc2168.reg_idx] = val;
+//                pclog("acc2168_write: idx=%02x val=%02x %04x:%04x\n", acc2168.reg_idx, val, CS,cpu_state.pc);
+
+                switch (acc2168.reg_idx)
+                {
+                        case 0x02:
+                        acc2168_shadow_recalc();
+                        break;
+                }
+        }
+}
+
+static uint8_t acc2168_read(uint16_t addr, void *p)
+{
+        if (!(addr & 1))
+                return acc2168.reg_idx;
+
+//        pclog("acc2168_read: idx=%02x val=%02x\n", acc2168.reg_idx, acc2168.regs[acc2168.reg_idx]);
+        return acc2168.regs[acc2168.reg_idx];
+}
+
+static uint8_t port78_read(uint16_t addr, void *p)
+{
+        return 0;
+}
+
+static uint8_t port92_read(uint16_t addr, void *p)
+{
+        return acc2168.port_62 | 0xfc;
+}
+
+static void port92_write(uint16_t addr, uint8_t val, void *p)
+{
+        if ((mem_a20_alt ^ val) & 2)
+        {
+                mem_a20_alt = val & 2;
+                mem_a20_recalc();
+        }
+        if ((~acc2168.port_62 & val) & 1)
+        {
+                softresetx86();
+                cpu_set_edx();
+        }
+        acc2168.port_62 = val | 0xfC;
+}
+
+void acc2168_init()
+{
+        memset(&acc2168, 0, sizeof(acc2168));
+        io_sethandler(0x00f2, 0x0002, acc2168_read, NULL, NULL, acc2168_write, NULL, NULL,  NULL);
+        io_sethandler(0x0078, 0x0001, port78_read, NULL, NULL, NULL, NULL, NULL,  NULL);
+        io_sethandler(0x0092, 0x0001, port92_read, NULL, NULL, port92_write, NULL, NULL,  NULL);
+}

src/acc2168.h

@@ -0,0 +1 @@
+void acc2168_init();

src/acc3221.c

@@ -0,0 +1,122 @@
+#include "ibm.h"
+#include "acc3221.h"
+#include "fdc.h"
+#include "ide.h"
+#include "io.h"
+#include "lpt.h"
+#include "serial.h"
+
+static struct
+{
+        int reg_idx;
+        uint8_t regs[256];
+} acc3221;
+
+#define REG_BE_LPT1_DISABLE (1 << 4)
+
+#define REG_DB_SERIAL1_DISABLE (1 << 4)
+#define REG_DB_SERIAL2_DISABLE (1 << 1)
+
+#define REG_DE_SIRQ3_SOURCE  (3 << 6)
+#define REG_DE_SIRQ3_SERIAL1 (1 << 6)
+#define REG_DE_SIRQ3_SERIAL2 (3 << 6)
+
+#define REG_DE_SIRQ4_SOURCE  (3 << 4)
+#define REG_DE_SIRQ4_SERIAL1 (1 << 4)
+#define REG_DE_SIRQ4_SERIAL2 (3 << 4)
+
+#define REG_FB_FDC_DISABLE (1 << 1)
+
+#define REG_FE_IDE_DISABLE (1 << 1)
+
+static void acc3221_write(uint16_t addr, uint8_t val, void *p)
+{
+        if (!(addr & 1))
+                acc3221.reg_idx = val;
+        else
+        {
+                acc3221.regs[acc3221.reg_idx] = val;
+//                pclog("Write ACC2036 R%02x %02x %04x:%04x %i\n", acc2036.reg_idx, val, CS,cpu_state.pc, ins);
+
+                if (acc3221.reg_idx >= 0xbc)
+                {
+//                        pclog("Write ACC3221 R%02x %02x %04x:%04x %i\n", acc3221.reg_idx, val, CS,cpu_state.pc, ins);
+                        fdc_remove();
+                        if (!(acc3221.regs[0xfb] & REG_FB_FDC_DISABLE))
+                                fdc_add();
+
+                        serial1_remove();
+                        if (!(acc3221.regs[0xdb] & REG_DB_SERIAL1_DISABLE))
+                        {
+                                uint16_t addr = (acc3221.regs[0xdc] & 0x7f) << 2;
+
+                                if ((acc3221.regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL1)
+                                {
+//                                        pclog("COM1 addr %03x IRQ 3\n", addr);
+                                        serial1_set(addr, 3);
+                                }
+                                else if ((acc3221.regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL1)
+                                {
+//                                        pclog("COM1 addr %03x IRQ 4\n", addr);
+                                        serial1_set(addr, 4);
+                                }
+//                                else
+//                                        pclog("COM1 addr %03x no IRQ\n", addr);
+                        }
+//                        else
+//                                pclog("COM1 disabled\n");
+
+                        serial2_remove();
+                        if (!(acc3221.regs[0xdb] & REG_DB_SERIAL2_DISABLE))
+                        {
+                                uint16_t addr = (acc3221.regs[0xdd] & 0x7f) << 2;
+
+                                if ((acc3221.regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL2)
+                                {
+//                                        pclog("COM2 addr %03x IRQ 3\n", addr);
+                                        serial2_set(addr, 3);
+                                }
+                                else if ((acc3221.regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL2)
+                                {
+//                                        pclog("COM2 addr %03x IRQ 4\n", addr);
+                                        serial2_set(addr, 4);
+                                }
+//                                else
+//                                        pclog("COM2 addr %03x no IRQ\n", addr);
+                        }
+//                        else
+//                                pclog("COM2 disabled\n");
+
+                        lpt1_remove();
+                        lpt2_remove();
+                        if (!(acc3221.regs[0xbe] & REG_BE_LPT1_DISABLE))
+                        {
+//                                pclog("LPT1 addr %03x\n", acc3221.regs[0xbf] << 2);
+                                lpt1_init(acc3221.regs[0xbf] << 2);
+                        }
+//                        else
+//                                pclog("LPT1 disabled\n");
+
+                        ide_pri_disable();
+                        if (!(acc3221.regs[0xfe] & REG_FE_IDE_DISABLE))
+                                ide_pri_enable();
+                }
+        }
+}
+
+static uint8_t acc3221_read(uint16_t addr, void *p)
+{
+        if (!(addr & 1))
+                return acc3221.reg_idx;
+
+        if (acc3221.reg_idx < 0xbc)
+                return 0xff;
+                
+        return acc3221.regs[acc3221.reg_idx];
+}
+
+void acc3221_init()
+{
+        memset(&acc3221, 0, sizeof(acc3221));
+        io_sethandler(0x00f2, 0x0002, acc3221_read, NULL, NULL, acc3221_write, NULL, NULL,  NULL);
+}

src/acc3221.h

@@ -0,0 +1 @@
+void acc3221_init();

src/amstrad.c

@@ -5,11 +5,14 @@
 #include "lpt.h"
 #include "mouse.h"
 #include "video.h"
+#include "fdc.h"
+#include "x86.h"
 
 #include "amstrad.h"
 
 static uint8_t amstrad_dead;
 int amstrad_latch = 0;
+static uint8_t amstrad_language;
 
 uint8_t amstrad_read(uint16_t port, void *priv)
 {
@@ -21,16 +24,19 @@ uint8_t amstrad_read(uint16_t port, void *priv)
                 case 0x378:
                 return lpt1_read(port, NULL);
                 case 0x379:
-                return lpt1_read(port, NULL) | 7;
+                return lpt1_read(port, NULL) | (amstrad_language & 7);
                 case 0x37a:
                 temp = lpt1_read(port, NULL) & 0x1f;
                 if (romset == ROM_PC1512) return temp | 0x20;
-                if (romset == ROM_PC200)
+                if (romset == ROM_PC200 || romset == ROM_PPC512)
                 {
+                        if (fdc_discchange_read())
+                                temp |= 0x20;
+/* DIP switches 4,5: Initial video mode */
                         if (video_is_cga())
-                                temp |= 0x80;
+                                temp |= 0x80;	/* CGA 80 */
                         else if (video_is_mda())
-                                temp |= 0xc0;
+                                temp |= 0xc0;	/* MDA */
                         return temp;
                 }
                 if (romset == ROM_PC1640)
@@ -55,8 +61,13 @@ uint8_t amstrad_read(uint16_t port, void *priv)
                 }
                 return temp;
                 case 0x3de:
-                return 0x20; /*PC200 - use external video. If internal video is being used
+                if (romset == ROM_PC200 || romset == ROM_PPC512)
-                               then this port is handled in vid_pc200.c*/
+		{
+/* Read DIP switches / internal display adapter status. This code is only
+ * reached if the IDA is disabled; if it is enabled this read will be
+ * handled by the video card */
+		}
+                return 0x20; /* Disable IDA */
                 case 0xdead:
                 return amstrad_dead;
         }
@@ -67,6 +78,10 @@ void amstrad_write(uint16_t port, uint8_t val, void *priv)
 {
         switch (port)
         {
+                case 0x66:
+                softresetx86();
+                break;
+                
                 case 0x378:
                 case 0x379:
                 case 0x37a:
@@ -151,8 +166,170 @@ void amstrad_init()
         
         io_sethandler(0x0078, 0x0001, amstrad_mouse_read, NULL, NULL, amstrad_mouse_write, NULL, NULL,  NULL);
         io_sethandler(0x007a, 0x0001, amstrad_mouse_read, NULL, NULL, amstrad_mouse_write, NULL, NULL,  NULL);
+        io_sethandler(0x0066, 0x0001, NULL,               NULL, NULL, amstrad_write,       NULL, NULL,  NULL);
         io_sethandler(0x0378, 0x0003, amstrad_read,       NULL, NULL, amstrad_write,       NULL, NULL,  NULL);
         io_sethandler(0xdead, 0x0001, amstrad_read,       NULL, NULL, amstrad_write,       NULL, NULL,  NULL);
-        if (romset == ROM_PC200 && gfxcard != GFX_BUILTIN)        
+        if ((romset == ROM_PC200 || romset == ROM_PPC512) && gfxcard != GFX_BUILTIN)        
                 io_sethandler(0x03de, 0x0001, amstrad_read,       NULL, NULL, amstrad_write,       NULL, NULL,  NULL);
+
+	
 }
+
+static void *ams1512_init()
+{
+	amstrad_language = device_get_config_int("language");
+	return &amstrad_language;
+}
+
+device_config_t ams1512_config[] = 
+{
+	{
+                .name = "language",
+                .description = "BIOS language",
+                .type = CONFIG_SELECTION,
+		.selection =
+		{
+			{
+				.description = "English",
+				.value = 7
+			},
+			{
+				.description = "German",
+				.value = 6
+			},
+			{
+				.description = "French",
+				.value = 5
+			},
+			{
+				.description = "Spanish",
+				.value = 4
+			},
+			{
+				.description = "Danish",
+				.value = 3
+			},
+			{
+				.description = "Swedish",
+				.value = 2
+			},
+			{
+				.description = "Italian",
+				.value = 1
+			},
+			{
+				.description = "Diagnostic mode",
+				.value = 0
+			},
+			{
+				.description = ""
+			}
+		},
+                .default_int = 7
+	},
+        {
+                .type = -1
+        }
+};
+	
+
+device_config_t ams2086_config[] = 
+{
+	{
+                .name = "language",
+                .description = "BIOS language",
+                .type = CONFIG_SELECTION,
+		.selection =
+		{
+			{
+				.description = "English",
+				.value = 7
+			},
+			{
+				.description = "Diagnostic mode",
+				.value = 0
+			},
+			{
+				.description = ""
+			}
+		},
+                .default_int = 7
+	},
+        {
+                .type = -1
+        }
+};
+		
+
+
+device_config_t ams3086_config[] = 
+{
+	{
+                .name = "language",
+                .description = "BIOS language",
+                .type = CONFIG_SELECTION,
+		.selection =
+		{
+			{
+				.description = "English",
+				.value = 7
+			},
+			{
+				.description = "Diagnostic mode",
+				.value = 3
+			},
+			{
+				.description = ""
+			}
+		},
+                .default_int = 7
+	},
+        {
+                .type = -1
+        }
+};
+	
+
+	
+
+device_t ams1512_device =
+{
+        "Amstrad PC1512 (BIOS)",
+        0,
+        ams1512_init,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        ams1512_config
+};
+
+
+
+device_t ams2086_device =
+{
+        "Amstrad PC2086 (BIOS)",
+        0,
+        ams1512_init,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        ams2086_config
+};
+
+
+device_t ams3086_device =
+{
+        "Amstrad PC3086 (BIOS)",
+        0,
+        ams1512_init,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        ams3086_config
+};

src/amstrad.h

@@ -1,10 +1,15 @@
 #include "mouse.h"
+#include "device.h"
 
 void amstrad_init();
 
 extern mouse_t mouse_amstrad;
 extern int amstrad_latch;
 
+extern device_t ams1512_device;
+extern device_t ams2086_device;
+extern device_t ams3086_device;
+
 enum
 {
         AMSTRAD_NOLATCH,

src/cassette.c

@@ -0,0 +1,187 @@
+/************************************************************************
+
+    PCem: IBM 5150 Cassette support
+
+    Copyright (C) 2019  John Elliott <seasip.webmaster@gmail.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*************************************************************************/
+
+#include <stdlib.h>
+#include "ibm.h"
+#include "cpu.h"
+#include "x86.h"
+#include "device.h"
+#include "pzx.h"
+
+char cassettefn[256];
+
+typedef struct cassette_t 
+{
+	uint8_t motor;		/* Motor status */
+	pzxfile_t pzx;
+	int cycles_last;	/* Cycle count at last cassette poll */
+
+} cassette_t;
+
+extern device_t cassette_device;
+
+
+static cassette_t *st_cas;
+
+
+
+#define CAS_LOG(x) pclog x
+// #define CAS_LOG(x) 
+
+
+/* The PCem CPU uses IBM cycles (4.77MHz). PZX uses Spectrum cycles (3.5MHz)
+ * so scale accordingly. */
+static int32_t pzx_cycles(int32_t pc)
+{
+	double d = pc;
+
+	return (int32_t)(((d * 3.5) / 4.772728) + 0.5);
+}
+
+void cassette_eject(void)
+{
+	if (st_cas->pzx.input)
+	{
+		pzx_close(&st_cas->pzx);
+	}
+	cassettefn[0] = 0;
+}
+
+void cassette_load(const char *filename)
+{
+	FILE *fp;
+	unsigned char magic[8];
+
+	if (!filename) return;
+
+	fp = fopen(filename, "rb");
+	if (!fp)
+	{
+		/* Warn user? */
+		CAS_LOG(("Failed to open cassette input %s\n", filename));
+		return;
+	}
+	memset(magic, 0, sizeof(magic));
+	fread(magic, 1, sizeof(magic), fp);	
+
+	/* Check for PZX signature. In due course support could be added for
+	 * other formats like TZX */
+	if (!memcmp(magic, "PZXT", 4))
+	{
+		const char *result;
+
+		result = pzx_open(&st_cas->pzx, fp);
+
+		if (result)
+		{
+			CAS_LOG(("Failed to open %s as PZX: %s\n",
+				filename, result));
+			fclose(fp);
+			return;			
+		}
+		strcpy(cassettefn, filename);
+	}
+}
+
+
+uint8_t cassette_input(void)
+{
+	int ticks;
+
+	/* While motor is off, result is loopback */
+	if (!st_cas->motor)
+	{
+		return ppispeakon;
+	}
+	/* If there is no tapefile open don't try to extract data */
+	if (st_cas->pzx.input == NULL) return 0;
+	/* Otherwise see how many ticks there have been since the last input */
+	if (st_cas->cycles_last == -1) 
+	{
+		st_cas->cycles_last = cycles;
+	}
+	if (cycles <= st_cas->cycles_last)
+	{
+		ticks = (st_cas->cycles_last - cycles);
+	}
+	else
+	{
+		ticks = (st_cas->cycles_last + (cpu_get_speed() / 100) - cycles);
+	}
+	st_cas->cycles_last = cycles;
+
+	return pzx_advance(&st_cas->pzx, pzx_cycles(ticks));	
+}
+
+
+
+void cassette_set_motor(uint8_t on)
+{
+	if (on && !st_cas->motor)
+	{
+		CAS_LOG(("Start cassette motor\n"));
+		st_cas->cycles_last = -1;
+	}
+	if (st_cas->motor && !on)
+	{
+		CAS_LOG(("Stop cassette motor\n"));
+		st_cas->cycles_last = -1;
+	}
+	st_cas->motor = on;
+}
+
+
+static void *cassette_init(void)
+{
+	cassette_t *cas = malloc(sizeof(cassette_t));
+
+	memset(cas, 0, sizeof(cassette_t));
+	pzx_init(&cas->pzx);
+
+	st_cas = cas;
+	return cas;
+}
+
+
+static void cassette_close(void *p)
+{
+	cassette_t *cas = (cassette_t *)p;
+
+	pzx_close(&cas->pzx);
+
+	free(cas);
+}
+
+
+device_t cassette_device = 
+{
+	"Cassette",
+	0,
+	cassette_init,
+	cassette_close,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL
+};
+

src/cassette.h

@@ -0,0 +1,30 @@
+/************************************************************************
+
+    PCem: IBM 5150 cassette support
+
+    Copyright (C) 2019  John Elliott <seasip.webmaster@gmail.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*************************************************************************/
+
+extern device_t cassette_device;
+
+uint8_t cassette_input(void);
+void cassette_set_motor(uint8_t on);
+void cassette_eject(void);
+void cassette_load(const char *filename);
+
+extern char cassettefn[256];

src/cdrom-ioctl.c

@@ -451,8 +451,8 @@ static int ioctl_readsector(uint8_t *b, int sector, int count)
         status = ReadFile(hIOCTL, b, count*2048, (LPDWORD)&size, NULL);
         ioctl_close();
 
-        /*If the read failed, try again using SPTI*/
+        /*If the read 'succeeded' but didn't read all required data, try again using SPTI*/
-        if (!status || size != count*2048)
+        if (status && size != count*2048)
         {
                 uint8_t cmd[12] = { 0xbe, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 };
                 SCSI_PASS_THROUGH_DIRECT_WITH_BUFFER swb;

src/codegen.c

@@ -22,17 +22,19 @@ static struct
         x86seg *op_ea_seg;
         uint32_t op_32;
         int first_uop;
+        int TOP;
 } codegen_instructions[MAX_INSTRUCTION_COUNT];
 
-int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction)
+int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction, int *TOP)
 {
         int c;
         
-        for (c = 0; c < block->ins; c++)
+        for (c = 0; c <= block->ins; c++)
         {
                 if (codegen_instructions[c].pc == pc)
                 {
                         *first_instruction = c;
+                        *TOP = codegen_instructions[c].TOP;
                         return codegen_instructions[c].first_uop;
                 }
         }
@@ -366,7 +368,7 @@ static uint8_t opcode_modrm[256] =
 static uint8_t opcode_0f_modrm[256] =
 {
         1, 1, 1, 1,  0, 0, 0, 0,  0, 0, 0, 0,  0, 1, 0, 1, /*00*/
-        0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*10*/
+        0, 0, 0, 0,  0, 0, 0, 0,  1, 1, 1, 1,  1, 1, 1, 1, /*10*/
         1, 1, 1, 1,  1, 1, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*20*/
         0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0, /*30*/
 
@@ -590,6 +592,7 @@ generate_call:
         codegen_instructions[block->ins].op_ssegs = last_op_ssegs;
         codegen_instructions[block->ins].op_ea_seg = last_op_ea_seg;
         codegen_instructions[block->ins].op_32 = last_op_32;
+        codegen_instructions[block->ins].TOP = cpu_state.TOP;
         codegen_instructions[block->ins].first_uop = ir->wr_pos;
 
         codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);

src/codegen.h

@@ -374,7 +374,9 @@ extern codegen_timing_t codegen_timing_686;
 extern codegen_timing_t codegen_timing_486;
 extern codegen_timing_t codegen_timing_winchip;
 extern codegen_timing_t codegen_timing_winchip2;
+extern codegen_timing_t codegen_timing_cyrixiii;
 extern codegen_timing_t codegen_timing_k6;
+extern codegen_timing_t codegen_timing_p6;
 
 void codegen_timing_set(codegen_timing_t *timing);
 
@@ -404,7 +406,7 @@ extern int codegen_in_recompile;
 
 void codegen_generate_reset();
 
-int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction);
+int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction, int *TOP);
 void codegen_set_loop_start(struct ir_data_t *ir, int first_instruction);
 
 #ifdef DEBUG_EXTRA

src/codegen_allocator.c

@@ -1,6 +1,7 @@
 #if defined(__linux__) || defined(__APPLE__)
 #include <sys/mman.h>
 #include <unistd.h>
+#include <stdlib.h>
 #endif
 #if defined WIN32 || defined _WIN32 || defined _WIN32
 #include <windows.h>
@@ -29,6 +30,10 @@ void codegen_allocator_init()
 
 #if defined WIN32 || defined _WIN32 || defined _WIN32
         mem_block_alloc = VirtualAlloc(NULL, MEM_BLOCK_NR * MEM_BLOCK_SIZE, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
+        /* TODO: check deployment target: older Intel-based versions of macOS don't play
+           nice with MAP_JIT. */
+#elif defined(__APPLE__) && defined(MAP_JIT)
+        mem_block_alloc = mmap(0, MEM_BLOCK_NR * MEM_BLOCK_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_ANON|MAP_PRIVATE|MAP_JIT, 0, 0);
 #else
         mem_block_alloc = mmap(0, MEM_BLOCK_NR * MEM_BLOCK_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_ANON|MAP_PRIVATE, 0, 0);
 #endif

src/codegen_backend.h

@@ -1,3 +1,6 @@
+#ifndef _CODEGEN_BACKEND_H_
+#define _CODEGEN_BACKEND_H_
+
 //#ifdef __amd64__
 //#include "codegen_x86-64.h"
 #if defined __amd64__
@@ -25,5 +28,16 @@ typedef int (*uOpFn)(codeblock_t *codeblock, struct uop_t *uop);
 
 extern const uOpFn uop_handlers[];
 
-extern int codegen_host_reg_list[CODEGEN_HOST_REGS];
+/*Register will not be preserved across function calls*/
-extern int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS];
+#define HOST_REG_FLAG_VOLATILE (1 << 0)
+
+typedef struct host_reg_def_t
+{
+        int reg;
+        int flags;
+} host_reg_def_t;
+
+extern host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS];
+extern host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS];
+
+#endif

src/codegen_backend_arm.c

@@ -38,27 +38,27 @@ void *codegen_fp_round;
 void *codegen_gpf_rout;
 void *codegen_exit_rout;
 
-int codegen_host_reg_list[CODEGEN_HOST_REGS] =
+host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
 {
-        REG_R4,
+        {REG_R4, 0},
-        REG_R5,
+        {REG_R5, 0},
-        REG_R6,
+        {REG_R6, 0},
-	REG_R7,
+	{REG_R7, 0},
-	REG_R8,
+	{REG_R8, 0},
-	REG_R9,
+	{REG_R9, 0},
-	REG_R11,
+	{REG_R11, 0}
 };
 
-int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
+host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
 {
-        REG_D8,
+        {REG_D8, 0},
-        REG_D9,
+        {REG_D9, 0},
-        REG_D10,
+        {REG_D10, 0},
-	REG_D11,
+	{REG_D11, 0},
-	REG_D12,
+	{REG_D12, 0},
-	REG_D13,
+	{REG_D13, 0},
-	REG_D14,
+	{REG_D14, 0},
-	REG_D15
+	{REG_D15, 0}
 };
 
 static void build_load_routine(codeblock_t *block, int size, int is_float)

src/codegen_backend_arm64.c

@@ -39,30 +39,30 @@ void *codegen_fp_round_quad;
 void *codegen_gpf_rout;
 void *codegen_exit_rout;
 
-int codegen_host_reg_list[CODEGEN_HOST_REGS] =
+host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
 {
-        REG_X19,
+        {REG_X19, 0},
-        REG_X20,
+        {REG_X20, 0},
-        REG_X21,
+        {REG_X21, 0},
-	REG_X22,
+	{REG_X22, 0},
-	REG_X23,
+	{REG_X23, 0},
-        REG_X24,
+        {REG_X24, 0},
-        REG_X25,
+        {REG_X25, 0},
-	REG_X26,
+	{REG_X26, 0},
-	REG_X27,
+	{REG_X27, 0},
-	REG_X28
+	{REG_X28, 0}
 };
 
-int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
+host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
 {
-        REG_V8,
+        {REG_V8, 0},
-        REG_V9,
+        {REG_V9, 0},
-        REG_V10,
+        {REG_V10, 0},
-	REG_V11,
+	{REG_V11, 0},
-	REG_V12,
+	{REG_V12, 0},
-        REG_V13,
+        {REG_V13, 0},
-        REG_V14,
+        {REG_V14, 0},
-	REG_V15
+	{REG_V15, 0}
 };
 
 static void build_load_routine(codeblock_t *block, int size, int is_float)

src/codegen_backend_arm64_uops.c

@@ -839,8 +839,9 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
 
 	host_arm64_branch_set_offset(branch_ptr, &block->data[block_pos]);
 
-	host_arm64_STR_IMM_W(block, REG_WZR, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[0] - (uintptr_t)&cpu_state);
+	host_arm64_mov_imm(block, REG_TEMP, 0x01010101);
-	host_arm64_STR_IMM_W(block, REG_WZR, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[4] - (uintptr_t)&cpu_state);
+	host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[0] - (uintptr_t)&cpu_state);
+	host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[4] - (uintptr_t)&cpu_state);
 	host_arm64_STR_IMM_W(block, REG_WZR, REG_CPUSTATE, (uintptr_t)&cpu_state.TOP - (uintptr_t)&cpu_state);
 	host_arm64_STRB_IMM(block, REG_WZR, REG_CPUSTATE, (uintptr_t)&cpu_state.ismmx - (uintptr_t)&cpu_state);
 

src/codegen_backend_arm_uops.c

@@ -910,9 +910,10 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
 
 	*branch_ptr |= ((((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_ptr) - 8) & 0x3fffffc) >> 2;
 
-        host_arm_MOV_IMM(block, REG_TEMP, 0);
+        host_arm_MOV_IMM(block, REG_TEMP, 0x01010101);
 	host_arm_STR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[0] - (uintptr_t)&cpu_state);
 	host_arm_STR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.tag[4] - (uintptr_t)&cpu_state);
+        host_arm_MOV_IMM(block, REG_TEMP, 0);
 	host_arm_STR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.TOP - (uintptr_t)&cpu_state);
 	host_arm_STRB_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.ismmx - (uintptr_t)&cpu_state);
 

src/codegen_backend_x86-64.c

@@ -13,6 +13,7 @@
 #if defined(__linux__) || defined(__APPLE__)
 #include <sys/mman.h>
 #include <unistd.h>
+#include <stdlib.h>
 #endif
 #if defined WIN32 || defined _WIN32 || defined _WIN32
 #include <windows.h>
@@ -35,22 +36,32 @@ void *codegen_mem_store_double;
 void *codegen_gpf_rout;
 void *codegen_exit_rout;
 
-int codegen_host_reg_list[CODEGEN_HOST_REGS] =
+host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
 {
-        REG_EAX,
+        /*Note: while EAX and EDX are normally volatile registers under x86
-        REG_EBX,
+          calling conventions, the recompiler will explicitly save and restore
-        REG_EDX
+          them across funcion calls*/
+        {REG_EAX, 0},
+        {REG_EBX, 0},
+        {REG_EDX, 0}
 };
 
-int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
+host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
 {
-        REG_XMM0,
+#if WIN64
-        REG_XMM1,
+        /*Windows x86-64 calling convention preserves XMM6-XMM15*/
-        REG_XMM2,
+        {REG_XMM6, 0},
-        REG_XMM3,
+        {REG_XMM7, 0},
-        REG_XMM4,
+#else
-        REG_XMM5,
+        /*System V AMD64 calling convention does not preserve any XMM registers*/
-        REG_XMM6
+        {REG_XMM6, HOST_REG_FLAG_VOLATILE},
+        {REG_XMM7, HOST_REG_FLAG_VOLATILE},
+#endif
+        {REG_XMM1, HOST_REG_FLAG_VOLATILE},
+        {REG_XMM2, HOST_REG_FLAG_VOLATILE},
+        {REG_XMM3, HOST_REG_FLAG_VOLATILE},
+        {REG_XMM4, HOST_REG_FLAG_VOLATILE},
+        {REG_XMM5, HOST_REG_FLAG_VOLATILE}
 };
 
 static void build_load_routine(codeblock_t *block, int size, int is_float)
@@ -278,12 +289,6 @@ void codegen_backend_init()
 {
         codeblock_t *block;
         int c;
-#if defined(__linux__) || defined(__APPLE__)
-	void *start;
-	size_t len;
-	long pagesize = sysconf(_SC_PAGESIZE);
-	long pagemask = ~(pagesize - 1);
-#endif
 
         codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
         codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
@@ -312,7 +317,7 @@ void codegen_backend_init()
         host_x86_XOR32_REG_REG(block, REG_EDI, REG_EDI);
         host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
 #endif
-	host_x86_CALL(block, (uintptr_t)x86gpf);
+	host_x86_CALL(block, (void *)x86gpf);
         codegen_exit_rout = &codeblock[block_current].data[block_pos];
         host_x86_ADD64_REG_IMM(block, REG_RSP, 0x38);
         host_x86_POP(block, REG_R15);
@@ -358,6 +363,8 @@ void codegen_backend_prologue(codeblock_t *block)
                 host_x86_SUB32_REG_IMM(block, REG_EAX, block->TOP);
                 host_x86_MOV32_BASE_OFFSET_REG(block, REG_RSP, IREG_TOP_diff_stack_offset, REG_EAX);
         }
+        if (block->flags & CODEBLOCK_NO_IMMEDIATES)
+            host_x86_MOV64_REG_IMM(block, REG_R12, (uintptr_t)ram);
 }
 
 void codegen_backend_epilogue(codeblock_t *block)

src/codegen_backend_x86-64.h

@@ -10,3 +10,5 @@
 #define HASH(l) ((l) & 0x1ffff)
 
 #define BLOCK_MAX 0x3c0
+
+#define CODEGEN_BACKEND_HAS_MOV_IMM

src/codegen_backend_x86-64_defs.h

@@ -1,3 +1,5 @@
+/*RBP = cpu_state + 128
+  R12 = ram (if block->flags & CODEBLOCK_NO_IMMEDIATES)*/
 #define REG_AX 0
 #define REG_CX 1
 #define REG_DX 2
@@ -42,7 +44,7 @@
 #define REG_XMM6 6
 #define REG_XMM7 7
 
-#define REG_XMM_TEMP REG_XMM7
+#define REG_XMM_TEMP REG_XMM0
 
 #define CODEGEN_HOST_REGS 3
 #define CODEGEN_HOST_FP_REGS 7

src/codegen_backend_x86-64_ops.c

@@ -499,7 +499,7 @@ void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a,
 
 void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
 
         if (offset >= -128 && offset < 127)
         {
@@ -517,9 +517,29 @@ void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
                 codegen_addbyte(block, imm_data);
         }
 }
+void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
+{
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+
+        if (offset >= -128 && offset < 127)
+        {
+                codegen_alloc_bytes(block, 6);
+                codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[RBP], imm_data*/
+                codegen_addword(block, imm_data);
+        }
+        else
+        {
+                if ((uintptr_t)p >> 32)
+                        fatal("host_x86_MOV32_ABS_IMM - out of range %p\n", p);
+                codegen_alloc_bytes(block, 10);
+                codegen_addbyte4(block, 0x66, 0xc7, 0x04, 0x25); /*MOV p, imm_data*/
+                codegen_addlong(block, (uint32_t)(uintptr_t)p);
+                codegen_addword(block, imm_data);
+        }
+}
 void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
 
         if (offset >= -128 && offset < 127)
         {
@@ -540,7 +560,7 @@ void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
 
 void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
 
         if (src_reg & 8)
                 fatal("host_x86_MOV8_ABS_REG - bad reg\n");
@@ -614,7 +634,7 @@ void host_x86_MOV32_ABS_REG(codeblock_t *block, void *p, int src_reg)
 }
 void host_x86_MOV64_ABS_REG(codeblock_t *block, void *p, int src_reg)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
 
         if (src_reg & 8)
                 fatal("host_x86_MOV64_ABS_REG - bad reg\n");
@@ -675,7 +695,8 @@ void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int index_r
 
 void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
         
         if (dst_reg & 8)
                 fatal("host_x86_MOV8_REG_ABS reg & 8\n");
@@ -691,6 +712,12 @@ void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
                 codegen_addbyte2(block, 0x8a, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
                 codegen_addlong(block, offset);
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                codegen_alloc_bytes(block, 8);
+                codegen_addbyte4(block, 0x41, 0x8a, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOV dst_reg, ram_offset[R12]*/
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 fatal("host_x86_MOV8_REG_ABS - out of range\n");
@@ -698,7 +725,8 @@ void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 }
 void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
 
         if (dst_reg & 8)
                 fatal("host_x86_MOV16_REG_ABS reg & 8\n");
@@ -714,14 +742,27 @@ void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p)
                 codegen_addbyte3(block, 0x66, 0x8b, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
                 codegen_addlong(block, offset);
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                codegen_alloc_bytes(block, 9);
+                codegen_addbyte4(block, 0x66, 0x41, 0x8b, 0x84 | ((dst_reg & 7) << 3)); /*MOV dst_reg, ram_offset[R12]*/
+                codegen_addbyte(block, 0x24);
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 fatal("host_x86_MOV16_REG_ABS - out of range\n");
+                codegen_alloc_bytes(block, 10);
+		codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, p*/
+		codegen_addquad(block, (uintptr_t)p);
+                codegen_alloc_bytes(block, 1);
+                codegen_addbyte4(block, 0x66, 0x41, 0x8b, 0x01 | ((dst_reg & 7) << 3)); /*MOV dst_reg, [r9]*/
         }
 }
 void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
         
         if (dst_reg & 8)
                 fatal("host_x86_MOV32_REG_ABS reg & 8\n");
@@ -737,6 +778,12 @@ void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
                 codegen_addbyte2(block, 0x8b, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
                 codegen_addlong(block, offset);
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                codegen_alloc_bytes(block, 8);
+                codegen_addbyte4(block, 0x41, 0x8b, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOV dst_reg, ram_offset[R12]*/
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 fatal("host_x86_MOV32_REG_ABS - out of range\n");
@@ -748,7 +795,7 @@ void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 }
 void host_x86_MOV64_REG_ABS(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
 
         if (dst_reg & 8)
                 fatal("host_x86_MOV64_REG_ABS reg & 8\n");
@@ -914,6 +961,30 @@ void host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset
                 fatal("MOV64_BASE_OFFSET_REG - offset %i\n", offset);
 }
 
+void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
+{
+        if (base_reg & 8)
+                fatal("host_x86_MOV32_BASE_OFFSET_IMM reg & 8\n");
+
+        if (offset >= -128 && offset < 127)
+        {
+                if (base_reg == REG_RSP)
+                {
+                        codegen_alloc_bytes(block, 8);
+                        codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
+                        codegen_addlong(block, imm_data);
+                }
+                else
+                {
+                        codegen_alloc_bytes(block, 7);
+                        codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
+                        codegen_addlong(block, imm_data);
+                }
+        }
+        else
+                fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
+}
+
 void host_x86_MOV8_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data)
 {
         if (reg >= 8)
@@ -987,7 +1058,7 @@ void host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_d
                 codegen_addbyte3(block, 0xc7, 0x04, 0x24); /*MOV [ESP], imm_data*/
                 codegen_addlong(block, imm_data);
         }
-        else if (offset >= -80 || offset < 0x80)
+        else if (offset >= -0x80 && offset < 0x80)
         {
                 codegen_alloc_bytes(block, 8);
                 codegen_addbyte4(block, 0xc7, 0x44, 0x24, offset & 0xff); /*MOV offset[ESP], imm_data*/
@@ -1062,7 +1133,8 @@ void host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg)
 
 void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
         
         if (dst_reg & 8)
                 fatal("host_x86_MOVZX_REG_ABS_16_8 - bad reg\n");
@@ -1073,6 +1145,13 @@ void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
                 codegen_addbyte(block, 0x66);
                 codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                codegen_alloc_bytes(block, 10);
+                codegen_addbyte2(block, 0x66, 0x41);
+                codegen_addbyte4(block, 0x0f, 0xb6, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 codegen_alloc_bytes(block, 10);
@@ -1085,7 +1164,8 @@ void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
 }
 void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
         
 //        if (dst_reg & 8)
 //                fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
@@ -1104,6 +1184,16 @@ void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
                         codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
                 }
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                if (dst_reg & 8)
+                        fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
+
+                codegen_alloc_bytes(block, 9);
+                codegen_addbyte(block, 0x41);
+                codegen_addbyte4(block, 0x0f, 0xb6, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 if (dst_reg & 8)
@@ -1118,7 +1208,8 @@ void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
 }
 void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
 {
-        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+        int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
         
         if (dst_reg & 8)
                 fatal("host_x86_MOVZX_REG_ABS_32_16 - bad reg\n");
@@ -1128,6 +1219,13 @@ void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
                 codegen_alloc_bytes(block, 4);
                 codegen_addbyte4(block, 0x0f, 0xb7, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
         }
+        else if ((ram_offset < (1ull << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES))
+        {
+                codegen_alloc_bytes(block, 9);
+                codegen_addbyte(block, 0x41);
+                codegen_addbyte4(block, 0x0f, 0xb7, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
+                codegen_addlong(block, ram_offset);
+        }
         else
         {
                 codegen_alloc_bytes(block, 10);

src/codegen_backend_x86-64_ops.h

@@ -56,6 +56,7 @@ void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int sr
 void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
 
 void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
+void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
 void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
 
 void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
@@ -72,6 +73,8 @@ void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int dst_reg, int base_reg
 void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
 void host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
 
+void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
+
 void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
 void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
 void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);

src/codegen_backend_x86-64_uops.c

@@ -195,9 +195,9 @@ static int codegen_CALL_FUNC(codeblock_t *block, uop_t *uop)
 static int codegen_CALL_FUNC_RESULT(codeblock_t *block, uop_t *uop)
 {
         int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
-        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
 
 #ifdef RECOMPILER_DEBUG
+        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
         if (!REG_IS_L(dest_size))
                 fatal("CALL_FUNC_RESULT %02x\n", uop->dest_reg_a_real);
 #endif
@@ -826,8 +826,8 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
         host_x86_CALL(block, x86_int);
         host_x86_JMP(block, codegen_exit_rout);
         *branch_offset = (uint32_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 4;
-        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[0], 0);
+        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[0], 0x01010101);
-        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0);
+        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0x01010101);
         host_x86_MOV32_ABS_IMM(block, &cpu_state.TOP, 0);
         host_x86_MOV8_ABS_IMM(block, &cpu_state.ismmx, 1);
 
@@ -918,9 +918,9 @@ static int codegen_LOAD_FUNC_ARG3_IMM(codeblock_t *block, uop_t *uop)
 static int codegen_LOAD_SEG(codeblock_t *block, uop_t *uop)
 {
         int src_reg = HOST_REG_GET(uop->src_reg_a_real);
-        int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
 
 #ifdef RECOMPILER_DEBUG
+        int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
         if (!REG_IS_W(src_size))
                 fatal("LOAD_SEG %02x %p\n", uop->src_reg_a_real, uop->p);
 #endif
@@ -1029,9 +1029,9 @@ static int codegen_MEM_LOAD_REG(codeblock_t *block, uop_t *uop)
 static int codegen_MEM_LOAD_SINGLE(codeblock_t *block, uop_t *uop)
 {
         int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), seg_reg = HOST_REG_GET(uop->src_reg_a_real), addr_reg = HOST_REG_GET(uop->src_reg_b_real);
-        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
 
 #ifdef RECOMPILER_DEBUG
+        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
         if (!REG_IS_D(dest_size))
                 fatal("MEM_LOAD_SINGLE - %02x\n", uop->dest_reg_a_real);
 #endif
@@ -1048,9 +1048,9 @@ static int codegen_MEM_LOAD_SINGLE(codeblock_t *block, uop_t *uop)
 static int codegen_MEM_LOAD_DOUBLE(codeblock_t *block, uop_t *uop)
 {
         int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), seg_reg = HOST_REG_GET(uop->src_reg_a_real), addr_reg = HOST_REG_GET(uop->src_reg_b_real);
-        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
 
 #ifdef RECOMPILER_DEBUG
+        int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
         if (!REG_IS_D(dest_size))
                 fatal("MEM_LOAD_DOUBLE - %02x\n", uop->dest_reg_a_real);
 #endif
@@ -1174,9 +1174,9 @@ static int codegen_MEM_STORE_REG(codeblock_t *block, uop_t *uop)
 static int codegen_MEM_STORE_SINGLE(codeblock_t *block, uop_t *uop)
 {
         int seg_reg = HOST_REG_GET(uop->src_reg_a_real), addr_reg = HOST_REG_GET(uop->src_reg_b_real), src_reg = HOST_REG_GET(uop->src_reg_c_real);
-        int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
 
 #ifdef RECOMPILER_DEBUG
+        int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
         if (!REG_IS_D(src_size))
                 fatal("MEM_STORE_SINGLE - %02x\n", uop->src_reg_b_real);
 #endif
@@ -1193,9 +1193,9 @@ static int codegen_MEM_STORE_SINGLE(codeblock_t *block, uop_t *uop)
 static int codegen_MEM_STORE_DOUBLE(codeblock_t *block, uop_t *uop)
 {
         int seg_reg = HOST_REG_GET(uop->src_reg_a_real), addr_reg = HOST_REG_GET(uop->src_reg_b_real), src_reg = HOST_REG_GET(uop->src_reg_c_real);
-        int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
 
 #ifdef RECOMPILER_DEBUG
+        int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
         if (!REG_IS_D(src_size))
                 fatal("MEM_STORE_DOUBLE - %02x\n", uop->src_reg_b_real);
 #endif
@@ -1495,7 +1495,7 @@ static int codegen_OR(codeblock_t *block, uop_t *uop)
 }
 static int codegen_OR_IMM(codeblock_t *block, uop_t *uop)
 {
-        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
+        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
         int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
 
         if (REG_IS_L(dest_size) && REG_IS_L(src_size))
@@ -2766,7 +2766,7 @@ static int codegen_TEST_JS_DEST(codeblock_t *block, uop_t *uop)
 
 static int codegen_XOR(codeblock_t *block, uop_t *uop)
 {
-        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg_a = HOST_REG_GET(uop->src_reg_a_real), src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
+        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
         int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size_a = IREG_GET_SIZE(uop->src_reg_a_real), src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
 
         if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real)
@@ -2793,7 +2793,7 @@ static int codegen_XOR(codeblock_t *block, uop_t *uop)
 }
 static int codegen_XOR_IMM(codeblock_t *block, uop_t *uop)
 {
-        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
+        int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
         int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
 
         if (REG_IS_L(dest_size) && REG_IS_L(src_size))
@@ -3141,4 +3141,21 @@ void codegen_set_jump_dest(codeblock_t *block, void *p)
         *(uint32_t *)p = (uintptr_t)&block_write_data[block_pos] - ((uintptr_t)p + 4);
 }
 
+void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data)
+{
+        host_x86_MOV8_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data)
+{
+        host_x86_MOV16_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data)
+{
+        host_x86_MOV32_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data)
+{
+        host_x86_MOV32_BASE_OFFSET_IMM(block, REG_ESP, stack_offset, imm_data);
+}
+
 #endif

src/codegen_backend_x86.c

@@ -36,21 +36,24 @@ void *codegen_mem_store_double;
 void *codegen_gpf_rout;
 void *codegen_exit_rout;
 
-int codegen_host_reg_list[CODEGEN_HOST_REGS] =
+host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
 {
-        REG_EAX,
+        /*Note: while EAX and EDX are normally volatile registers under x86
-        REG_EBX,
+          calling conventions, the recompiler will explicitly save and restore
-        REG_EDX
+          them across funcion calls*/
+        {REG_EAX, 0},
+        {REG_EBX, 0},
+        {REG_EDX, 0}
 };
 
-int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
+host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
 {
-        REG_XMM0,
+        {REG_XMM0, HOST_REG_FLAG_VOLATILE},
-        REG_XMM1,
+        {REG_XMM1, HOST_REG_FLAG_VOLATILE},
-        REG_XMM2,
+        {REG_XMM2, HOST_REG_FLAG_VOLATILE},
-        REG_XMM3,
+        {REG_XMM3, HOST_REG_FLAG_VOLATILE},
-        REG_XMM4,
+        {REG_XMM4, HOST_REG_FLAG_VOLATILE},
-        REG_XMM5
+        {REG_XMM5, HOST_REG_FLAG_VOLATILE}
 };
 
 static void build_load_routine(codeblock_t *block, int size, int is_float)

src/codegen_backend_x86.h

@@ -10,3 +10,5 @@
 #define HASH(l) ((l) & 0x1ffff)
 
 #define BLOCK_MAX 0x3c0
+
+#define CODEGEN_BACKEND_HAS_MOV_IMM

src/codegen_backend_x86_ops.c

@@ -445,6 +445,24 @@ void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
                 codegen_addbyte(block, imm_data);
         }
 }
+void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
+{
+        int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
+
+        if (offset >= -128 && offset < 127)
+        {
+                codegen_alloc_bytes(block, 6);
+                codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[EBP], imm_data*/
+                codegen_addword(block, imm_data);
+        }
+        else
+        {
+                codegen_alloc_bytes(block, 9);
+                codegen_addbyte3(block, 0x66, 0xc7, 0x05); /*MOV p, imm_data*/
+                codegen_addlong(block, (uint32_t)p);
+                codegen_addword(block, imm_data);
+        }
+}
 void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
 {
         int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
@@ -701,6 +719,27 @@ void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset
                 fatal("MOV32_BASE_OFFSET_REG - offset %i\n", offset);
 }
 
+void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
+{
+        if (offset >= -128 && offset < 127)
+        {
+                if (base_reg == REG_ESP)
+                {
+                        codegen_alloc_bytes(block, 8);
+                        codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
+                        codegen_addlong(block, imm_data);
+                }
+                else
+                {
+                        codegen_alloc_bytes(block, 7);
+                        codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
+                        codegen_addlong(block, imm_data);
+                }
+        }
+        else
+                fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
+}
+
 void host_x86_MOV8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
 {
         codegen_alloc_bytes(block, 2);
@@ -759,7 +798,7 @@ void host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_d
                 codegen_addbyte3(block, 0xc7, 0x04, 0x24); /*MOV [ESP], imm_data*/
                 codegen_addlong(block, imm_data);
         }
-        else if (offset >= -80 || offset < 0x80)
+        else if (offset >= -0x80 && offset < 0x80)
         {
                 codegen_alloc_bytes(block, 8);
                 codegen_addbyte4(block, 0xc7, 0x44, 0x24, offset & 0xff); /*MOV offset[ESP], imm_data*/

src/codegen_backend_x86_ops.h

@@ -60,6 +60,7 @@ void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int sr
 void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
 
 void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
+void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
 void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
 
 void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
@@ -75,6 +76,8 @@ void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg
 void host_x86_MOV16_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
 void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
 
+void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
+
 void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
 void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
 void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);

src/codegen_backend_x86_ops_sse.c

@@ -200,7 +200,7 @@ void host_x86_MOVQ_STACK_OFFSET_XREG(codeblock_t *block, int offset, int src_reg
                 codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x04 | (src_reg << 3)); /*MOVQ [ESP], src_reg*/
                 codegen_addbyte(block, 0x24);
         }
-        else if (offset >= -80 || offset < 0x80)
+        else if (offset >= -0x80 && offset < 0x80)
         {
                 codegen_alloc_bytes(block, 6);
                 codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x44 | (src_reg << 3)); /*MOVQ offset[ESP], src_reg*/
@@ -429,6 +429,13 @@ void host_x86_PMULLW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
         codegen_addbyte4(block, 0x66, 0x0f, 0xd5, 0xc0 | src_reg | (dst_reg << 3)); /*PMULLW dst_reg, src_reg*/
 }
 
+void host_x86_PSHUFD_XREG_XREG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint8_t shuffle)
+{
+        codegen_alloc_bytes(block, 5);
+        codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | src_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0xee (move top 64-bits to low 64-bits)*/
+        codegen_addbyte(block, shuffle);
+}
+
 void host_x86_PSLLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
 {
         codegen_alloc_bytes(block, 5);
@@ -520,27 +527,6 @@ void host_x86_PSUBUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
         codegen_addbyte4(block, 0x66, 0x0f, 0xd9, 0xc0 | src_reg | (dst_reg << 3)); /*PSUBUSW dst_reg, src_reg*/
 }
 
-void host_x86_PUNPCKHBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
-{
-        codegen_alloc_bytes(block, 9);
-        codegen_addbyte4(block, 0x66, 0x0f, 0x60, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLBW dst_reg, src_reg*/
-        codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0xee (move top 64-bits to low 64-bits)*/
-        codegen_addbyte(block, 0xee);
-}
-void host_x86_PUNPCKHWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
-{
-        codegen_alloc_bytes(block, 9);
-        codegen_addbyte4(block, 0x66, 0x0f, 0x61, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLWD dst_reg, src_reg*/
-        codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0xee (move top 64-bits to low 64-bits)*/
-        codegen_addbyte(block, 0xee);
-}
-void host_x86_PUNPCKHDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
-{
-        codegen_alloc_bytes(block, 9);
-        codegen_addbyte4(block, 0x66, 0x0f, 0x62, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLDQ dst_reg, src_reg*/
-        codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0xee (move top 64-bits to low 64-bits)*/
-        codegen_addbyte(block, 0xee);
-}
 void host_x86_PUNPCKLBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
 {
         codegen_alloc_bytes(block, 4);

src/codegen_backend_x86_ops_sse.h

@@ -88,6 +88,8 @@ void host_x86_PSRLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
 void host_x86_PSRLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
 void host_x86_PSRLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
 
+void host_x86_PSHUFD_XREG_XREG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint8_t shuffle);
+
 void host_x86_PSUBB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PSUBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PSUBD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
@@ -96,9 +98,6 @@ void host_x86_PSUBSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PSUBUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PSUBUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 
-void host_x86_PUNPCKHBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
-void host_x86_PUNPCKHWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
-void host_x86_PUNPCKHDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PUNPCKLBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PUNPCKLWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
 void host_x86_PUNPCKLDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);

src/codegen_backend_x86_uops.c

@@ -827,8 +827,8 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
         host_x86_CALL(block, x86_int);
         host_x86_JMP(block, codegen_exit_rout);
         *branch_offset = (uint32_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 4;
-        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[0], 0);
+        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[0], 0x01010101);
-        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0);
+        host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0x01010101);
         host_x86_MOV32_ABS_IMM(block, &cpu_state.TOP, 0);
         host_x86_MOV8_ABS_IMM(block, &cpu_state.ismmx, 1);
         
@@ -2250,7 +2250,8 @@ static int codegen_PUNPCKHBW(codeblock_t *block, uop_t *uop)
 
         if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real)
         {
-                host_x86_PUNPCKHBW_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PUNPCKLBW_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PSHUFD_XREG_XREG_IMM(block, dest_reg, dest_reg, 0xee); /*0xee = move top 64-bits to low 64-bits*/
         }
 #ifdef RECOMPILER_DEBUG
         else
@@ -2265,7 +2266,8 @@ static int codegen_PUNPCKHWD(codeblock_t *block, uop_t *uop)
 
         if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real)
         {
-                host_x86_PUNPCKHWD_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PUNPCKLWD_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PSHUFD_XREG_XREG_IMM(block, dest_reg, dest_reg, 0xee); /*0xee = move top 64-bits to low 64-bits*/
         }
 #ifdef RECOMPILER_DEBUG
         else
@@ -2280,7 +2282,8 @@ static int codegen_PUNPCKHDQ(codeblock_t *block, uop_t *uop)
 
         if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real)
         {
-                host_x86_PUNPCKHDQ_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PUNPCKLDQ_XREG_XREG(block, dest_reg, src_reg_b);
+                host_x86_PSHUFD_XREG_XREG_IMM(block, dest_reg, dest_reg, 0xee); /*0xee = move top 64-bits to low 64-bits*/
         }
 #ifdef RECOMPILER_DEBUG
         else
@@ -2641,6 +2644,11 @@ static int codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
         host_x86_MOV8_ABS_IMM(block, uop->p, uop->imm_data);
         return 0;
 }
+static int codegen_STORE_PTR_IMM_16(codeblock_t *block, uop_t *uop)
+{
+        host_x86_MOV16_ABS_IMM(block, uop->p, uop->imm_data);
+        return 0;
+}
 
 static int codegen_SUB(codeblock_t *block, uop_t *uop)
 {
@@ -2836,6 +2844,7 @@ const uOpFn uop_handlers[UOP_MAX] =
 
         [UOP_STORE_P_IMM & UOP_MASK] = codegen_STORE_PTR_IMM,
         [UOP_STORE_P_IMM_8 & UOP_MASK] = codegen_STORE_PTR_IMM_8,
+        [UOP_STORE_P_IMM_16 & UOP_MASK] = codegen_STORE_PTR_IMM_16,
         
         [UOP_MEM_LOAD_ABS & UOP_MASK]    = codegen_MEM_LOAD_ABS,
         [UOP_MEM_LOAD_REG & UOP_MASK]    = codegen_MEM_LOAD_REG,
@@ -3136,4 +3145,21 @@ void codegen_set_jump_dest(codeblock_t *block, void *p)
         *(uint32_t *)p = (uintptr_t)&block_write_data[block_pos] - ((uintptr_t)p + 4);
 }
 
+void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data)
+{
+        host_x86_MOV8_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data)
+{
+        host_x86_MOV16_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data)
+{
+        host_x86_MOV32_ABS_IMM(block, p, imm_data);
+}
+void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data)
+{
+        host_x86_MOV32_BASE_OFFSET_IMM(block, REG_ESP, stack_offset, imm_data);
+}
+
 #endif

src/codegen_block.c

@@ -69,8 +69,10 @@ static int dirty_list_size = 0;
 
 static void block_free_list_add(codeblock_t *block)
 {
+#ifndef RELEASE_BUILD
         if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
                 fatal("block_free_list_add: block=%p in dirty list\n", block);
+#endif
         if (block_free_list)
                 block->next = block_free_list;
         else
@@ -82,8 +84,10 @@ static void block_free_list_add(codeblock_t *block)
 
 static void block_dirty_list_add(codeblock_t *block)
 {
+#ifndef RELEASE_BUILD
         if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
                 fatal("block_dirty_list_add: block=%p already in dirty list\n", block);
+#endif
 //        pclog("block_dirty_list_add: block=%i size=%i %i head=%i tail=%i\n", get_block_nr(block), dirty_list_size, dirty_list_check_size(), block_dirty_list_head, block_dirty_list_tail);
         if (block_dirty_list_head != BLOCK_INVALID)
         {
@@ -108,12 +112,14 @@ static void block_dirty_list_add(codeblock_t *block)
                 /*Evict oldest block to the free list*/
                 codeblock_t *evict_block = &codeblock[block_dirty_list_tail];
 
+#ifndef RELEASE_BUILD
                 if (!(evict_block->flags & CODEBLOCK_IN_DIRTY_LIST))
                         fatal("block_dirty_list_add: evict_block=%p %x %x not in dirty list\n", evict_block, evict_block->phys, evict_block->flags);
                 if (!block_dirty_list_tail)
                         fatal("block_dirty_list_add - !block_dirty_list_tail\n");
                 if (evict_block->prev == BLOCK_INVALID)
                         fatal("block_dirty_list_add - evict_block->prev == BLOCK_INVALID\n");
+#endif
 
                 block_dirty_list_tail = evict_block->prev;
                 codeblock[evict_block->prev].next = BLOCK_INVALID;
@@ -132,8 +138,10 @@ static void block_dirty_list_remove(codeblock_t *block)
         codeblock_t *prev_block = &codeblock[block->prev];
         codeblock_t *next_block = &codeblock[block->next];
 
+#ifndef RELEASE_BUILD
         if (!(block->flags & CODEBLOCK_IN_DIRTY_LIST))
                 fatal("block_dirty_list_remove: block=%p not in dirty list\n", block);
+#endif
 
         /*Is block head of list*/
         if (block->prev == BLOCK_INVALID)
@@ -148,8 +156,10 @@ static void block_dirty_list_remove(codeblock_t *block)
                 next_block->prev = block->prev;
 
         dirty_list_size--;
+#ifndef RELEASE_BUILD
         if (dirty_list_size < 0)
                 fatal("remove - dirty_list_size < 0!\n");
+#endif
         block->flags &= ~CODEBLOCK_IN_DIRTY_LIST;
 //        pclog("  block_dirty_list_remove: %p flags = %x\n", block, block->flags);
 }
@@ -180,9 +190,10 @@ static codeblock_t *block_free_list_get()
                 /*Free list is empty, check the dirty list*/
                 if (block_dirty_list_tail)
                 {
+#ifndef RELEASE_BUILD
                         if (dirty_list_size <= 0)
                                 fatal("get - dirty_list_size <= 0!\n");
-
+#endif
                         /*Reuse oldest block*/
                         block = &codeblock[block_dirty_list_tail];
 
@@ -310,9 +321,10 @@ static void add_to_block_list(codeblock_t *block)
         uint16_t block_nr = get_block_nr(block);
 //pclog("Add to block list %p %08x %llx %x\n", block, block->phys, block->page_mask2, block->flags);
 
+#ifndef RELEASE_BUILD
         if (!block->page_mask)
                 fatal("add_to_block_list - mask = 0 %llx %llx\n", block->page_mask,block->page_mask2);
-
+#endif
         if (block_prev_nr)
         {
                 block->next = block_prev_nr;
@@ -327,8 +339,10 @@ static void add_to_block_list(codeblock_t *block)
 
         if (block->next)
         {
+#ifndef RELEASE_BUILD
                 if (codeblock[block->next].pc == BLOCK_PC_INVALID)
                         fatal("block->next->pc=BLOCK_PC_INVALID %p %p %x %x\n", (void *)&codeblock[block->next], (void *)codeblock, block_current, block_pos);
+#endif
         }
         
         if (block->page_mask2)
@@ -356,9 +370,10 @@ static void remove_from_block_list(codeblock_t *block, uint32_t pc)
 {
         if (!block->page_mask)
                 return;
+#ifndef RELEASE_BUILD
         if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
                 fatal("remove_from_block_list: in dirty list\n");
-
+#endif
         if (block->prev)
         {
                 codeblock[block->prev].next = block->next;
@@ -376,8 +391,10 @@ static void remove_from_block_list(codeblock_t *block, uint32_t pc)
 
         if (!(block->flags & CODEBLOCK_HAS_PAGE2))
         {
+#ifndef RELEASE_BUILD
                 if (block->prev_2 || block->next_2)
                         fatal("Invalid block_2 %x %p %08x\n", block->flags, block, block->phys);
+#endif
                 return;
         }
         block->flags &= ~CODEBLOCK_HAS_PAGE2;
@@ -404,11 +421,12 @@ static void invalidate_block(codeblock_t *block)
 {
         uint32_t old_pc = block->pc;
 
+#ifndef RELEASE_BUILD
         if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
                 fatal("invalidate_block: already in dirty list\n");
         if (block->pc == BLOCK_PC_INVALID)
                 fatal("Invalidating deleted block\n");
-                
+#endif
         remove_from_block_list(block, old_pc);
         block_dirty_list_add(block);
         if (block->head_mem_block)
@@ -423,8 +441,10 @@ static void delete_block(codeblock_t *block)
         if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
                 codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
 
+#ifndef RELEASE_BUILD
         if (block->pc == BLOCK_PC_INVALID)
                 fatal("Deleting deleted block\n");
+#endif
         block->pc = BLOCK_PC_INVALID;
 
         codeblock_tree_delete(block);
@@ -443,8 +463,10 @@ static void delete_dirty_block(codeblock_t *block)
         if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
                 codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
 
+#ifndef RELEASE_BUILD
         if (block->pc == BLOCK_PC_INVALID)
                 fatal("Deleting deleted block\n");
+#endif
         block->pc = BLOCK_PC_INVALID;
 
         codeblock_tree_delete(block);
@@ -494,8 +516,10 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
                         invalidate_block(block);
                         cpu_recomp_evicted++;
                 }
+#ifndef RELEASE_BUILD
                 if (block_nr == next_block)
                         fatal("Broken 1\n");
+#endif
                 block_nr = next_block;
         }
 
@@ -512,8 +536,10 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
                         invalidate_block(block);
                         cpu_recomp_evicted++;
                 }
+#ifndef RELEASE_BUILD
                 if (block_nr == next_block)
                         fatal("Broken 2\n");
+#endif
                 block_nr = next_block;
         }
         
@@ -541,8 +567,10 @@ void codegen_block_init(uint32_t phys_addr)
         if (!page->block)
                 mem_flush_write_page(phys_addr, cs+cpu_state.pc);
         block = block_free_list_get();
+#ifndef RELEASE_BUILD
         if (!block)
                 fatal("codegen_block_init: block_free_list_get() returned NULL\n");
+#endif
         block_current = get_block_nr(block);
 
         block_num = HASH(phys_addr);
@@ -582,10 +610,10 @@ void codegen_block_start_recompile(codeblock_t *block)
 
         block_num = HASH(block->phys);
         block_current = get_block_nr(block);//block->pnt;
-
+#ifndef RELEASE_BUILD
         if (block->pc != cs + cpu_state.pc || (block->flags & CODEBLOCK_WAS_RECOMPILED))
                 fatal("Recompile to used block!\n");
-
+#endif
         block->head_mem_block = codegen_allocator_allocate(NULL, block_current);
         block->data = codeblock_allocator_get_ptr(block->head_mem_block);
 
@@ -695,6 +723,7 @@ void codegen_block_generate_end_mask_recompile()
                         if (!pages[block->phys_2 >> 12].block_2)
                                 mem_flush_write_page(block->phys_2, codegen_endpc);
 
+#ifndef RELEASE_BUILD
                         if (!block->page_mask2)
                                 fatal("!page_mask2\n");
                         if (block->next_2)
@@ -703,6 +732,7 @@ void codegen_block_generate_end_mask_recompile()
                                 if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
                                         fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *)&codeblock[block->next_2]);
                         }
+#endif
                 }
                 else
                 {
@@ -724,9 +754,10 @@ void codegen_block_generate_end_mask_mark()
         uint32_t end_pc;
         page_t *p;
 
+#ifndef RELEASE_BUILD
         if (block->flags & CODEBLOCK_BYTE_MASK)
                 fatal("codegen_block_generate_end_mask2() - BYTE_MASK\n");
-
+#endif
         block->page_mask = 0;
         start_pc = (block->pc & 0xfff) & ~63;
         if ((block->pc ^ codegen_endpc) & ~0xfff)
@@ -771,7 +802,7 @@ void codegen_block_generate_end_mask_mark()
 
                         if (!pages[block->phys_2 >> 12].block_2)
                                 mem_flush_write_page(block->phys_2, codegen_endpc);
-
+#ifndef RELEASE_BUILD
                         if (!block->page_mask2)
                                 fatal("!page_mask2\n");
                         if (block->next_2)
@@ -780,7 +811,7 @@ void codegen_block_generate_end_mask_mark()
                                 if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
                                         fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *)&codeblock[block->next_2]);
                         }
-
+#endif
                         block->dirty_mask2 = &page_2->dirty_mask;
                 }
                 else

src/codegen_ir.c

@@ -107,37 +107,61 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
                 if ((uop->type & UOP_MASK) == UOP_INVALID)
                         continue;
 
-                if (uop->type & UOP_TYPE_PARAMS_REGS)
+#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
+                if ((uop->type & UOP_MASK) == (UOP_MOV_IMM & UOP_MASK) && reg_is_native_size(uop->dest_reg_a) && !codegen_reg_is_loaded(uop->dest_reg_a) && reg_version[IREG_GET_REG(uop->dest_reg_a.reg)][uop->dest_reg_a.version].refcount <= 0)
                 {
-                        codegen_reg_alloc_register(uop->dest_reg_a, uop->src_reg_a, uop->src_reg_b, uop->src_reg_c);
+                        /*Special case for UOP_MOV_IMM - if destination not already in host register
-                        if (uop->src_reg_a.reg != IREG_INVALID)
+                          and won't be used again then just store directly to memory*/
-                        {
+                        codegen_reg_write_imm(block, uop->dest_reg_a, uop->imm_data);
-                                uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
-                        }
-                        if (uop->src_reg_b.reg != IREG_INVALID)
-                        {
-                                uop->src_reg_b_real = codegen_reg_alloc_read_reg(block, uop->src_reg_b, NULL);
-                        }
-                        if (uop->src_reg_c.reg != IREG_INVALID)
-                        {
-                                uop->src_reg_c_real = codegen_reg_alloc_read_reg(block, uop->src_reg_c, NULL);
-                        }
                 }
-                
+                else
-                if (uop->type & UOP_TYPE_ORDER_BARRIER)
+#endif
-                        codegen_reg_flush(ir, block);
+                if ((uop->type & UOP_MASK) == (UOP_MOV & UOP_MASK) && reg_version[IREG_GET_REG(uop->src_reg_a.reg)][uop->src_reg_a.version].refcount <= 1  &&
-
+                                reg_is_native_size(uop->src_reg_a) && reg_is_native_size(uop->dest_reg_a))
-                if (uop->type & UOP_TYPE_PARAMS_REGS)
                 {
-                        if (uop->dest_reg_a.reg != IREG_INVALID)
+                        /*Special case for UOP_MOV - if source register won't be used again then
-                        {
+                          just rename it to dest register instead of moving*/
-                                uop->dest_reg_a_real = codegen_reg_alloc_write_reg(block, uop->dest_reg_a);
+                        codegen_reg_alloc_register(invalid_ir_reg, uop->src_reg_a, invalid_ir_reg, invalid_ir_reg);
-                        }
+                        uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
+                        codegen_reg_rename(block, uop->src_reg_a, uop->dest_reg_a);
+                        if (uop->type & UOP_TYPE_ORDER_BARRIER)
+                                codegen_reg_flush(ir, block);
                 }
+                else
+                {
+                        if (uop->type & UOP_TYPE_PARAMS_REGS)
+                        {
+                                codegen_reg_alloc_register(uop->dest_reg_a, uop->src_reg_a, uop->src_reg_b, uop->src_reg_c);
+                                if (uop->src_reg_a.reg != IREG_INVALID)
+                                {
+                                        uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
+                                }
+                                if (uop->src_reg_b.reg != IREG_INVALID)
+                                {
+                                        uop->src_reg_b_real = codegen_reg_alloc_read_reg(block, uop->src_reg_b, NULL);
+                                }
+                                if (uop->src_reg_c.reg != IREG_INVALID)
+                                {
+                                        uop->src_reg_c_real = codegen_reg_alloc_read_reg(block, uop->src_reg_c, NULL);
+                                }
+                        }
 
-                if (!uop_handlers[uop->type & UOP_MASK])
+                        if (uop->type & UOP_TYPE_ORDER_BARRIER)
-                        fatal("!uop_handlers[uop->type & UOP_MASK] %08x\n", uop->type);
+                                codegen_reg_flush(ir, block);
-                uop_handlers[uop->type & UOP_MASK](block, uop);
+
+                        if (uop->type & UOP_TYPE_PARAMS_REGS)
+                        {
+                                if (uop->dest_reg_a.reg != IREG_INVALID)
+                                {
+                                        uop->dest_reg_a_real = codegen_reg_alloc_write_reg(block, uop->dest_reg_a);
+                                }
+                        }
+#ifndef RELEASE_BUILD
+                        if (!uop_handlers[uop->type & UOP_MASK])
+                                fatal("!uop_handlers[uop->type & UOP_MASK] %08x\n", uop->type);
+#endif
+                        uop_handlers[uop->type & UOP_MASK](block, uop);
+                }
 
                 if (uop->type & UOP_TYPE_JUMP)
                 {

src/codegen_ir_defs.h

@@ -55,6 +55,7 @@
 /*UOP_JMP_DEST - jump to ptr*/
 #define UOP_JMP_DEST              (UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x17 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
 #define UOP_NOP_BARRIER           (UOP_TYPE_BARRIER | 0x18)
+#define UOP_STORE_P_IMM_16        (UOP_TYPE_PARAMS_IMM     | 0x19)
 
 #ifdef DEBUG_EXTRA
 /*UOP_LOG_INSTR - log non-recompiled instruction in imm_data*/
@@ -765,6 +766,7 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
 
 #define uop_STORE_PTR_IMM(ir, p, imm)    uop_gen_pointer_imm(UOP_STORE_P_IMM, ir, p, imm)
 #define uop_STORE_PTR_IMM_8(ir, p, imm)  uop_gen_pointer_imm(UOP_STORE_P_IMM_8, ir, p, imm)
+#define uop_STORE_PTR_IMM_16(ir, p, imm)  uop_gen_pointer_imm(UOP_STORE_P_IMM_16, ir, p, imm)
 
 #define uop_TEST_JNS_DEST(ir, src_reg) uop_gen_reg_src1(UOP_TEST_JNS_DEST, ir, src_reg)
 #define uop_TEST_JS_DEST(ir, src_reg)  uop_gen_reg_src1(UOP_TEST_JS_DEST, ir, src_reg)
@@ -807,4 +809,9 @@ void codegen_direct_write_double_stack(codeblock_t *block, int stack_offset, int
 
 void codegen_set_jump_dest(codeblock_t *block, void *p);
 
+void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data);
+void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data);
+void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data);
+void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data);
+
 #endif

src/codegen_ops_arith.c

@@ -1953,12 +1953,12 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
                         break;
                         
                         case 0x10: /*ADC*/
-                        get_cf(ir, IREG_temp2);
+                        get_cf(ir, IREG_temp3);
                         if (block->flags & CODEBLOCK_NO_IMMEDIATES)
                                 uop_ADD(ir, IREG_temp1, IREG_temp0, IREG_temp2);
                         else
                                 uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
-                        uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp2);
+                        uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp3);
                         uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
                         uop_MOV(ir, IREG_flags_op1, IREG_temp0);
                         if (block->flags & CODEBLOCK_NO_IMMEDIATES)
@@ -1970,12 +1970,12 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
                         break;
 
                         case 0x18: /*SBB*/
-                        get_cf(ir, IREG_temp2);
+                        get_cf(ir, IREG_temp3);
                         if (block->flags & CODEBLOCK_NO_IMMEDIATES)
                                 uop_SUB(ir, IREG_temp1, IREG_temp0, IREG_temp2);
                         else
                                 uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
-                        uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp2);
+                        uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp3);
                         uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
                         uop_MOV(ir, IREG_flags_op1, IREG_temp0);
                         if (block->flags & CODEBLOCK_NO_IMMEDIATES)

src/codegen_ops_fpu_arith.c

@@ -274,6 +274,8 @@ uint32_t ropFADD ## name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint
 {                                                                                                                               \
         x86seg *target_seg;                                                                                                     \
                                                                                                                                 \
+        if ((cpu_state.npxc >> 10) & 3)                                                                                         \
+                return 0;                                                                                                       \
         uop_FP_ENTER(ir);                                                                                                       \
         uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);                                                                           \
         op_pc--;                                                                                                                \

src/codegen_ops_helpers.c

@@ -34,9 +34,10 @@ int codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, uint32_t next_pc,
         int start;
         int max_unroll;
         int first_instruction;
+        int TOP = -1;
 
         /*Check that dest instruction was actually compiled into block*/
-        start = codegen_get_instruction_uop(block, dest_addr, &first_instruction);
+        start = codegen_get_instruction_uop(block, dest_addr, &first_instruction, &TOP);
 
         /*Couldn't find any uOPs corresponding to the destination instruction*/
         if (start == -1)
@@ -48,9 +49,15 @@ int codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, uint32_t next_pc,
                         return 0;
                 }
                 else
+                {
                         start = ir->wr_pos;
+                        TOP = cpu_state.TOP;
+                }
         }
         
+        if (TOP != cpu_state.TOP)
+                return 0;
+
         max_unroll = UNROLL_MAX_UOPS / ((ir->wr_pos-start)+6);
         if (max_unroll > (UNROLL_MAX_REG_REFERENCES / max_version_refcount))
                 max_unroll = (UNROLL_MAX_REG_REFERENCES / max_version_refcount);

src/codegen_ops_misc.c

@@ -356,11 +356,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
                 return -1;
                 
                 case 0x28: /*JMP far*/
+                uop_MOVZX(ir, IREG_pc, src_reg);
                 uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);
                 uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
-                uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
+                uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
                 uop_CALL_FUNC(ir, loadcsjmp);
-                uop_MOVZX(ir, IREG_pc, src_reg);
                 return -1;
 
                 case 0x30: /*PUSH*/
@@ -463,11 +463,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
                 return -1;
 
                 case 0x28: /*JMP far*/
+                uop_MOV(ir, IREG_pc, src_reg);
                 uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4);
                 uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
-                uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
+                uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
                 uop_CALL_FUNC(ir, loadcsjmp);
-                uop_MOV(ir, IREG_pc, src_reg);
                 return -1;
 
                 case 0x30: /*PUSH*/

src/codegen_ops_mmx_loadstore.c

@@ -38,6 +38,9 @@ uint32_t ropMOVD_d_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
 {
         int src_reg = (fetchdat >> 3) & 7;
 
+        if (cpu_iscyrix && (cpu_cur_status & CPU_STATUS_SMM))
+                return 0;
+
         uop_MMX_ENTER(ir);
         codegen_mark_code_present(block, cs+op_pc, 1);
         if ((fetchdat & 0xc0) == 0xc0)

src/codegen_reg.c

@@ -22,7 +22,7 @@ typedef struct host_reg_set_t
 {
         ir_reg_t *regs;
         uint8_t *dirty;
-        int *reg_list;
+        host_reg_def_t *reg_list;
         uint16_t locked;
         int nr_regs;
 } host_reg_set_t;
@@ -191,7 +191,7 @@ void codegen_reg_mark_as_required()
         }
 }
 
-static int reg_is_native_size(ir_reg_t ir_reg)
+int reg_is_native_size(ir_reg_t ir_reg)
 {
         int native_size = ireg_data[IREG_GET_REG(ir_reg.reg)].native_size;
         int requested_size = IREG_GET_SIZE(ir_reg.reg);
@@ -271,75 +271,91 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
         switch (ireg_data[IREG_GET_REG(ir_reg.reg)].native_size)
         {
                 case REG_WORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
                         fatal("codegen_reg_load - REG_WORD !REG_INTEGER\n");
+#endif
                 if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
-                        codegen_direct_read_16_stack(block, reg_set->reg_list[c], (int)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_16_stack(block, reg_set->reg_list[c].reg, (intptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 else
-                        codegen_direct_read_16(block, reg_set->reg_list[c], ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_16(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 break;
 
                 case REG_DWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
                         fatal("codegen_reg_load - REG_DWORD !REG_INTEGER\n");
+#endif
                 if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
-                        codegen_direct_read_32_stack(block, reg_set->reg_list[c], (int)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_32_stack(block, reg_set->reg_list[c].reg, (intptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 else
-                        codegen_direct_read_32(block, reg_set->reg_list[c], ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_32(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 break;
 
                 case REG_QWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
                         fatal("codegen_reg_load - REG_QWORD !REG_FP\n");
+#endif
                 if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
-                        codegen_direct_read_64_stack(block, reg_set->reg_list[c], (int)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_64_stack(block, reg_set->reg_list[c].reg, (intptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 else
-                        codegen_direct_read_64(block, reg_set->reg_list[c], ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_64(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 break;
                 
                 case REG_POINTER:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
                         fatal("codegen_reg_load - REG_POINTER !REG_INTEGER\n");
+#endif
                 if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
-                        codegen_direct_read_pointer_stack(block, reg_set->reg_list[c], (int)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_pointer_stack(block, reg_set->reg_list[c].reg, (intptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 else
-                        codegen_direct_read_pointer(block, reg_set->reg_list[c], ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_pointer(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 break;
 
                 case REG_DOUBLE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
                         fatal("codegen_reg_load - REG_DOUBLE !REG_FP\n");
+#endif
                 if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
-                        codegen_direct_read_double_stack(block, reg_set->reg_list[c], (int)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_double_stack(block, reg_set->reg_list[c].reg, (intptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 else
-                        codegen_direct_read_double(block, reg_set->reg_list[c], ireg_data[IREG_GET_REG(ir_reg.reg)].p);
+                        codegen_direct_read_double(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
                 break;
                 
                 case REG_FPU_ST_BYTE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
                         fatal("codegen_reg_load - REG_FPU_ST_BYTE !REG_INTEGER\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_read_8(block, reg_set->reg_list[c], &cpu_state.tag[ir_reg.reg & 7]);
+                        codegen_direct_read_8(block, reg_set->reg_list[c].reg, &cpu_state.tag[ir_reg.reg & 7]);
                 else
-                        codegen_direct_read_st_8(block, reg_set->reg_list[c], &cpu_state.tag[0], ir_reg.reg & 7);
+                        codegen_direct_read_st_8(block, reg_set->reg_list[c].reg, &cpu_state.tag[0], ir_reg.reg & 7);
                 break;
 
                 case REG_FPU_ST_QWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
                         fatal("codegen_reg_load - REG_FPU_ST_QWORD !REG_FP\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_read_64(block, reg_set->reg_list[c], &cpu_state.MM[ir_reg.reg & 7]);
+                        codegen_direct_read_64(block, reg_set->reg_list[c].reg, &cpu_state.MM[ir_reg.reg & 7]);
                 else
-                        codegen_direct_read_st_64(block, reg_set->reg_list[c], &cpu_state.MM[0], ir_reg.reg & 7);
+                        codegen_direct_read_st_64(block, reg_set->reg_list[c].reg, &cpu_state.MM[0], ir_reg.reg & 7);
                 break;
 
                 case REG_FPU_ST_DOUBLE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
                         fatal("codegen_reg_load - REG_FPU_ST_DOUBLE !REG_FP\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_read_double(block, reg_set->reg_list[c], &cpu_state.ST[ir_reg.reg & 7]);
+                        codegen_direct_read_double(block, reg_set->reg_list[c].reg, &cpu_state.ST[ir_reg.reg & 7]);
                 else
-                        codegen_direct_read_st_double(block, reg_set->reg_list[c], &cpu_state.ST[0], ir_reg.reg & 7);
+                        codegen_direct_read_st_double(block, reg_set->reg_list[c].reg, &cpu_state.ST[0], ir_reg.reg & 7);
                 break;
 
                 default:
@@ -363,81 +379,99 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
         switch (ireg_data[ir_reg].native_size)
         {
                 case REG_BYTE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_INTEGER)
                         fatal("codegen_reg_writeback - REG_BYTE !REG_INTEGER\n");
                 if ((uintptr_t)p < 256)
                         fatal("codegen_reg_writeback - REG_BYTE %p\n", p);
-                codegen_direct_write_8(block, p, reg_set->reg_list[c]);
+#endif
+                codegen_direct_write_8(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_WORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_INTEGER)
                         fatal("codegen_reg_writeback - REG_WORD !REG_INTEGER\n");
                 if ((uintptr_t)p < 256)
                         fatal("codegen_reg_writeback - REG_WORD %p\n", p);
-                codegen_direct_write_16(block, p, reg_set->reg_list[c]);
+#endif
+                codegen_direct_write_16(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_DWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_INTEGER)
                         fatal("codegen_reg_writeback - REG_DWORD !REG_INTEGER\n");
+#endif
                 if ((uintptr_t)p < 256)
-                        codegen_direct_write_32_stack(block, (int)p, reg_set->reg_list[c]);
+                        codegen_direct_write_32_stack(block, (intptr_t)p, reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_32(block, p, reg_set->reg_list[c]);
+                        codegen_direct_write_32(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_QWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_FP)
                         fatal("codegen_reg_writeback - REG_QWORD !REG_FP\n");
+#endif
                 if ((uintptr_t)p < 256)
-                        codegen_direct_write_64_stack(block, (int)p, reg_set->reg_list[c]);
+                        codegen_direct_write_64_stack(block, (intptr_t)p, reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_64(block, p, reg_set->reg_list[c]);
+                        codegen_direct_write_64(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_POINTER:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_INTEGER)
                         fatal("codegen_reg_writeback - REG_POINTER !REG_INTEGER\n");
                 if ((uintptr_t)p < 256)
                         fatal("codegen_reg_writeback - REG_POINTER %p\n", p);
-                codegen_direct_write_ptr(block, p, reg_set->reg_list[c]);
+#endif
+                codegen_direct_write_ptr(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_DOUBLE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_FP)
                         fatal("codegen_reg_writeback - REG_DOUBLE !REG_FP\n");
+#endif
                 if ((uintptr_t)p < 256)
-                        codegen_direct_write_double_stack(block, (int)p, reg_set->reg_list[c]);
+                        codegen_direct_write_double_stack(block, (intptr_t)p, reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_double(block, p, reg_set->reg_list[c]);
+                        codegen_direct_write_double(block, p, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_FPU_ST_BYTE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_INTEGER)
                         fatal("codegen_reg_writeback - REG_FPU_ST_BYTE !REG_INTEGER\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_write_8(block, &cpu_state.tag[reg_set->regs[c].reg & 7], reg_set->reg_list[c]);
+                        codegen_direct_write_8(block, &cpu_state.tag[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_st_8(block, &cpu_state.tag[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c]);
+                        codegen_direct_write_st_8(block, &cpu_state.tag[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_FPU_ST_QWORD:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_FP)
                         fatal("codegen_reg_writeback - REG_FPU_ST_QWORD !REG_FP\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_write_64(block, &cpu_state.MM[reg_set->regs[c].reg & 7], reg_set->reg_list[c]);
+                        codegen_direct_write_64(block, &cpu_state.MM[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_st_64(block, &cpu_state.MM[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c]);
+                        codegen_direct_write_st_64(block, &cpu_state.MM[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c].reg);
                 break;
 
                 case REG_FPU_ST_DOUBLE:
+#ifndef RELEASE_BUILD
                 if (ireg_data[ir_reg].type != REG_FP)
                         fatal("codegen_reg_writeback - REG_FPU_ST_DOUBLE !REG_FP\n");
+#endif
                 if (block->flags & CODEBLOCK_STATIC_TOP)
-                        codegen_direct_write_double(block, &cpu_state.ST[reg_set->regs[c].reg & 7], reg_set->reg_list[c]);
+                        codegen_direct_write_double(block, &cpu_state.ST[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
                 else
-                        codegen_direct_write_st_double(block, &cpu_state.ST[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c]);
+                        codegen_direct_write_st_double(block, &cpu_state.ST[0], reg_set->regs[c].reg & 7, reg_set->reg_list[c].reg);
                 break;
 
                 default:
@@ -449,6 +483,49 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
         reg_set->dirty[c] = 0;
 }
 
+#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
+void codegen_reg_write_imm(codeblock_t *block, ir_reg_t ir_reg, uint32_t imm_data)
+{
+        int reg_idx = IREG_GET_REG(ir_reg.reg);
+        void *p = ireg_data[reg_idx].p;
+
+        switch (ireg_data[reg_idx].native_size)
+        {
+                case REG_BYTE:
+#ifndef RELEASE_BUILD
+                if ((uintptr_t)p < 256)
+                        fatal("codegen_reg_write_imm - REG_BYTE %p\n", p);
+#endif
+                codegen_direct_write_8_imm(block, p, imm_data);
+                break;
+
+                case REG_WORD:
+#ifndef RELEASE_BUILD
+                if ((uintptr_t)p < 256)
+                        fatal("codegen_reg_write_imm - REG_WORD %p\n", p);
+#endif
+                codegen_direct_write_16_imm(block, p, imm_data);
+                break;
+
+                case REG_DWORD:
+                if ((uintptr_t)p < 256)
+                        codegen_direct_write_32_imm_stack(block, (int)p, imm_data);
+                else
+                        codegen_direct_write_32_imm(block, p, imm_data);
+                break;
+                
+                case REG_POINTER:
+                case REG_QWORD:
+                case REG_DOUBLE:
+                case REG_FPU_ST_BYTE:
+                case REG_FPU_ST_QWORD:
+                case REG_FPU_ST_DOUBLE:
+                default:
+                fatal("codegen_reg_write_imm - native_size=%i\n", ireg_data[reg_idx].native_size);
+        }
+}
+#endif
+
 static void alloc_reg(ir_reg_t ir_reg)
 {
         host_reg_set_t *reg_set = get_reg_set(ir_reg);
@@ -459,8 +536,10 @@ static void alloc_reg(ir_reg_t ir_reg)
         {
                 if (IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg))
                 {
+#ifndef RELEASE_BUILD
                         if (reg_set->regs[c].version != ir_reg.version)
                                 fatal("alloc_reg - host_regs[c].version != ir_reg.version  %i %p %p  %i %i\n", c, reg_set, &host_reg_set, reg_set->regs[c].reg, ir_reg.reg);
+#endif
                         reg_set->locked |= (1 << c);
                         return;
                 }
@@ -552,9 +631,10 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
                         reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount++;
                         break;
                 }
-
+#ifndef RELEASE_BUILD
                 if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg) && reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount)
                         fatal("codegen_reg_alloc_read_reg - version mismatch!\n");
+#endif
         }
 
         if (c == reg_set->nr_regs)
@@ -573,8 +653,10 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
                                 if (!(reg_set->locked & (1 << c)))
                                         break;
                         }
+#ifndef RELEASE_BUILD
                         if (c == reg_set->nr_regs)
                                 fatal("codegen_reg_alloc_read_reg - out of registers\n");
+#endif
                 }
                 if (reg_set->dirty[c])
                         codegen_reg_writeback(reg_set, block, c, 1);
@@ -589,13 +671,15 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
 //                pclog("   already loaded %i\n", c);
 
         reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount--;
+#ifndef RELEASE_BUILD
         if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount == (uint8_t)-1)
                 fatal("codegen_reg_alloc_read_reg - refcount < 0\n");
+#endif
 
         if (host_reg_idx)
                 *host_reg_idx = c;
 //        pclog(" codegen_reg_alloc_read_reg: %i.%i %i  %02x.%i  %i\n", ir_reg.reg, ir_reg.version, codegen_host_reg_list[c],  reg_set->regs[c].reg,reg_set->regs[c].version,  c);
-        return reg_set->reg_list[c] | IREG_GET_SIZE(ir_reg.reg);
+        return reg_set->reg_list[c].reg | IREG_GET_SIZE(ir_reg.reg);
 }
 
 ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
@@ -614,16 +698,18 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
                 
                 codegen_reg_alloc_read_reg(block, parent_reg, &c);
 
+#ifndef RELEASE_BUILD
                 if (IREG_GET_REG(reg_set->regs[c].reg) != IREG_GET_REG(ir_reg.reg) || reg_set->regs[c].version > ir_reg.version-1)
                         fatal("codegen_reg_alloc_write_reg sub_reg - doesn't match  %i %02x.%i %02x.%i\n", c,
                                         reg_set->regs[c].reg,reg_set->regs[c].version,
                                         ir_reg.reg,ir_reg.version);
+#endif
 
                 reg_set->regs[c].reg = ir_reg.reg;
                 reg_set->regs[c].version = ir_reg.version;
                 reg_set->dirty[c] = 1;
 //        pclog(" codegen_reg_alloc_write_reg: partial %i.%i %i\n", ir_reg.reg, ir_reg.version, codegen_host_reg_list[c]);
-                return reg_set->reg_list[c] | IREG_GET_SIZE(ir_reg.reg);
+                return reg_set->reg_list[c].reg | IREG_GET_SIZE(ir_reg.reg);
         }
         
         /*Search for previous version in host register*/
@@ -633,8 +719,10 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
                 {
                         if (reg_set->regs[c].version <= ir_reg.version-1)
                         {
+#ifndef RELEASE_BUILD
                                 if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount != 0)
                                         fatal("codegen_reg_alloc_write_reg - previous version refcount != 0\n");
+#endif
                                 break;
                         }
                 }
@@ -657,8 +745,10 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
                                 if (!(reg_set->locked & (1 << c)))
                                         break;
                         }
+#ifndef RELEASE_BUILD
                         if (c == reg_set->nr_regs)
                                 fatal("codegen_reg_alloc_write_reg - out of registers\n");
+#endif
                         if (reg_set->dirty[c])
                                 codegen_reg_writeback(reg_set, block, c, 1);
                 }
@@ -668,7 +758,69 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
         reg_set->regs[c].version = ir_reg.version;
         reg_set->dirty[c] = 1;
 //        pclog(" codegen_reg_alloc_write_reg: %i.%i %i\n", ir_reg.reg, ir_reg.version, codegen_host_reg_list[c]);
-        return reg_set->reg_list[c] | IREG_GET_SIZE(ir_reg.reg);
+        return reg_set->reg_list[c].reg | IREG_GET_SIZE(ir_reg.reg);
+}
+
+#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
+int codegen_reg_is_loaded(ir_reg_t ir_reg)
+{
+        host_reg_set_t *reg_set = get_reg_set(ir_reg);
+        int c;
+        
+        /*Search for previous version in host register*/
+        for (c = 0; c < reg_set->nr_regs; c++)
+        {
+                if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg))
+                {
+                        if (reg_set->regs[c].version <= ir_reg.version-1)
+                        {
+#ifndef RELEASE_BUILD
+                                if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount != 0)
+                                        fatal("codegen_reg_alloc_write_reg - previous version refcount != 0\n");
+#endif
+                                return 1;
+                        }
+                }
+        }
+        return 0;
+}
+#endif
+
+void codegen_reg_rename(codeblock_t *block, ir_reg_t src, ir_reg_t dst)
+{
+        host_reg_set_t *reg_set = get_reg_set(src);
+        int c;
+        int target;
+
+//        pclog("rename: %i.%i -> %i.%i\n", src.reg,src.version, dst.reg, dst.version);
+        /*Search for required register*/
+        for (c = 0; c < reg_set->nr_regs; c++)
+        {
+                if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(src.reg) && reg_set->regs[c].version == src.version)
+                        break;
+        }
+#ifndef RELEASE_BUILD
+        if (c == reg_set->nr_regs)
+                fatal("codegen_reg_rename: Can't find register to rename\n");
+#endif
+        target = c;
+        if (reg_set->dirty[target])
+                codegen_reg_writeback(reg_set, block, target, 0);
+        reg_set->regs[target] = dst;
+        reg_set->dirty[target] = 1;
+//        pclog("renamed reg %i dest=%i.%i\n", target, dst.reg, dst.version);
+
+        /*Invalidate any stale copies of the dest register*/
+        for (c = 0; c < reg_set->nr_regs; c++)
+        {
+                if (c == target)
+                        continue;
+                if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(dst.reg))
+                {
+                        reg_set->regs[c] = invalid_ir_reg;
+                        reg_set->dirty[c] = 0;
+                }
+        }
 }
 
 void codegen_reg_flush(ir_data_t *ir, codeblock_t *block)
@@ -683,6 +835,11 @@ void codegen_reg_flush(ir_data_t *ir, codeblock_t *block)
                 {
                         codegen_reg_writeback(reg_set, block, c, 0);
                 }
+                if (reg_set->reg_list[c].flags & HOST_REG_FLAG_VOLATILE)
+                {
+                        reg_set->regs[c] = invalid_ir_reg;
+                        reg_set->dirty[c] = 0;
+                }
         }
 
         reg_set = &host_fp_reg_set;
@@ -692,6 +849,11 @@ void codegen_reg_flush(ir_data_t *ir, codeblock_t *block)
                 {
                         codegen_reg_writeback(reg_set, block, c, 0);
                 }
+                if (reg_set->reg_list[c].flags & HOST_REG_FLAG_VOLATILE)
+                {
+                        reg_set->regs[c] = invalid_ir_reg;
+                        reg_set->dirty[c] = 0;
+                }
         }
 }
 

src/codegen_reg.h

@@ -325,17 +325,21 @@ static inline ir_reg_t codegen_reg_read(int reg)
         ir_reg_t ireg;
         reg_version_t *version;
         
+#ifndef RELEASE_BUILD
         if (IREG_GET_REG(reg) == IREG_INVALID)
                 fatal("codegen_reg_read - IREG_INVALID\n");
-        
+#endif
         ireg.reg = reg;
         ireg.version = reg_last_version[IREG_GET_REG(reg)];
         version = &reg_version[IREG_GET_REG(ireg.reg)][ireg.version];
         version->flags = 0;
         version->refcount++;
+#ifndef RELEASE_BUILD
         if (!version->refcount)
                 fatal("codegen_reg_read - refcount overflow\n");
-        else if (version->refcount > REG_REFCOUNT_MAX)
+        else
+#endif
+        if (version->refcount > REG_REFCOUNT_MAX)
                 CPU_BLOCK_END();
         if (version->refcount > max_version_refcount)
                 max_version_refcount = version->refcount;
@@ -343,26 +347,35 @@ static inline ir_reg_t codegen_reg_read(int reg)
         return ireg;
 }
 
+int reg_is_native_size(ir_reg_t ir_reg);
+
 static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
 {
         ir_reg_t ireg;
         int last_version = reg_last_version[IREG_GET_REG(reg)];
         reg_version_t *version;
         
+#ifndef RELEASE_BUILD
         if (IREG_GET_REG(reg) == IREG_INVALID)
                 fatal("codegen_reg_write - IREG_INVALID\n");
-
+#endif
         ireg.reg = reg;
         ireg.version = last_version + 1;
         
         if (IREG_GET_REG(reg) > IREG_EBX && last_version && !reg_version[IREG_GET_REG(reg)][last_version].refcount &&
                         !(reg_version[IREG_GET_REG(reg)][last_version].flags & REG_FLAGS_REQUIRED))
-                add_to_dead_list(&reg_version[IREG_GET_REG(reg)][last_version], IREG_GET_REG(reg), last_version);
+        {
+                if (reg_is_native_size(ireg)) /*Non-native size registers have an implicit dependency on the previous version, so don't add to dead list*/
+                        add_to_dead_list(&reg_version[IREG_GET_REG(reg)][last_version], IREG_GET_REG(reg), last_version);
+        }
         
         reg_last_version[IREG_GET_REG(reg)]++;
+#ifndef RELEASE_BUILD
         if (!reg_last_version[IREG_GET_REG(reg)])
                 fatal("codegen_reg_write - version overflow\n");
-        else if (reg_last_version[IREG_GET_REG(reg)] > REG_VERSION_MAX)
+        else
+#endif
+        if (reg_last_version[IREG_GET_REG(reg)] > REG_VERSION_MAX)
                 CPU_BLOCK_END();
         if (reg_last_version[IREG_GET_REG(reg)] > max_version_refcount)
                 max_version_refcount = reg_last_version[IREG_GET_REG(reg)];
@@ -391,9 +404,16 @@ void codegen_reg_flush_invalidate(struct ir_data_t *ir, codeblock_t *block);
 /*Register ir_reg usage for this uOP. This ensures that required registers aren't evicted*/
 void codegen_reg_alloc_register(ir_reg_t dest_reg_a, ir_reg_t src_reg_a, ir_reg_t src_reg_b, ir_reg_t src_reg_c);
 
+#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
+int codegen_reg_is_loaded(ir_reg_t ir_reg);
+void codegen_reg_write_imm(codeblock_t *block, ir_reg_t ir_reg, uint32_t imm_data);
+#endif
+
 ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, int *host_reg_idx);
 ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg);
 
+void codegen_reg_rename(codeblock_t *block, ir_reg_t src, ir_reg_t dst);
+
 void codegen_reg_mark_as_required();
 void codegen_reg_process_dead_list(struct ir_data_t *ir);
 #endif

src/codegen_timing_common.c

@@ -3,41 +3,41 @@
 
 uint64_t opcode_deps[256] =
 {
-/*      ADD                      ADD                      ADD                              ADD*/
+/*      ADD                                     ADD                                     ADD                              ADD*/
-/*00*/  SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,      SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+/*00*/  SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      ADD                      ADD                      PUSH ES                          POP ES*/
+/*      ADD                                     ADD                                     PUSH ES                          POP ES*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP,                        IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  IMPL_ESP,                        IMPL_ESP,
-/*      OR                       OR                       OR                               OR*/
+/*      OR                                      OR                                      OR                               OR*/
-        SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,      SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+        SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      OR                       OR                       PUSH CS*/
+/*      OR                                      OR                                      PUSH CS*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP,                        0,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  IMPL_ESP,                        0,
 
-/*      ADC                      ADC                      ADC                              ADC*/
+/*      ADC                                     ADC                                     ADC                              ADC*/
-/*10*/  SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,      SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+/*10*/  SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      ADC                      ADC                      PUSH SS                          POP SS*/
+/*      ADC                                     ADC                                     PUSH SS                          POP SS*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP,                        IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  IMPL_ESP,                        IMPL_ESP,
-/*      SBB                      SBB                      SBB                              SBB*/        
+/*      SBB                                     SBB                                     SBB                              SBB*/
-        SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,      SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+        SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      SBB                      SBB                      PUSH DS                          POP DS*/
+/*      SBB                                     SBB                                     PUSH DS                          POP DS*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP,                        IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  IMPL_ESP,                        IMPL_ESP,
 
-/*      AND                      AND                              AND                              AND*/
+/*      AND                                     AND                                     AND                              AND*/
-/*20*/  SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,              SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+/*20*/  SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      AND                      AND                                                               DAA*/
+/*      AND                                     AND                                                                      DAA*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0,                               SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  0,                               SRCDEP_EAX | DSTDEP_EAX,
-/*      SUB                      SUB                              SUB                              SUB*/
+/*      SUB                                     SUB                                     SUB                              SUB*/
-        SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,              SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+        SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      SUB                      SUB                                                               DAS*/
+/*      SUB                                     SUB                                                                      DAS*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0,                               SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  0,                               SRCDEP_EAX | DSTDEP_EAX,
         
-/*      XOR                      XOR                              XOR                              XOR*/
+/*      XOR                                     XOR                                     XOR                              XOR*/
-/*30*/  SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,              SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
+/*30*/  SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
-/*      XOR                      XOR                                                               AAA*/
+/*      XOR                                     XOR                                                                      AAA*/
-        SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0,                               SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,     SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,  0,                               SRCDEP_EAX | DSTDEP_EAX,
-/*      CMP                      CMP                              CMP                              CMP*/
+/*      CMP                                     CMP                                     CMP                              CMP*/
-        SRCDEP_REG | MODRM,      SRCDEP_REG | MODRM,              SRCDEP_REG | MODRM,              SRCDEP_REG | MODRM,
+        SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,                     SRCDEP_REG | MODRM,              SRCDEP_REG | MODRM,
-/*      CMP                      CMP                                                               AAS*/
+/*      CMP                                     CMP                                                                      AAS*/
-        SRCDEP_EAX,              SRCDEP_EAX,                      0,                               SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | HAS_IMM8,                  SRCDEP_EAX | HAS_IMM1632,               0,                               SRCDEP_EAX | DSTDEP_EAX,
 
 /*      INC EAX                  INC ECX                  INC EDX                  INC EBX*/
 /*40*/  SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
@@ -61,7 +61,7 @@ uint64_t opcode_deps[256] =
 /*60*/  IMPL_ESP,              IMPL_ESP,                0,                       0,
         0,                     0,                       0,                       0,
 /*      PUSH imm               IMUL                     PUSH imm                 IMUL*/
-        IMPL_ESP,              DSTDEP_REG | MODRM,      IMPL_ESP,                DSTDEP_REG | MODRM,
+        IMPL_ESP | HAS_IMM1632,DSTDEP_REG | MODRM,      IMPL_ESP | HAS_IMM8,     DSTDEP_REG | MODRM,
 /*      INSB                   INSW                     OUTSB                    OUTSW*/
         0,                     0,                       0,                       0,
         
@@ -95,15 +95,15 @@ uint64_t opcode_deps[256] =
         0,                       0,                       0,                       0,
 
 /*      MOV*/
-/*b0*/  DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+/*b0*/  DSTDEP_EAX | HAS_IMM8,    DSTDEP_ECX | HAS_IMM8,    DSTDEP_EDX | HAS_IMM8,    DSTDEP_EBX | HAS_IMM8,
-        DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+        DSTDEP_EAX | HAS_IMM8,    DSTDEP_ECX | HAS_IMM8,    DSTDEP_EDX | HAS_IMM8,    DSTDEP_EBX | HAS_IMM8,
-        DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+        DSTDEP_EAX | HAS_IMM1632, DSTDEP_ECX | HAS_IMM1632, DSTDEP_EDX | HAS_IMM1632, DSTDEP_EBX | HAS_IMM1632,
-        DSTDEP_ESP,              DSTDEP_EBP,              DSTDEP_ESI,              DSTDEP_EDI,
+        DSTDEP_ESP | HAS_IMM1632, DSTDEP_EBP | HAS_IMM1632, DSTDEP_ESI | HAS_IMM1632, DSTDEP_EDI | HAS_IMM1632,
 
 /*                                                      RET imm                   RET*/
 /*c0*/  0,                       0,                     SRCDEP_ESP | DSTDEP_ESP,  IMPL_ESP,
 /*      LES                      LDS                    MOV                       MOV*/
-        DSTDEP_REG | MODRM,      DSTDEP_REG | MODRM,    MODRM,                    MODRM,
+        DSTDEP_REG | MODRM,      DSTDEP_REG | MODRM,    MODRM | HAS_IMM8,         MODRM | HAS_IMM1632,
 /*      ENTER                    LEAVE                  RETF                      RETF*/
         IMPL_ESP,                IMPL_ESP,              IMPL_ESP,                 IMPL_ESP,
 /*      INT3                     INT                    INTO                      IRET*/
@@ -140,38 +140,38 @@ uint64_t opcode_deps_mod3[256] =
 /*      ADD                      ADD                 ADD                                          ADD*/
 /*00*/  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      ADD                                          ADD                                          PUSH ES                                      POP ES*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX,                     IMPL_ESP,                                    IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       IMPL_ESP,                                    IMPL_ESP,
 /*      OR                                           OR                                           OR                                           OR*/
         SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      OR                                           OR                                           PUSH CS*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX,                     IMPL_ESP,                                    0,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       IMPL_ESP,                                    0,
 
 /*      ADC                                          ADC                                          ADC                                          ADC*/
 /*10*/  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      ADC                                          ADC                                          PUSH SS                                      POP SS*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX,                     IMPL_ESP,                                    IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       IMPL_ESP,                                    IMPL_ESP,
 /*      SBB                                          SBB                                          SBB                                          SBB*/        
         SRCDEP_REG |SRCDEP_RM | DSTDEP_RM |  MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      SBB                                          SBB                                          PUSH DS                                      POP DS*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX,                     IMPL_ESP,                                    IMPL_ESP,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       IMPL_ESP,                                    IMPL_ESP,
 
 /*      AND                                          AND                                          AND                                          AND*/
 /*20*/  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      AND                                          AND                                                                                       DAA*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX | MODRM,             0,                                           SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       0,                                           SRCDEP_EAX | DSTDEP_EAX,
 /*      SUB                                          SUB                                          SUB                                          SUB*/
         SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      SUB                                          SUB                                                                                       DAS*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX | MODRM,             0,                                           SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       0,                                           SRCDEP_EAX | DSTDEP_EAX,
         
 /*      XOR                                          XOR                                          XOR                                          XOR*/
 /*30*/  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,  SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      XOR                                          XOR                                                                                       AAA*/
-        SRCDEP_EAX | DSTDEP_EAX,                     SRCDEP_EAX | DSTDEP_EAX | MODRM,             0,                                           SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8,          SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632,       0,                                           SRCDEP_EAX | DSTDEP_EAX,
 /*      CMP                                          CMP                                          CMP                                          CMP*/
         SRCDEP_REG | SRCDEP_RM | MODRM,              SRCDEP_REG | SRCDEP_RM | MODRM,              SRCDEP_REG | SRCDEP_RM | MODRM,              SRCDEP_REG | SRCDEP_RM | MODRM,
 /*      CMP                                          CMP                                                                                       AAS*/
-        SRCDEP_EAX,                                  SRCDEP_EAX,                                  0,                                           SRCDEP_EAX | DSTDEP_EAX,
+        SRCDEP_EAX | HAS_IMM8,                       SRCDEP_EAX | HAS_IMM1632,                    0,                                           SRCDEP_EAX | DSTDEP_EAX,
 
 /*      INC EAX                  INC ECX                  INC EDX                  INC EBX*/
 /*40*/  SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
@@ -195,7 +195,7 @@ uint64_t opcode_deps_mod3[256] =
 /*60*/  IMPL_ESP,              IMPL_ESP,                        0,                       0,
         0,                     0,                               0,                       0,
 /*      PUSH imm               IMUL                             PUSH imm                 IMUL*/
-        IMPL_ESP,              DSTDEP_REG | SRCDEP_RM | MODRM,  IMPL_ESP,                DSTDEP_REG | SRCDEP_RM | MODRM,
+        IMPL_ESP | HAS_IMM1632,DSTDEP_REG | SRCDEP_RM | MODRM,  IMPL_ESP | HAS_IMM8,     DSTDEP_REG | SRCDEP_RM | MODRM,
 /*      INSB                   INSW                             OUTSB                    OUTSW*/
         0,                     0,                               0,                       0,
         
@@ -229,19 +229,19 @@ uint64_t opcode_deps_mod3[256] =
         0,                       0,                       0,                       0,
 
 /*      MOV*/
-/*b0*/  DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+/*b0*/  DSTDEP_EAX | HAS_IMM8,    DSTDEP_ECX | HAS_IMM8,    DSTDEP_EDX | HAS_IMM8,    DSTDEP_EBX | HAS_IMM8,
-        DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+        DSTDEP_EAX | HAS_IMM8,    DSTDEP_ECX | HAS_IMM8,    DSTDEP_EDX | HAS_IMM8,    DSTDEP_EBX | HAS_IMM8,
-        DSTDEP_EAX,              DSTDEP_ECX,              DSTDEP_EDX,              DSTDEP_EBX,
+        DSTDEP_EAX | HAS_IMM1632, DSTDEP_ECX | HAS_IMM1632, DSTDEP_EDX | HAS_IMM1632, DSTDEP_EBX | HAS_IMM1632,
-        DSTDEP_ESP,              DSTDEP_EBP,              DSTDEP_ESI,              DSTDEP_EDI,
+        DSTDEP_ESP | HAS_IMM1632, DSTDEP_EBP | HAS_IMM1632, DSTDEP_ESI | HAS_IMM1632, DSTDEP_EDI | HAS_IMM1632,
 
-/*                                                      RET imm                   RET*/
+/*                                                      RET imm                         RET*/
-/*c0*/  0,                       0,                     SRCDEP_ESP | DSTDEP_ESP,  IMPL_ESP,
+/*c0*/  0,                       0,                     SRCDEP_ESP | DSTDEP_ESP,        IMPL_ESP,
-/*      LES                      LDS                    MOV                       MOV*/
+/*      LES                      LDS                    MOV                             MOV*/
-        DSTDEP_REG | MODRM,      DSTDEP_REG | MODRM,    DSTDEP_RM | MODRM,        DSTDEP_RM | MODRM,
+        DSTDEP_REG | MODRM,      DSTDEP_REG | MODRM,    DSTDEP_RM | MODRM | HAS_IMM8,   DSTDEP_RM | MODRM | HAS_IMM1632,
-/*      ENTER                    LEAVE                  RETF                      RETF*/
+/*      ENTER                    LEAVE                  RETF                            RETF*/
-        IMPL_ESP,                IMPL_ESP,              IMPL_ESP,                 IMPL_ESP,
+        IMPL_ESP,                IMPL_ESP,              IMPL_ESP,                       IMPL_ESP,
-/*      INT3                     INT                    INTO                      IRET*/
+/*      INT3                     INT                    INTO                            IRET*/
-        0,                       0,                     0,                        0,
+        0,                       0,                     0,                              0,
 
 
 /*d0*/  0,                       0,                       0,                      0,

src/codegen_timing_cyrixiii.c

@@ -0,0 +1,679 @@
+/*Since VIA didn't document cycle timings in the Cyrix III/C3 datasheets, and
+  I don't currently own either chip to test against, most of the timing here is
+  a guess. This code makes the current (probably wrong) assumptions, based on the
+  few details in the Cyrix III datasheet :
+  - Most common integer instructions are 1 cycle, including register-memory and
+    memory-register versions
+  - Basic FPU instructions are 2 cycles. The datasheet claims "a non-dependent
+    add or multiply can start every two clocks"; it's not clear if this is referring
+    to CPU or FPU clocks, since the FPU runs at 1/2 CPU speed on these chips.
+  - MMX instructions are 1 cycle
+  - No instruction pairing of any kind (unlike WinChip 2)
+  - Prefixes other than 0x0f cost 1 cycle each
+  - AGI stalls cost 1 cycle, except for implicit references to ESP*/
+#include "ibm.h"
+#include "cpu.h"
+#include "x86.h"
+#include "x86_ops.h"
+#include "x87.h"
+#include "mem.h"
+#include "codegen.h"
+#include "codegen_ops.h"
+#include "codegen_timing_common.h"
+
+/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
+#define CYCLES_HAS_MULTI (1 << 31)
+
+#define CYCLES_FPU (1 << 30)
+
+#define CYCLES_IS_MMX_MUL   (1 << 29)
+#define CYCLES_IS_MMX_SHIFT (1 << 28)
+#define CYCLES_IS_MMX_ANY   (1 << 27)
+#define CYCLES_IS_3DNOW     (1 << 26)
+
+#define CYCLES_MMX_MUL(c)   (CYCLES_IS_MMX_MUL   | c)
+#define CYCLES_MMX_SHIFT(c) (CYCLES_IS_MMX_SHIFT | c)
+#define CYCLES_MMX_ANY(c)   (CYCLES_IS_MMX_ANY   | c)
+#define CYCLES_3DNOW(c)     (CYCLES_IS_3DNOW     | c)
+
+#define CYCLES_IS_MMX (CYCLES_IS_MMX_MUL | CYCLES_IS_MMX_SHIFT | CYCLES_IS_MMX_ANY | CYCLES_IS_3DNOW)
+
+#define GET_CYCLES(c) (c & ~(CYCLES_HAS_MULTI | CYCLES_FPU | CYCLES_IS_MMX))
+
+#define CYCLES(c) c
+#define CYCLES2(c16, c32) (CYCLES_HAS_MULTI | c16 | (c32 << 8))
+
+/*comp_time = cycles until instruction complete
+  i_overlap = cycles that overlap with integer
+  f_overlap = cycles that overlap with subsequent FPU*/
+#define FPU_CYCLES(comp_time, i_overlap, f_overlap) (comp_time) | (i_overlap << 8) | (f_overlap << 16) | CYCLES_FPU
+
+#define FPU_COMP_TIME(timing) (timing & 0xff)
+#define FPU_I_OVERLAP(timing) ((timing >> 8) & 0xff)
+#define FPU_F_OVERLAP(timing) ((timing >> 16) & 0xff)
+
+#define FPU_I_LATENCY(timing) (FPU_COMP_TIME(timing) - FPU_I_OVERLAP(timing))
+
+#define FPU_F_LATENCY(timing) (FPU_I_OVERLAP(timing) - FPU_F_OVERLAP(timing))
+
+#define FPU_RESULT_LATENCY(timing) ((timing >> 8) & 0xff)
+
+#define INVALID 0
+
+static uint32_t opcode_timings[256] =
+{
+/*00*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      INVALID,
+/*10*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),
+/*20*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),
+/*30*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),
+
+/*40*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*50*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*60*/  CYCLES(11),     CYCLES(9),      CYCLES(7),      CYCLES(9),      CYCLES(4),      CYCLES(4),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES2(17,25), CYCLES(1),      CYCLES2(17,20), CYCLES(17),     CYCLES(17),     CYCLES(17),     CYCLES(17),
+/*70*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*80*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(2),      CYCLES(5),      CYCLES(5),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(1),      CYCLES(5),      CYCLES(6),
+/*90*/  CYCLES(1),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(0),      CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(2),      CYCLES(3),
+/*a0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(7),      CYCLES(7),      CYCLES(8),      CYCLES(8),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),
+/*b0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*c0*/  CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),      CYCLES(1),      CYCLES(1),      CYCLES(14),     CYCLES(5),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(3),      CYCLES(0),
+/*d0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(15),     CYCLES(14),     CYCLES(2),      CYCLES(4),      INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,
+/*e0*/  CYCLES(6),      CYCLES(6),      CYCLES(6),      CYCLES(5),      CYCLES(14),     CYCLES(14),     CYCLES(16),     CYCLES(16),     CYCLES(3),      CYCLES(3),      CYCLES(17),     CYCLES(3),      CYCLES(14),     CYCLES(14),     CYCLES(14),     CYCLES(14),
+/*f0*/  CYCLES(4),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(4),      CYCLES(2),      INVALID,        INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(3),      INVALID
+};
+
+static uint32_t opcode_timings_mod3[256] =
+{
+/*00*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      INVALID,
+/*10*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(3),
+/*20*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(3),
+/*30*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),
+
+/*40*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*50*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+/*60*/  CYCLES(11),     CYCLES(9),      CYCLES(7),      CYCLES(9),      CYCLES(4),      CYCLES(4),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES2(14,25), CYCLES(1),      CYCLES2(17,20), CYCLES(17),     CYCLES(17),     CYCLES(17),     CYCLES(17),
+/*70*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*80*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(2),      CYCLES(1),      CYCLES(2),      CYCLES(1),
+/*90*/  CYCLES(1),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(0),      CYCLES(4),      CYCLES(4),      CYCLES(5),      CYCLES(2),      CYCLES(3),
+/*a0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(7),      CYCLES(7),      CYCLES(8),      CYCLES(8),      CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),
+/*b0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),
+
+/*c0*/  CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(5),      CYCLES(6),      CYCLES(6),      CYCLES(1),      CYCLES(1),      CYCLES(14),     CYCLES(5),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(3),      CYCLES(0),
+/*d0*/  CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(1),      CYCLES(15),     CYCLES(14),     CYCLES(2),      CYCLES(4),      INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,        INVALID,
+/*e0*/  CYCLES(6),      CYCLES(6),      CYCLES(6),      CYCLES(5),      CYCLES(14),     CYCLES(14),     CYCLES(16),     CYCLES(16),     CYCLES(3),      CYCLES(3),      CYCLES(17),     CYCLES(3),      CYCLES(14),     CYCLES(14),     CYCLES(14),     CYCLES(14),
+/*f0*/  CYCLES(4),      CYCLES(0),      CYCLES(0),      CYCLES(0),      CYCLES(4),      CYCLES(2),      INVALID,        INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(3),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(3),      INVALID,
+};
+
+static uint32_t opcode_timings_0f[256] =
+{
+/*00*/  CYCLES(20),          CYCLES(11),          CYCLES(11),          CYCLES(10),          INVALID,           CYCLES(195),       CYCLES(7),         INVALID,             CYCLES(1000),        CYCLES(10000),       INVALID,             INVALID,             INVALID,           CYCLES_3DNOW(1),   CYCLES(1),         CYCLES_3DNOW(1),
+/*10*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*20*/  CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),         CYCLES(6),         INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*30*/  CYCLES(9),           CYCLES(1),           CYCLES(9),           INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+
+/*40*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*50*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*60*/  CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+/*70*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES(100),         INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+
+/*80*/  CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*90*/  CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),
+/*a0*/  CYCLES(3),           CYCLES(3),           CYCLES(14),          CYCLES(8),           CYCLES(3),         CYCLES(4),         INVALID,           INVALID,             CYCLES(3),           CYCLES(3),           INVALID,             CYCLES(13),          CYCLES(3),         CYCLES(3),         INVALID,           CYCLES2(18,30),
+/*b0*/  CYCLES(10),          CYCLES(10),          CYCLES(6),           CYCLES(13),          CYCLES(6),         CYCLES(6),         CYCLES(3),         CYCLES(3),           INVALID,             INVALID,             CYCLES(6),           CYCLES(13),          CYCLES(7),         CYCLES(7),         CYCLES(3),         CYCLES(3),
+
+/*c0*/  CYCLES(4),           CYCLES(4),           INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           CYCLES(3),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*d0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*e0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,             INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*f0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(2), INVALID,
+};
+static uint32_t opcode_timings_0f_mod3[256] =
+{
+/*00*/  CYCLES(20),          CYCLES(11),          CYCLES(11),          CYCLES(10),          INVALID,           CYCLES(195),       CYCLES(7),         INVALID,             CYCLES(1000),        CYCLES(10000),       INVALID,             INVALID,             INVALID,           CYCLES_3DNOW(1),   CYCLES(1),         CYCLES_3DNOW(1),
+/*10*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*20*/  CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),           CYCLES(6),         CYCLES(6),         INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*30*/  CYCLES(9),           CYCLES(1),           CYCLES(9),           INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+
+/*40*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*50*/  INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,             INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           INVALID,
+/*60*/  CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+/*70*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES(100),         INVALID,             INVALID,             INVALID,             INVALID,             INVALID,           INVALID,           CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
+
+/*80*/  CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*90*/  CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),           CYCLES(3),         CYCLES(3),         CYCLES(3),         CYCLES(3),
+/*a0*/  CYCLES(3),           CYCLES(3),           CYCLES(14),          CYCLES(8),           CYCLES(3),         CYCLES(4),         INVALID,           INVALID,             CYCLES(3),           CYCLES(3),           INVALID,             CYCLES(13),          CYCLES(3),         CYCLES(3),         INVALID,           CYCLES2(18,30),
+/*b0*/  CYCLES(10),          CYCLES(10),          CYCLES(6),           CYCLES(13),          CYCLES(6),         CYCLES(6),         CYCLES(3),         CYCLES(3),           INVALID,             INVALID,             CYCLES(6),           CYCLES(13),          CYCLES(7),         CYCLES(7),         CYCLES(3),         CYCLES(3),
+
+/*c0*/  CYCLES(4),           CYCLES(4),           INVALID,             INVALID,             INVALID,           INVALID,           INVALID,           CYCLES(3),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),           CYCLES(1),         CYCLES(1),         CYCLES(1),         CYCLES(1),
+/*d0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*e0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,             INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,           CYCLES_MMX_ANY(1),
+/*f0*/  INVALID,             CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID,           CYCLES_MMX_MUL(1), INVALID,           INVALID,             CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   CYCLES_MMX_ANY(1),   INVALID,             CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,
+};
+
+static uint32_t opcode_timings_shift[8] =
+{
+        CYCLES(7),      CYCLES(7),      CYCLES(10),     CYCLES(10),     CYCLES(7),      CYCLES(7),      CYCLES(7),      CYCLES(7)
+};
+static uint32_t opcode_timings_shift_mod3[8] =
+{
+        CYCLES(3),      CYCLES(3),      CYCLES(9),      CYCLES(9),      CYCLES(3),      CYCLES(3),      CYCLES(3),      CYCLES(3)
+};
+
+static uint32_t opcode_timings_f6[8] =
+{
+        CYCLES(2),      INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(13),     CYCLES(14),     CYCLES(16),     CYCLES(19)
+};
+static uint32_t opcode_timings_f6_mod3[8] =
+{
+        CYCLES(1),      INVALID,        CYCLES(1),      CYCLES(1),      CYCLES(13),     CYCLES(14),     CYCLES(16),     CYCLES(19)
+};
+static uint32_t opcode_timings_f7[8] =
+{
+        CYCLES(2),      INVALID,        CYCLES(2),      CYCLES(2),      CYCLES(21),     CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
+};
+static uint32_t opcode_timings_f7_mod3[8] =
+{
+        CYCLES(1),      INVALID,        CYCLES(1),      CYCLES(1),      CYCLES(21),     CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
+};
+static uint32_t opcode_timings_ff[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(5),      CYCLES(0),      CYCLES(5),      CYCLES(0),      CYCLES(5),      INVALID
+};
+static uint32_t opcode_timings_ff_mod3[8] =
+{
+        CYCLES(1),      CYCLES(1),      CYCLES(5),      CYCLES(0),      CYCLES(5),      CYCLES(0),      CYCLES(5),      INVALID
+};
+
+static uint32_t opcode_timings_d8[8] =
+{
+/*      FADDs               FMULs               FCOMs                 FCOMPs*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FSUBs               FSUBRs              FDIVs                 FDIVRs*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+static uint32_t opcode_timings_d8_mod3[8] =
+{
+/*      FADD                  FMUL                  FCOM                  FCOMP*/
+        FPU_CYCLES(4,2,2),    FPU_CYCLES(4,2,2),    FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FSUB                  FSUBR                 FDIV                  FDIVR*/
+        FPU_CYCLES(4,2,2),    FPU_CYCLES(4,2,2),    FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_d9[8] =
+{
+/*      FLDs                                     FSTs                 FSTPs*/
+        FPU_CYCLES(2,0,0),   INVALID,            FPU_CYCLES(2,0,0),   FPU_CYCLES(2,0,0),
+/*      FLDENV               FLDCW               FSTENV               FSTCW*/
+        FPU_CYCLES(32,0,0),  FPU_CYCLES(8,0,0),  FPU_CYCLES(48,0,0),  FPU_CYCLES(2,0,0)
+};
+static uint32_t opcode_timings_d9_mod3[64] =
+{
+        /*FLD*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+        /*FXCH*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+        /*FNOP*/
+        FPU_CYCLES(3,0,0),  INVALID,            INVALID,            INVALID,
+        INVALID,            INVALID,            INVALID,            INVALID,
+        /*FSTP*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+/*      opFCHS              opFABS*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  INVALID,            INVALID,
+/*      opFTST              opFXAM*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(21,4,0), INVALID,            INVALID,
+/*      opFLD1              opFLDL2T            opFLDL2E            opFLDPI*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),
+/*      opFLDEG2            opFLDLN2            opFLDZ*/
+        FPU_CYCLES(5,2,2),  FPU_CYCLES(5,2,2),  FPU_CYCLES(2,0,0),  INVALID,
+/*      opF2XM1             opFYL2X             opFPTAN             opFPATAN*/
+        FPU_CYCLES(53,2,2), FPU_CYCLES(103,2,2),FPU_CYCLES(120,36,0),FPU_CYCLES(112,2,2),
+/*                                              opFDECSTP           opFINCSTP,*/
+        INVALID,            INVALID,            FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),
+/*      opFPREM                                 opFSQRT             opFSINCOS*/
+        FPU_CYCLES(64,2,2), INVALID,            FPU_CYCLES(70,69,2),FPU_CYCLES(89,2,2),
+/*      opFRNDINT           opFSCALE            opFSIN              opFCOS*/
+        FPU_CYCLES(9,0,0),  FPU_CYCLES(20,5,0), FPU_CYCLES(65,2,2), FPU_CYCLES(65,2,2)
+};
+
+static uint32_t opcode_timings_da[8] =
+{
+/*      FIADDl              FIMULl              FICOMl                FICOMPl*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(4,0,0),    FPU_CYCLES(4,0,0),
+/*      FISUBl              FISUBRl             FIDIVl                FIDIVRl*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(42,38,2),  FPU_CYCLES(42,38,2)
+};
+static uint32_t opcode_timings_da_mod3[8] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+/*                          FCOMPP*/
+        INVALID,            FPU_CYCLES(2,0,0),  INVALID,              INVALID
+};
+
+
+static uint32_t opcode_timings_db[8] =
+{
+/*      FLDil                                   FSTil                 FSTPil*/
+        FPU_CYCLES(3,2,2),  INVALID,            FPU_CYCLES(6,0,0),    FPU_CYCLES(6,0,0),
+/*                          FLDe                                      FSTPe*/
+        INVALID,            FPU_CYCLES(3,0,0),  INVALID,              FPU_CYCLES(3,0,0)
+};
+static uint32_t opcode_timings_db_mod3[64] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+/*                          opFNOP              opFCLEX               opFINIT*/
+        INVALID,            FPU_CYCLES(2,0,0),  FPU_CYCLES(7,0,0),    FPU_CYCLES(17,0,0),
+/*      opFNOP              opFNOP*/
+        FPU_CYCLES(2,0,0),  FPU_CYCLES(2,0,0),  INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+
+        INVALID,            INVALID,            INVALID,              INVALID,
+        INVALID,            INVALID,            INVALID,              INVALID,
+};
+
+static uint32_t opcode_timings_dc[8] =
+{
+/*      FADDd               FMULd               FCOMd                 FCOMPd*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FSUBd               FSUBRd              FDIVd                 FDIVRd*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+static uint32_t opcode_timings_dc_mod3[8] =
+{
+/*      opFADDr               opFMULr*/
+        FPU_CYCLES(4,2,2),    FPU_CYCLES(4,2,2),INVALID,              INVALID,
+/*      opFSUBRr              opFSUBr           opFDIVRr              opFDIVr*/
+        FPU_CYCLES(4,2,2),    FPU_CYCLES(4,2,2),FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_dd[8] =
+{
+/*      FLDd                                    FSTd                  FSTPd*/
+        FPU_CYCLES(2,0,0),    INVALID,          FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FRSTOR                                  FSAVE                 FSTSW*/
+        FPU_CYCLES(70,0,0),   INVALID,          FPU_CYCLES(127,0,0),  FPU_CYCLES(6,0,0)
+};
+static uint32_t opcode_timings_dd_mod3[8] =
+{
+/*      FFFREE                                  FST                   FSTP*/
+        FPU_CYCLES(2,0,0),    INVALID,          FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),
+/*      FUCOM                 FUCOMP*/
+        FPU_CYCLES(2,0,0),    FPU_CYCLES(2,0,0),INVALID,              INVALID
+};
+
+static uint32_t opcode_timings_de[8] =
+{
+/*      FIADDw              FIMULw              FICOMw                FICOMPw*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(4,0,0),    FPU_CYCLES(4,0,0),
+/*      FISUBw              FISUBRw             FIDIVw                FIDIVRw*/
+        FPU_CYCLES(6,2,2),  FPU_CYCLES(6,2,2),  FPU_CYCLES(42,38,2),  FPU_CYCLES(42,38,2)
+};
+static uint32_t opcode_timings_de_mod3[8] =
+{
+/*      FADDP               FMULP                                     FCOMPP*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  INVALID,              FPU_CYCLES(2,0,0),
+/*      FSUBP               FSUBRP              FDIVP                 FDIVRP*/
+        FPU_CYCLES(4,2,2),  FPU_CYCLES(4,2,2),  FPU_CYCLES(39,38,2),  FPU_CYCLES(39,38,2)
+};
+
+static uint32_t opcode_timings_df[8] =
+{
+/*      FILDiw                                  FISTiw                FISTPiw*/
+        FPU_CYCLES(3,2,2),  INVALID,            FPU_CYCLES(6,0,0),    FPU_CYCLES(6,0,0),
+/*                          FILDiq              FBSTP                 FISTPiq*/
+        INVALID,            FPU_CYCLES(3,2,2),  FPU_CYCLES(148,0,0),  FPU_CYCLES(6,0,0)
+};
+static uint32_t opcode_timings_df_mod3[8] =
+{
+        INVALID,            INVALID,            INVALID,              INVALID,
+/*      FSTSW AX*/
+        FPU_CYCLES(6,0,0),  INVALID,            INVALID,              INVALID
+};
+
+static uint32_t opcode_timings_8x[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_8x_mod3[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_81[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+static uint32_t opcode_timings_81_mod3[8] =
+{
+        CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2),      CYCLES(2)
+};
+
+static int timing_count;
+static uint8_t last_prefix;
+static uint32_t regmask_modified;
+static int decode_delay, decode_delay_offset;
+static int fpu_latency;
+static int fpu_st_latency[8];
+
+
+static inline int COUNT(uint32_t c, int op_32)
+{
+        if (c & CYCLES_FPU)
+                return FPU_I_LATENCY(c);
+        if (c & CYCLES_HAS_MULTI)
+        {
+                if (op_32 & 0x100)
+                        return (c >> 8) & 0xff;
+                return c & 0xff;
+        }
+        return GET_CYCLES(c);
+}
+
+static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_32)
+{
+        uint32_t addr_regmask = get_addr_regmask(deps[opcode], fetchdat, op_32);
+
+        /*Instructions that use ESP implicitly (eg PUSH, POP, CALL etc) do not
+          cause AGIs with each other, but do with instructions that use it explicitly*/
+        if ((addr_regmask & REGMASK_IMPL_ESP) && (regmask_modified & (1 << REG_ESP)) && !(regmask_modified & REGMASK_IMPL_ESP))
+                addr_regmask |= (1 << REG_ESP);
+
+        return (regmask_modified & addr_regmask) & ~REGMASK_IMPL_ESP;
+}
+
+static int codegen_fpu_latencies(uint64_t deps, int reg)
+{
+        int latency = fpu_latency;
+
+        if ((deps & FPU_RW_ST0) && fpu_st_latency[0] && fpu_st_latency[0] > latency)
+                latency = fpu_st_latency[0];
+        if ((deps & FPU_RW_ST1) && fpu_st_latency[1] && fpu_st_latency[1] > latency)
+                latency = fpu_st_latency[1];
+        if ((deps & FPU_RW_STREG) && fpu_st_latency[reg] && fpu_st_latency[reg] > latency)
+                latency = fpu_st_latency[reg];
+
+        return latency;
+}
+
+#define SUB_AND_CLAMP(latency, count)  \
+        latency -= count;              \
+        if (latency < 0)               \
+                latency = 0
+
+static void codegen_fpu_latency_clock(int count)
+{
+        SUB_AND_CLAMP(fpu_latency, count);
+        SUB_AND_CLAMP(fpu_st_latency[0], count);
+        SUB_AND_CLAMP(fpu_st_latency[1], count);
+        SUB_AND_CLAMP(fpu_st_latency[2], count);
+        SUB_AND_CLAMP(fpu_st_latency[3], count);
+        SUB_AND_CLAMP(fpu_st_latency[4], count);
+        SUB_AND_CLAMP(fpu_st_latency[5], count);
+        SUB_AND_CLAMP(fpu_st_latency[6], count);
+        SUB_AND_CLAMP(fpu_st_latency[7], count);
+}
+
+static void codegen_instruction(uint32_t *timings, uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int decode_delay_offset, int op_32, int exec_delay)
+{
+        int instr_cycles, latency = 0;
+
+        if ((timings[opcode] & CYCLES_FPU) && !(deps[opcode] & FPU_FXCH))
+                instr_cycles = latency = codegen_fpu_latencies(deps[opcode], fetchdat & 7);
+        else
+                instr_cycles = 0;
+
+        if ((decode_delay + decode_delay_offset) > 0)
+                codegen_fpu_latency_clock(decode_delay + decode_delay_offset + instr_cycles);
+        else
+                codegen_fpu_latency_clock(instr_cycles);
+        instr_cycles += COUNT(timings[opcode], op_32);
+        instr_cycles += exec_delay;
+        if ((decode_delay + decode_delay_offset) > 0)
+                codegen_block_cycles += instr_cycles + decode_delay + decode_delay_offset;
+        else
+                codegen_block_cycles += instr_cycles;
+        decode_delay = (-instr_cycles) + 1;
+
+        if (deps[opcode] & FPU_POP)
+        {
+                int c;
+
+                for (c = 0; c < 7; c++)
+                        fpu_st_latency[c] = fpu_st_latency[c+1];
+                fpu_st_latency[7] = 0;
+        }
+        if (deps[opcode] & FPU_POP2)
+        {
+                int c;
+
+                for (c = 0; c < 6; c++)
+                        fpu_st_latency[c] = fpu_st_latency[c+2];
+                fpu_st_latency[6] = fpu_st_latency[7] = 0;
+        }
+        if (timings[opcode] & CYCLES_FPU)
+        {
+  /*              if (fpu_latency)
+                        fatal("Bad latency FPU\n");*/
+                fpu_latency = FPU_F_LATENCY(timings[opcode]);
+        }
+
+        if (deps[opcode] & FPU_PUSH)
+        {
+                int c;
+
+                for (c = 0; c < 7; c++)
+                        fpu_st_latency[c+1] = fpu_st_latency[c];
+                fpu_st_latency[0] = 0;
+        }
+        if (deps[opcode] & FPU_WRITE_ST0)
+        {
+/*                if (fpu_st_latency[0])
+                        fatal("Bad latency ST0\n");*/
+                fpu_st_latency[0] = FPU_RESULT_LATENCY(timings[opcode]);
+        }
+        if (deps[opcode] & FPU_WRITE_ST1)
+        {
+/*                if (fpu_st_latency[1])
+                        fatal("Bad latency ST1\n");*/
+                fpu_st_latency[1] = FPU_RESULT_LATENCY(timings[opcode]);
+        }
+        if (deps[opcode] & FPU_WRITE_STREG)
+        {
+                int reg = fetchdat & 7;
+                if (deps[opcode] & FPU_POP)
+                        reg--;
+                if (reg >= 0 &&
+                        !(reg == 0 && (deps[opcode] & FPU_WRITE_ST0)) &&
+                        !(reg == 1 && (deps[opcode] & FPU_WRITE_ST1)))
+                {
+/*                        if (fpu_st_latency[reg])
+                                fatal("Bad latency STREG %i %08x %i %016llx %02x\n",fpu_st_latency[reg], fetchdat, reg, timings[opcode], opcode);*/
+                        fpu_st_latency[reg] = FPU_RESULT_LATENCY(timings[opcode]);
+                }
+        }
+}
+
+static void codegen_timing_cyrixiii_block_start()
+{
+        regmask_modified = 0;
+        decode_delay = decode_delay_offset = 0;
+}
+
+static void codegen_timing_cyrixiii_start()
+{
+        timing_count = 0;
+        last_prefix = 0;
+}
+
+static void codegen_timing_cyrixiii_prefix(uint8_t prefix, uint32_t fetchdat)
+{
+        if (prefix == 0x0f)
+        {
+                /*0fh prefix is 'free'*/
+                last_prefix = prefix;
+                return;
+        }
+        /*On C3 all prefixes take 1 cycle to decode. Decode may be shadowed
+          by execution of previous instructions*/
+        decode_delay_offset++;
+        last_prefix = prefix;
+}
+
+static void codegen_timing_cyrixiii_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
+{
+        uint32_t *timings;
+        uint64_t *deps;
+        int mod3 = ((fetchdat & 0xc0) == 0xc0);
+        int bit8 = !(opcode & 1);
+        int agi_stall = 0;
+
+        switch (last_prefix)
+        {
+                case 0x0f:
+                timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
+                deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
+//                pclog("timings 0f\n");
+                break;
+
+                case 0xd8:
+                timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
+                deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings d8\n");
+                break;
+                case 0xd9:
+                timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
+                deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+//                pclog("timings d9\n");
+                break;
+                case 0xda:
+                timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
+                deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings da\n");
+                break;
+                case 0xdb:
+                timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
+                deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
+                opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
+//                pclog("timings db\n");
+                break;
+                case 0xdc:
+                timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
+                deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings dc\n");
+                break;
+                case 0xdd:
+                timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
+                deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings dd\n");
+                break;
+                case 0xde:
+                timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
+                deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings de\n");
+                break;
+                case 0xdf:
+                timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
+                deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
+                opcode = (opcode >> 3) & 7;
+//                pclog("timings df\n");
+                break;
+
+                default:
+                switch (opcode)
+                {
+                        case 0x80: case 0x82: case 0x83:
+                        timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
+                        deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings 80 %p %p %p\n", (void *)timings, (void *)opcode_timings_mod3, (void *)opcode_timings_8x);
+                        break;
+                        case 0x81:
+                        timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
+                        deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings 80 %p %p %p\n", (void *)timings, (void *)opcode_timings_mod3, (void *)opcode_timings_8x);
+                        break;
+
+                        case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
+                        timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
+                        deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings c0\n");
+                        break;
+
+                        case 0xf6:
+                        timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
+                        deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings f6\n");
+                        break;
+                        case 0xf7:
+                        timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
+                        deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings f7\n");
+                        break;
+                        case 0xff:
+                        timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
+                        deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
+                        opcode = (fetchdat >> 3) & 7;
+//                        pclog("timings ff\n");
+                        break;
+
+                        default:
+                        timings = mod3 ? opcode_timings_mod3 : opcode_timings;
+                        deps = mod3 ? opcode_deps_mod3 : opcode_deps;
+//                        pclog("timings normal\n");
+                        break;
+                }
+        }
+
+        if (check_agi(deps, opcode, fetchdat, op_32))
+                agi_stall = 1;
+        codegen_instruction(timings, deps, opcode, fetchdat, decode_delay_offset, op_32, agi_stall);
+        decode_delay_offset = 0;
+        regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
+}
+
+static void codegen_timing_cyrixiii_block_end()
+{
+}
+
+int codegen_timing_cyrixiii_jump_cycles()
+{
+        return 0;
+}
+
+codegen_timing_t codegen_timing_cyrixiii =
+{
+        codegen_timing_cyrixiii_start,
+        codegen_timing_cyrixiii_prefix,
+        codegen_timing_cyrixiii_opcode,
+        codegen_timing_cyrixiii_block_start,
+        codegen_timing_cyrixiii_block_end,
+        codegen_timing_cyrixiii_jump_cycles
+};

src/cpu.c

@@ -6,7 +6,9 @@
 #include "mem.h"
 #include "pci.h"
 #include "codegen.h"
+#include "x87_timings.h"
 
+int fpu_type;
 uint32_t cpu_features;
 
 static int cpu_turbo_speed, cpu_nonturbo_speed;
@@ -68,6 +70,7 @@ enum
         CPUID_TSC = (1 << 4),
         CPUID_MSR = (1 << 5),
         CPUID_CMPXCHG8B = (1 << 8),
+        CPUID_SEP = (1 << 11),
         CPUID_CMOV = (1 << 15),
         CPUID_MMX = (1 << 23)
 };
@@ -125,10 +128,59 @@ void cpu_set_edx()
         EDX = models[model].cpu[cpu_manufacturer].cpus[cpu].edx_reset;
 }
 
+int fpu_get_type(int model, int manu, int cpu, const char *internal_name)
+{
+        CPU *cpu_s = &models[model].cpu[manu].cpus[cpu];
+        const FPU *fpus = cpu_s->fpus;
+        int fpu_type = fpus[0].type;
+        int c = 0;
+        
+        while (fpus[c].internal_name)
+        {
+                if (!strcmp(internal_name, fpus[c].internal_name))
+                        fpu_type = fpus[c].type;
+                c++;
+        }
+        
+        return fpu_type;
+}
+
+const char *fpu_get_internal_name(int model, int manu, int cpu, int type)
+{
+        CPU *cpu_s = &models[model].cpu[manu].cpus[cpu];
+        const FPU *fpus = cpu_s->fpus;
+        int c = 0;
+
+        while (fpus[c].internal_name)
+        {
+                if (fpus[c].type == type)
+                        return fpus[c].internal_name;
+                c++;
+        }
+
+        return fpus[0].internal_name;
+}
+
+const char *fpu_get_name_from_index(int model, int manu, int cpu, int c)
+{
+        CPU *cpu_s = &models[model].cpu[manu].cpus[cpu];
+        const FPU *fpus = cpu_s->fpus;
+        
+        return fpus[c].name;
+}
+
+int fpu_get_type_from_index(int model, int manu, int cpu, int c)
+{
+        CPU *cpu_s = &models[model].cpu[manu].cpus[cpu];
+        const FPU *fpus = cpu_s->fpus;
+
+        return fpus[c].type;
+}
+
+CPU *cpu_s;
+
 void cpu_set()
 {
-        CPU *cpu_s;
-        
         if (!models[model].cpu[cpu_manufacturer].cpus)
         {
                 /*CPU is invalid, set to default*/
@@ -143,7 +195,8 @@ void cpu_set()
         is8086   = (cpu_s->cpu_type > CPU_8088);
         is386    = (cpu_s->cpu_type >= CPU_386SX);
         is486    = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC);
-        hasfpu   = (cpu_s->cpu_type >= CPU_i486DX);
+        hasfpu   = (fpu_type != FPU_NONE);
+
          cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
         cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC);
         if (cpu_s->multi) 
@@ -159,6 +212,7 @@ void cpu_set()
                 cpu_nonturbo_speed = cpu_s->rspeed;
         else
                 cpu_nonturbo_speed = 8000000;
+        cpu_turbo = 1;
 
         cpu_update_waitstates();
   
@@ -280,6 +334,7 @@ void cpu_set()
 
         timing_misaligned = 0;
         cpu_cyrix_alignment = 0;
+        cpu_CR4_mask = 0;
         
         switch (cpu_s->cpu_type)
         {
@@ -734,7 +789,7 @@ void cpu_set()
                 break;
 
   		case CPU_Cx6x86:
-                x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
+                x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
                 timing_rr  = 1; /*register dest - register src*/
                 timing_rm  = 1; /*register dest - memory src*/
                 timing_mr  = 2; /*memory dest   - register src*/
@@ -953,9 +1008,170 @@ void cpu_set()
                 codegen_timing_set(&codegen_timing_k6);
                 break;
 
+                case CPU_PENTIUMPRO:
+                x86_setopcodes(ops_386, ops_pentiumpro_0f, dynarec_ops_386, dynarec_ops_pentiumpro_0f);
+                x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
+                x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
+                x86_dynarec_opcodes_db_a16 = dynarec_ops_fpu_686_db_a16;
+                x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
+                x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
+                x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+                x86_opcodes_da_a16 = ops_fpu_686_da_a16;
+                x86_opcodes_da_a32 = ops_fpu_686_da_a32;
+                x86_opcodes_db_a16 = ops_fpu_686_db_a16;
+                x86_opcodes_db_a32 = ops_fpu_686_db_a32;
+                x86_opcodes_df_a16 = ops_fpu_686_df_a16;
+                x86_opcodes_df_a32 = ops_fpu_686_df_a32;
+                timing_rr  = 1; /*register dest - register src*/
+                timing_rm  = 2; /*register dest - memory src*/
+                timing_mr  = 3; /*memory dest   - register src*/
+                timing_mm  = 3;
+                timing_rml = 2; /*register dest - memory src long*/
+                timing_mrl = 3; /*memory dest   - register src long*/
+                timing_mml = 3;
+                timing_bt  = 0; /*branch taken*/
+                timing_bnt = 2; /*branch not taken*/
+                timing_int = 6;
+                timing_int_rm       = 11;
+                timing_int_v86      = 54;
+                timing_int_pm       = 25;
+                timing_int_pm_outer = 42;
+                timing_iret_rm       = 7;
+                timing_iret_v86      = 27; /*unknown*/
+                timing_iret_pm       = 10;
+                timing_iret_pm_outer = 27;
+                timing_call_rm = 4;
+                timing_call_pm = 4;
+                timing_call_pm_gate = 22;
+                timing_call_pm_gate_inner = 44;
+                timing_retf_rm       = 4;
+                timing_retf_pm       = 4;
+                timing_retf_pm_outer = 23;
+                timing_jmp_rm      = 3;
+                timing_jmp_pm      = 3;
+                timing_jmp_pm_gate = 18;
+                timing_misaligned = 3;
+                cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_CX8 | CPU_FEATURE_SYSCALL;
+                msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
+                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+                codegen_timing_set(&codegen_timing_p6);
+                break;
+
+                case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
+                x86_setopcodes(ops_386, ops_pentium2_0f, dynarec_ops_386, dynarec_ops_pentium2_0f);
+                x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
+                x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
+                x86_dynarec_opcodes_db_a16 = dynarec_ops_fpu_686_db_a16;
+                x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
+                x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
+                x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
+                x86_opcodes_da_a16 = ops_fpu_686_da_a16;
+                x86_opcodes_da_a32 = ops_fpu_686_da_a32;
+                x86_opcodes_db_a16 = ops_fpu_686_db_a16;
+                x86_opcodes_db_a32 = ops_fpu_686_db_a32;
+                x86_opcodes_df_a16 = ops_fpu_686_df_a16;
+                x86_opcodes_df_a32 = ops_fpu_686_df_a32;
+                timing_rr  = 1; /*register dest - register src*/
+                timing_rm  = 2; /*register dest - memory src*/
+                timing_mr  = 3; /*memory dest   - register src*/
+                timing_mm  = 3;
+                timing_rml = 2; /*register dest - memory src long*/
+                timing_mrl = 3; /*memory dest   - register src long*/
+                timing_mml = 3;
+                timing_bt  = 0; /*branch taken*/
+                timing_bnt = 2; /*branch not taken*/
+                timing_int = 6;
+                timing_int_rm       = 11;
+                timing_int_v86      = 54;
+                timing_int_pm       = 25;
+                timing_int_pm_outer = 42;
+                timing_iret_rm       = 7;
+                timing_iret_v86      = 27; /*unknown*/
+                timing_iret_pm       = 10;
+                timing_iret_pm_outer = 27;
+                timing_call_rm = 4;
+                timing_call_pm = 4;
+                timing_call_pm_gate = 22;
+                timing_call_pm_gate_inner = 44;
+                timing_retf_rm       = 4;
+                timing_retf_pm       = 4;
+                timing_retf_pm_outer = 23;
+                timing_jmp_rm      = 3;
+                timing_jmp_pm      = 3;
+                timing_jmp_pm_gate = 18;
+                timing_misaligned = 3;
+                cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_CX8 | CPU_FEATURE_MMX | CPU_FEATURE_SYSCALL;
+                msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
+                cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
+                codegen_timing_set(&codegen_timing_p6);
+                break;
+
+                case CPU_CYRIX_III:
+                x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
+                timing_rr  = 1; /*register dest - register src*/
+                timing_rm  = 1; /*register dest - memory src*/
+                timing_mr  = 1; /*memory dest   - register src*/
+                timing_mm  = 1;
+                timing_rml = 1; /*register dest - memory src long*/
+                timing_mrl = 1; /*memory dest   - register src long*/
+                timing_mml = 1;
+                timing_bt  = 1; /*branch taken*/
+                timing_bnt = 1; /*branch not taken*/
+                cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW;
+                msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
+                cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
+                /*unknown*/
+                timing_int_rm       = 26;
+                timing_int_v86      = 82;
+                timing_int_pm       = 44;
+                timing_int_pm_outer = 71;
+                timing_iret_rm       = 7;
+                timing_iret_v86      = 26;
+                timing_iret_pm       = 10;
+                timing_iret_pm_outer = 26;
+                timing_call_rm = 4;
+                timing_call_pm = 15;
+                timing_call_pm_gate = 26;
+                timing_call_pm_gate_inner = 35;
+                timing_retf_rm       = 4;
+                timing_retf_pm       = 7;
+                timing_retf_pm_outer = 23;
+                timing_jmp_rm      = 5;
+                timing_jmp_pm      = 7;
+                timing_jmp_pm_gate = 17;
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
+                codegen_timing_set(&codegen_timing_cyrixiii);
+                break;
+
                 default:
                 fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
         }
+        
+        switch (fpu_type)
+        {
+                case FPU_NONE:
+                break;
+
+                case FPU_8087:
+                x87_timings = x87_timings_8087;
+                break;
+
+                case FPU_287:
+                x87_timings = x87_timings_287;
+                break;
+
+                case FPU_287XL:
+                case FPU_387:
+                x87_timings = x87_timings_387;
+                break;
+                
+                default:
+                x87_timings = x87_timings_486;
+                break;
+        }
 }
 
 void cpu_CPUID()
@@ -1451,6 +1667,132 @@ void cpu_CPUID()
                         break;
                 }
                 break;
+
+                case CPU_PENTIUMPRO:
+                if (!EAX)
+                {
+                        EAX = 0x00000002;
+                        EBX = 0x756e6547;
+                        EDX = 0x49656e69;
+                        ECX = 0x6c65746e;
+                }
+                else if (EAX == 1)
+                {
+                        EAX = CPUID;
+                        EBX = ECX = 0;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_CMOV | CPUID_SEP;
+                }
+                else if (EAX == 2)
+                {
+                        EAX = 0x03020101;
+                        EBX = 0;
+                        ECX = 0;
+                        EDX = 0x06040a42;
+                }
+                else
+                        EAX = EBX = ECX = EDX = 0;
+                break;
+                
+                case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
+                if (!EAX)
+                {
+                        EAX = 0x00000002;
+                        EBX = 0x756e6547;
+                        EDX = 0x49656e69;
+                        ECX = 0x6c65746e;
+                }
+                else if (EAX == 1)
+                {
+                        EAX = CPUID;
+                        EBX = ECX = 0;
+                        EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_CMOV | CPUID_MMX | CPUID_SEP;
+                }
+                else if (EAX == 2)
+                {
+                        EAX = 0x03020101;
+                        EBX = 0;
+                        ECX = 0;
+                        if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUM_2)
+                                EDX = 0x08040c43; /*512kb L2 cache*/
+                        else if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_CELERON)
+                                EDX = 0x08040c40; /*No L2 cache*/
+                        else
+                                EDX = 0x08040c41; /*128kb L2 cache*/
+                }
+                else
+                        EAX = EBX = ECX = EDX = 0;
+                break;
+
+                case CPU_CYRIX_III:
+                switch (EAX)
+                {
+                        case 0:
+                        EAX = 1;
+                        EBX = 0x746e6543; /*CentaurHauls*/
+                        ECX = 0x736c7561;
+                        EDX = 0x48727561;
+                        break;
+                        case 1:
+                        EAX = models[model].cpu[cpu_manufacturer].cpus[cpu].cpuid_model;
+                        EBX = ECX = 0;
+                        EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
+			if (cpu_has_feature(CPU_FEATURE_CX8))
+				EDX |= CPUID_CMPXCHG8B;
+                        if (msr.fcr & (1 << 9))
+                                EDX |= CPUID_MMX;
+                        break;
+                        case 0x80000000:
+                        EAX = 0x80000006;
+                        break;
+                        case 0x80000001:
+                        EAX = models[model].cpu[cpu_manufacturer].cpus[cpu].edx_reset;
+                        EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
+			if (cpu_has_feature(CPU_FEATURE_CX8))
+				EDX |= CPUID_CMPXCHG8B;
+                        if (msr.fcr & (1 << 9))
+                                EDX |= CPUID_MMX;
+			if (cpu_has_feature(CPU_FEATURE_3DNOW))
+                                EDX |= CPUID_3DNOW;
+                        break;
+
+                        case 0x80000002: /*Processor name string*/
+                        if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpuid_model >= 0x670)
+                        {
+                                EAX = 0x20414956; /*VIA Samuel 2*/
+                                EBX = 0x756d6153;
+                                ECX = 0x32206c65;
+                                EDX = 0x00000000;
+                        }
+                        else
+                        {
+                                EAX = 0x20414956; /*VIA SamuelM*/
+                                EBX = 0x756d6153;
+                                ECX = 0x004d6c65;
+                                EDX = 0x00000000;
+                        }
+                        break;
+
+                        case 0x80000005: /*Cache information*/
+                        EBX = 0x08800880; /*TLBs*/
+                        ECX = 0x40040120; /*L1 data cache*/
+                        EDX = 0x40020120; /*L1 instruction cache*/
+                        break;
+
+                        case 0x80000006: /*L2 Cache information*/
+                        if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpuid_model >= 0x670)
+                                ECX = 0x40040120; /*L2 cache*/
+                        else
+                                ECX = 0;
+                        EAX = EBX = EDX = 0;
+                        break;
+
+                        default:
+                        EAX = EBX = ECX = EDX = 0;
+                        break;
+                }
+                break;
         }
 }
 
@@ -1460,6 +1802,7 @@ void cpu_RDMSR()
         {
                 case CPU_WINCHIP:
                 case CPU_WINCHIP2:
+                case CPU_CYRIX_III:
                 EAX = EDX = 0;
                 switch (ECX)
                 {
@@ -1526,6 +1869,32 @@ void cpu_RDMSR()
                         break;
                 }
                 break;
+                case CPU_PENTIUMPRO:
+                case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
+                EAX = EDX = 0;
+                switch (ECX)
+                {
+                        case 0x10:
+                        EAX = tsc & 0xffffffff;
+                        EDX = tsc >> 32;
+                        break;
+
+                        case 0x174:
+                        EAX = sysenter_cs;
+                        EDX = 0;
+                        break;
+                        case 0x175:
+                        EAX = sysenter_esp;
+                        EDX = 0;
+                        break;
+                        case 0x176:
+                        EAX = sysenter_eip;
+                        EDX = 0;
+                        break;
+                }
+                break;
         }
 }
 
@@ -1535,6 +1904,7 @@ void cpu_WRMSR()
         {
                 case CPU_WINCHIP:
                 case CPU_WINCHIP2:
+                case CPU_CYRIX_III:
                 switch (ECX)
                 {
                         case 0x02:
@@ -1609,11 +1979,39 @@ void cpu_WRMSR()
                         break;
                 }
                 break;
+                case CPU_PENTIUMPRO:
+                case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
+                switch (ECX)
+                {
+                        case 0x10:
+                        tsc = EAX | ((uint64_t)EDX << 32);
+                        break;
+                        
+                        case 0x174:
+                        sysenter_cs = EAX & 0xffff;
+                        break;
+                        case 0x175:
+                        sysenter_esp = EAX;
+                        break;
+                        case 0x176:
+                        sysenter_eip = EAX;
+                        break;
+                }
+                break;
         }
 }
 
 static int cyrix_addr;
 
+#define CCR1_USE_SMI  (1 << 1)
+#define CCR1_SMAC     (1 << 2)
+#define CCR1_SM3      (1 << 7)
+
+#define CCR3_SMI_LOCK (1 << 0)
+#define CCR3_NMI_EN   (1 << 1)
+
 void cyrix_write(uint16_t addr, uint8_t val, void *priv)
 {
         if (!(addr & 1))
@@ -1624,14 +2022,46 @@ void cyrix_write(uint16_t addr, uint8_t val, void *priv)
                 ccr0 = val;
                 break;
                 case 0xc1: /*CCR1*/
+                if ((ccr3 & CCR3_SMI_LOCK) && !(cpu_cur_status & CPU_STATUS_SMM))
+                        val = (val & ~(CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) | (ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3));
                 ccr1 = val;
                 break;
                 case 0xc2: /*CCR2*/
                 ccr2 = val;
                 break;
                 case 0xc3: /*CCR3*/
+                if ((ccr3 & CCR3_SMI_LOCK) && !(cpu_cur_status & CPU_STATUS_SMM))
+                        val = (val & ~(CCR3_NMI_EN)) | (ccr3 & CCR3_NMI_EN) | CCR3_SMI_LOCK;
                 ccr3 = val;
                 break;
+                case 0xcd:
+                if (!(ccr3 & CCR3_SMI_LOCK) || (cpu_cur_status & CPU_STATUS_SMM))
+                {
+                        cyrix.arr[3].base = (cyrix.arr[3].base & ~0xff000000) | (val << 24);
+                        cyrix.smhr &= ~SMHR_VALID;
+                }
+                break;
+                case 0xce:
+                if (!(ccr3 & CCR3_SMI_LOCK) || (cpu_cur_status & CPU_STATUS_SMM))
+                {
+                        cyrix.arr[3].base = (cyrix.arr[3].base & ~0x00ff0000) | (val << 16);
+                        cyrix.smhr &= ~SMHR_VALID;
+                }
+                break;
+                case 0xcf:
+                if (!(ccr3 & CCR3_SMI_LOCK) || (cpu_cur_status & CPU_STATUS_SMM))
+                {
+                        cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
+                        if ((val & 0xf) == 0xf)
+                                cyrix.arr[3].size = 1ull << 32; /*4 GB*/
+                        else if (val & 0xf)
+                                cyrix.arr[3].size = 2048 << (val & 0xf);
+                        else
+                                cyrix.arr[3].size = 0; /*Disabled*/
+                        cyrix.smhr &= ~SMHR_VALID;
+                }
+                break;
+
                 case 0xe8: /*CCR4*/
                 if ((ccr3 & 0xf0) == 0x10)
                 {
@@ -1672,7 +2102,6 @@ uint8_t cyrix_read(uint16_t addr, void *priv)
                         case 0xfe: return models[model].cpu[cpu_manufacturer].cpus[cpu].cyrix_id & 0xff;
                         case 0xff: return models[model].cpu[cpu_manufacturer].cpus[cpu].cyrix_id >> 8;
                 }
-                if ((cyrix_addr & ~0xf0) == 0xc0) return 0xff;
                 if (cyrix_addr == 0x20 && models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_Cx5x86) return 0xff;
         }
         return 0xff;
@@ -1753,9 +2182,25 @@ void cpu_set_turbo(int turbo)
         }
 }
 
+int cpu_get_turbo()
+{
+        return cpu_turbo;
+}
+
 int cpu_get_speed()
 {
         if (cpu_turbo)
                 return cpu_turbo_speed;
         return cpu_nonturbo_speed;
 }
+
+void cpu_set_nonturbo_divider(int divider)
+{
+        if (divider < 2)
+                cpu_set_turbo(1);
+        else
+        {
+                cpu_nonturbo_speed = cpu_turbo_speed / divider;
+                cpu_set_turbo(0);
+        }
+}

src/cpu.h

@@ -2,6 +2,7 @@
 #define _CPU_H_
 
 extern int cpu, cpu_manufacturer;
+extern int fpu_type;
 
 /*808x class CPUs*/
 #define CPU_8088 0
@@ -40,11 +41,17 @@ extern int cpu, cpu_manufacturer;
 #define CPU_K6_3        25
 #define CPU_K6_2P       26
 #define CPU_K6_3P       27
+#define CPU_PENTIUMPRO  28
+#define CPU_PENTIUM_2   29
+#define CPU_CELERON     30
+#define CPU_CELERON_A   31
+#define CPU_CYRIX_III   32
 
 #define MANU_INTEL 0
 #define MANU_AMD   1
 #define MANU_CYRIX 2
 #define MANU_IDT   3
+#define MANU_VIA   4
 
 extern int timing_rr;
 extern int timing_mr, timing_mrl;
@@ -60,10 +67,28 @@ extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
 
 extern int timing_misaligned;
 
+enum
+{
+        FPU_NONE,
+        FPU_8087,
+        FPU_287,
+        FPU_287XL,
+        FPU_387,
+        FPU_BUILTIN
+};
+
+typedef struct
+{
+        const char *name;
+        const char *internal_name;
+        const int type;
+} FPU;
+
 typedef struct
 {
         char name[32];
         int cpu_type;
+        const FPU *fpus;
         int speed;
         int rspeed;
         int multi;
@@ -77,6 +102,8 @@ typedef struct
         int atclk_div;
 } CPU;
 
+extern CPU *cpu_s;
+
 extern CPU cpus_8088[];
 extern CPU cpus_8086[];
 extern CPU cpus_286[];
@@ -95,12 +122,17 @@ extern CPU cpus_Pentium5V[];
 extern CPU cpus_PentiumS5[];
 extern CPU cpus_Pentium[];
 extern CPU cpus_6x86[];
+extern CPU cpus_6x86_SS7[];
 extern CPU cpus_K6_S7[];
 extern CPU cpus_K6_SS7[];
+extern CPU cpus_PentiumPro[];
+extern CPU cpus_Slot1_100MHz[];
+extern CPU cpus_VIA_100MHz[];
 
 extern CPU cpus_pcjr[];
 extern CPU cpus_europc[];
 extern CPU cpus_pc1512[];
+extern CPU cpus_super286tr[];
 extern CPU cpus_ibmat[];
 extern CPU cpus_ibmxt286[];
 extern CPU cpus_ps1_m2011[];
@@ -114,13 +146,14 @@ extern int cpu_multi;
 /*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/
 extern int cpu_cyrix_alignment;
 
-#define CPU_FEATURE_RDTSC (1 << 0)
+#define CPU_FEATURE_RDTSC   (1 << 0)
-#define CPU_FEATURE_MSR   (1 << 1)
+#define CPU_FEATURE_MSR     (1 << 1)
-#define CPU_FEATURE_MMX   (1 << 2)
+#define CPU_FEATURE_MMX     (1 << 2)
-#define CPU_FEATURE_CR4   (1 << 3)
+#define CPU_FEATURE_CR4     (1 << 3)
-#define CPU_FEATURE_VME   (1 << 4)
+#define CPU_FEATURE_VME     (1 << 4)
-#define CPU_FEATURE_CX8   (1 << 5)
+#define CPU_FEATURE_CX8     (1 << 5)
-#define CPU_FEATURE_3DNOW (1 << 6)
+#define CPU_FEATURE_3DNOW   (1 << 6)
+#define CPU_FEATURE_SYSCALL (1 << 7)
 
 extern uint32_t cpu_features;
 static inline int cpu_has_feature(int feature)
@@ -163,12 +196,20 @@ extern uint64_t xt_cpu_multi;
 extern int isa_cycles;
 #define ISA_CYCLES(x) (x * isa_cycles)
 
+#define CPU_CLOCK_DIVIDER_MAX 16384
 void cpu_update_waitstates();
 void cpu_set();
 void cpu_set_edx();
 void cpu_set_turbo(int turbo);
+int cpu_get_turbo();
+void cpu_set_nonturbo_divider(int divider);
 int cpu_get_speed();
 
 extern int has_vlb;
 
+int fpu_get_type(int model, int manu, int cpu, const char *internal_name);
+const char *fpu_get_internal_name(int model, int manu, int cpu, int type);
+const char *fpu_get_name_from_index(int model, int manu, int cpu, int c);
+int fpu_get_type_from_index(int model, int manu, int cpu, int c);
+
 #endif

src/cpu_tables.c

@@ -22,409 +22,530 @@
         17 = 200 MHz
 */
 
+FPU fpus_none[] =
+{
+        {"None", "none", FPU_NONE},
+        {NULL, NULL, 0}
+};
+FPU fpus_8088[] =
+{
+        {"None", "none", FPU_NONE},
+        {"8087", "8087", FPU_8087},
+        {NULL, NULL, 0}
+};
+FPU fpus_80286[] =
+{
+        {"None",  "none", FPU_NONE},
+        {"287",   "287",  FPU_287},
+        {"287XL", "287xl",  FPU_287XL},
+        {NULL, NULL, 0}
+};
+FPU fpus_80386[] =
+{
+        {"None", "none", FPU_NONE},
+        {"387",  "387",  FPU_387},
+        {NULL, NULL, 0}
+};
+FPU fpus_builtin[] =
+{
+        {"Built-in", "builtin", FPU_BUILTIN},
+        {NULL, NULL, 0}
+};
+
 CPU cpus_8088[] =
 {
         /*8088 standard*/
-        {"8088/4.77",    CPU_8088,  0,  4772728,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/4.77",    CPU_8088,  fpus_8088, 0,  4772728,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8088/7.16",    CPU_8088,  1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/7.16",    CPU_8088,  fpus_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8088/8",       CPU_8088,  1,  8000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/8",       CPU_8088,  fpus_8088, 1,  8000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8088/10",      CPU_8088,  2, 10000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/10",      CPU_8088,  fpus_8088, 2, 10000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8088/12",      CPU_8088,  3, 12000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/12",      CPU_8088,  fpus_8088, 3, 12000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8088/16",      CPU_8088,  4, 16000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/16",      CPU_8088,  fpus_8088, 4, 16000000,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_pcjr[] =
 {
         /*8088 PCjr*/
-        {"8088/4.77",    CPU_8088,  0,  4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8088/4.77",    CPU_8088,  fpus_none, 0,  4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_europc[] =
 {
          /*8088 EuroPC*/
-         {"8088/4.77",    CPU_8088,  0,  4772728,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+         {"8088/4.77",    CPU_8088,  fpus_8088, 0,  4772728,   1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-         {"8088/7.16",    CPU_8088,  1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+         {"8088/7.16",    CPU_8088,  fpus_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-         {"8088/9.54",    CPU_8088,  1,  4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+         {"8088/9.54",    CPU_8088,  fpus_8088, 1,  4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
          {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_8086[] =
 {
         /*8086 standard*/
-        {"8086/7.16",    CPU_8086,  1, 14318184/2,     1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/7.16",    CPU_8086,  fpus_8088, 1, 14318184/2,     1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8086/8",       CPU_8086,  1,  8000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/8",       CPU_8086,  fpus_8088, 1,  8000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8086/9.54",    CPU_8086,  1,  4772728*2,     1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/9.54",    CPU_8086,  fpus_8088, 1,  4772728*2,     1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8086/10",      CPU_8086,  2, 10000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/10",      CPU_8086,  fpus_8088, 2, 10000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8086/12",      CPU_8086,  3, 12000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/12",      CPU_8086,  fpus_8088, 3, 12000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
-        {"8086/16",      CPU_8086,  4, 16000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 2},
+        {"8086/16",      CPU_8086,  fpus_8088, 4, 16000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 2},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_pc1512[] =
 {
         /*8086 Amstrad*/
-        {"8086/8",       CPU_8086,  1,  8000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
+        {"8086/8",       CPU_8086,  fpus_8088, 1,  8000000,       1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_286[] =
 {
         /*286*/
-        {"286/6",        CPU_286,   0,  6000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/6",        CPU_286,   fpus_80286, 0,  6000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
-        {"286/8",        CPU_286,   1,  8000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/8",        CPU_286,   fpus_80286, 1,  8000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
-        {"286/10",       CPU_286,   2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/10",       CPU_286,   fpus_80286, 2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
-        {"286/12",       CPU_286,   3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
+        {"286/12",       CPU_286,   fpus_80286, 3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
-        {"286/16",       CPU_286,   4, 16000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
+        {"286/16",       CPU_286,   fpus_80286, 4, 16000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
-        {"286/20",       CPU_286,   5, 20000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
+        {"286/20",       CPU_286,   fpus_80286, 5, 20000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
-        {"286/25",       CPU_286,   6, 25000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
+        {"286/25",       CPU_286,   fpus_80286, 6, 25000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
+        {"",             -1,        0, 0, 0, 0}
+};
+
+CPU cpus_super286tr[] =
+{
+        /*286*/
+        {"286/12",       CPU_286,   fpus_80286, 3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_ibmat[] =
 {
         /*286*/
-        {"286/6",        CPU_286,   0,  6000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 1},
+        {"286/6",        CPU_286,   fpus_80286, 0,  6000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 1},
-        {"286/8",        CPU_286,   0,  8000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 1},
+        {"286/8",        CPU_286,   fpus_80286, 0,  8000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_ibmxt286[] =
 {
         /*286*/
-        {"286/6",        CPU_286,   0,  6000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/6",        CPU_286,   fpus_80286, 0,  6000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_ps1_m2011[] =
 {
         /*286*/
-        {"286/10",       CPU_286,   2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/10",       CPU_286,   fpus_80286, 2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_ps2_m30_286[] =
 {
         /*286*/
-        {"286/10",       CPU_286,   2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
+        {"286/10",       CPU_286,   fpus_80286, 2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2, 1},
-        {"286/12",       CPU_286,   3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
+        {"286/12",       CPU_286,   fpus_80286, 3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
-        {"286/16",       CPU_286,   4, 16000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
+        {"286/16",       CPU_286,   fpus_80286, 4, 16000000, 1, 0, 0, 0, 0, 0, 3,3,3,3, 2},
-        {"286/20",       CPU_286,   5, 20000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
+        {"286/20",       CPU_286,   fpus_80286, 5, 20000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
-        {"286/25",       CPU_286,   6, 25000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
+        {"286/25",       CPU_286,   fpus_80286, 6, 25000000, 1, 0, 0, 0, 0, 0, 4,4,4,4, 3},
         {"",             -1,        0, 0, 0, 0}
 };
 
 CPU cpus_i386SX[] =
 {
         /*i386SX*/
-        {"i386SX/16",    CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3, 2},
+        {"i386SX/16",    CPU_386SX, fpus_80386, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3, 2},
-        {"i386SX/20",    CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
+        {"i386SX/20",    CPU_386SX, fpus_80386, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"i386SX/25",    CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
+        {"i386SX/25",    CPU_386SX, fpus_80386, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"i386SX/33",    CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3, 4},
+        {"i386SX/33",    CPU_386SX, fpus_80386, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3, 4},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_i386DX[] =
 {
         /*i386DX*/
-        {"i386DX/16",    CPU_386DX, 0, 16000000, 1, 0, 0x0308, 0, 0, 0, 3,3,3,3, 2},
+        {"i386DX/16",    CPU_386DX, fpus_80386, 0, 16000000, 1, 0, 0x0308, 0, 0, 0, 3,3,3,3, 2},
-        {"i386DX/20",    CPU_386DX, 1, 20000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
+        {"i386DX/20",    CPU_386DX, fpus_80386, 1, 20000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
-        {"i386DX/25",    CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
+        {"i386DX/25",    CPU_386DX, fpus_80386, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
-        {"i386DX/33",    CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3, 4},
+        {"i386DX/33",    CPU_386DX, fpus_80386, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3, 4},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_acer[] =
 {
         /*i386SX*/
-        {"i386SX/25",    CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,4,4, 3},
+        {"i386SX/25",    CPU_386SX, fpus_80386, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,4,4, 3},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Am386SX[] =
 {
         /*Am386*/
-        {"Am386SX/16",   CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3, 2},
+        {"Am386SX/16",   CPU_386SX, fpus_80386, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3, 2},
-        {"Am386SX/20",   CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
+        {"Am386SX/20",   CPU_386SX, fpus_80386, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"Am386SX/25",   CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
+        {"Am386SX/25",   CPU_386SX, fpus_80386, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3, 3},
-        {"Am386SX/33",   CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3, 4},
+        {"Am386SX/33",   CPU_386SX, fpus_80386, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3, 4},
-        {"Am386SX/40",   CPU_386SX, 4, 40000000, 1, 0, 0x2308, 0, 0, 0, 7,7,3,3, 5},
+        {"Am386SX/40",   CPU_386SX, fpus_80386, 4, 40000000, 1, 0, 0x2308, 0, 0, 0, 7,7,3,3, 5},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Am386DX[] =
 {
         /*Am386*/
-        {"Am386DX/25",   CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
+        {"Am386DX/25",   CPU_386DX, fpus_80386, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3, 3},
-        {"Am386DX/33",   CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3, 4},
+        {"Am386DX/33",   CPU_386DX, fpus_80386, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3, 4},
-        {"Am386DX/40",   CPU_386DX, 4, 40000000, 1, 0, 0x0308, 0, 0, 0, 7,7,3,3, 5},
+        {"Am386DX/40",   CPU_386DX, fpus_80386, 4, 40000000, 1, 0, 0x0308, 0, 0, 0, 7,7,3,3, 5},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_486SLC[] =
 {
         /*Cx486SLC*/
-        {"Cx486SLC/20",  CPU_486SLC, 1, 20000000, 1, 0, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
+        {"Cx486SLC/20",  CPU_486SLC, fpus_80386, 1, 20000000, 1, 0, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
-        {"Cx486SLC/25",  CPU_486SLC, 2, 25000000, 1, 0, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
+        {"Cx486SLC/25",  CPU_486SLC, fpus_80386, 2, 25000000, 1, 0, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
-        {"Cx486SLC/33",  CPU_486SLC, 3, 33333333, 1, 0, 0x400, 0, 0x0000, 0, 6,6,3,3, 4},
+        {"Cx486SLC/33",  CPU_486SLC, fpus_80386, 3, 33333333, 1, 0, 0x400, 0, 0x0000, 0, 6,6,3,3, 4},
-        {"Cx486SRx2/32", CPU_486SLC, 3, 32000000, 2, 0, 0x406, 0, 0x0006, 0, 6,6,6,6, 2*2},
+        {"Cx486SRx2/32", CPU_486SLC, fpus_80386, 3, 32000000, 2, 0, 0x406, 0, 0x0006, 0, 6,6,6,6, 2*2},
-        {"Cx486SRx2/40", CPU_486SLC, 4, 40000000, 2, 0, 0x406, 0, 0x0006, 0, 8,8,6,6, 2*3},
+        {"Cx486SRx2/40", CPU_486SLC, fpus_80386, 4, 40000000, 2, 0, 0x406, 0, 0x0006, 0, 8,8,6,6, 2*3},
-        {"Cx486SRx2/50", CPU_486SLC, 5, 50000000, 2, 0, 0x406, 0, 0x0006, 0, 8,8,6,6, 2*3},
+        {"Cx486SRx2/50", CPU_486SLC, fpus_80386, 5, 50000000, 2, 0, 0x406, 0, 0x0006, 0, 8,8,6,6, 2*3},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_486DLC[] =
 {
         /*Cx486DLC*/
-        {"Cx486DLC/25",  CPU_486DLC, 2, 25000000, 1, 0, 0x401, 0, 0x0001, 0, 4,4,3,3, 3},
+        {"Cx486DLC/25",  CPU_486DLC, fpus_80386, 2, 25000000, 1, 0, 0x401, 0, 0x0001, 0, 4,4,3,3, 3},
-        {"Cx486DLC/33",  CPU_486DLC, 3, 33333333, 1, 0, 0x401, 0, 0x0001, 0, 6,6,3,3, 4},
+        {"Cx486DLC/33",  CPU_486DLC, fpus_80386, 3, 33333333, 1, 0, 0x401, 0, 0x0001, 0, 6,6,3,3, 4},
-        {"Cx486DLC/40",  CPU_486DLC, 4, 40000000, 1, 0, 0x401, 0, 0x0001, 0, 7,7,3,3, 5},
+        {"Cx486DLC/40",  CPU_486DLC, fpus_80386, 4, 40000000, 1, 0, 0x401, 0, 0x0001, 0, 7,7,3,3, 5},
-        {"Cx486DRx2/32", CPU_486DLC, 3, 32000000, 2, 0, 0x407, 0, 0x0007, 0, 6,6,6,6, 2*2},
+        {"Cx486DRx2/32", CPU_486DLC, fpus_80386, 3, 32000000, 2, 0, 0x407, 0, 0x0007, 0, 6,6,6,6, 2*2},
-        {"Cx486DRx2/40", CPU_486DLC, 4, 40000000, 2, 0, 0x407, 0, 0x0007, 0, 8,8,6,6, 2*3},
+        {"Cx486DRx2/40", CPU_486DLC, fpus_80386, 4, 40000000, 2, 0, 0x407, 0, 0x0007, 0, 8,8,6,6, 2*3},
-        {"Cx486DRx2/50", CPU_486DLC, 5, 50000000, 2, 0, 0x407, 0, 0x0007, 0, 8,8,6,6, 2*3},
+        {"Cx486DRx2/50", CPU_486DLC, fpus_80386, 5, 50000000, 2, 0, 0x407, 0, 0x0007, 0, 8,8,6,6, 2*3},
-        {"Cx486DRx2/66", CPU_486DLC, 6, 66666666, 2, 0, 0x407, 0, 0x0007, 0, 12,12,6,6, 2*4},
+        {"Cx486DRx2/66", CPU_486DLC, fpus_80386, 6, 66666666, 2, 0, 0x407, 0, 0x0007, 0, 12,12,6,6, 2*4},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_i486[] =
 {
         /*i486*/
-        {"i486SX/16",    CPU_i486SX, 0,  16000000, 1, 16000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3,3,3,3, 2},
+        {"i486SX/16",    CPU_i486SX, fpus_none,    0,  16000000, 1, 16000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3,3,3,3, 2},
-        {"i486SX/20",    CPU_i486SX, 1,  20000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
+        {"i486SX/20",    CPU_i486SX, fpus_none,    1,  20000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
-        {"i486SX/25",    CPU_i486SX, 2,  25000000, 1, 25000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
+        {"i486SX/25",    CPU_i486SX, fpus_none,    2,  25000000, 1, 25000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
-        {"i486SX/33",    CPU_i486SX, 3,  33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"i486SX/33",    CPU_i486SX, fpus_none,    3,  33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"i486SX2/50",   CPU_i486SX, 5,  50000000, 2, 25000000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
+        {"i486SX2/50",   CPU_i486SX, fpus_none,    5,  50000000, 2, 25000000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
-        {"i486DX/25",    CPU_i486DX, 2,  25000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
+        {"i486DX/25",    CPU_i486DX, fpus_builtin, 2,  25000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
-        {"i486DX/33",    CPU_i486DX, 3,  33333333, 1, 33333333, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"i486DX/33",    CPU_i486DX, fpus_builtin, 3,  33333333, 1, 33333333, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"i486DX/50",    CPU_i486DX, 5,  50000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4, 6},
+        {"i486DX/50",    CPU_i486DX, fpus_builtin, 5,  50000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4, 6},
-        {"i486DX2/40",   CPU_i486DX, 4,  40000000, 2, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
+        {"i486DX2/40",   CPU_i486DX, fpus_builtin, 4,  40000000, 2, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
-        {"i486DX2/50",   CPU_i486DX, 5,  50000000, 2, 25000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
+        {"i486DX2/50",   CPU_i486DX, fpus_builtin, 5,  50000000, 2, 25000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
-        {"i486DX2/66",   CPU_i486DX, 6,  66666666, 2, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
+        {"i486DX2/66",   CPU_i486DX, fpus_builtin, 6,  66666666, 2, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
-        {"iDX4/75",      CPU_iDX4,   7,  75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3}, /*CPUID available on DX4, >= 75 MHz*/
+        {"iDX4/75",      CPU_iDX4,   fpus_builtin, 7,  75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3}, /*CPUID available on DX4, >= 75 MHz*/
-        {"iDX4/100",     CPU_iDX4,  10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*4}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
+        {"iDX4/100",     CPU_iDX4,   fpus_builtin, 10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*4}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
-        {"Pentium OverDrive/63",       CPU_PENTIUM,     6,  62500000, 3, 25000000, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, (5*3)/2},
+        {"Pentium OverDrive/63",       CPU_PENTIUM,     fpus_builtin, 6,  62500000, 3, 25000000, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, (5*3)/2},
-        {"Pentium OverDrive/83",       CPU_PENTIUM,     8,  83333333, 3, 33333333, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, (5*4)/2},
+        {"Pentium OverDrive/83",       CPU_PENTIUM,     fpus_builtin, 8,  83333333, 3, 33333333, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, (5*4)/2},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Am486[] =
 {
         /*Am486/5x86*/
-        {"Am486SX/33",   CPU_Am486SX,  3,  33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"Am486SX/33",   CPU_Am486SX, fpus_none,    3,  33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"Am486SX/40",   CPU_Am486SX,  4,  40000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
+        {"Am486SX/40",   CPU_Am486SX, fpus_none,    4,  40000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
-        {"Am486SX2/50",  CPU_Am486SX,  5,  50000000, 2, 25000000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
+        {"Am486SX2/50",  CPU_Am486SX, fpus_none,    5,  50000000, 2, 25000000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
-        {"Am486SX2/66",  CPU_Am486SX,  6,  66666666, 2, 33333333, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
+        {"Am486SX2/66",  CPU_Am486SX, fpus_none,    6,  66666666, 2, 33333333, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
-        {"Am486DX/33",   CPU_Am486DX,  3,  33333333, 1, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"Am486DX/33",   CPU_Am486DX, fpus_builtin, 3,  33333333, 1, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"Am486DX/40",   CPU_Am486DX,  4,  40000000, 1, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
+        {"Am486DX/40",   CPU_Am486DX, fpus_builtin, 4,  40000000, 1, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
-        {"Am486DX2/50",  CPU_Am486DX,  5,  50000000, 2, 25000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
+        {"Am486DX2/50",  CPU_Am486DX, fpus_builtin, 5,  50000000, 2, 25000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
-        {"Am486DX2/66",  CPU_Am486DX,  6,  66666666, 2, 33333333, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
+        {"Am486DX2/66",  CPU_Am486DX, fpus_builtin, 6,  66666666, 2, 33333333, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
-        {"Am486DX2/80",  CPU_Am486DX,  8,  80000000, 2, 20000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14,6,6, 2*5},
+        {"Am486DX2/80",  CPU_Am486DX, fpus_builtin, 8,  80000000, 2, 20000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14,6,6, 2*5},
-        {"Am486DX4/75",  CPU_Am486DX,  7,  75000000, 3, 25000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3},
+        {"Am486DX4/75",  CPU_Am486DX, fpus_builtin, 7,  75000000, 3, 25000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3},
-        {"Am486DX4/90",  CPU_Am486DX,  9,  90000000, 3, 30000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
+        {"Am486DX4/90",  CPU_Am486DX, fpus_builtin, 9,  90000000, 3, 30000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
-        {"Am486DX4/100", CPU_Am486DX, 10, 100000000, 3, 33333333, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
+        {"Am486DX4/100", CPU_Am486DX, fpus_builtin, 10, 100000000, 3, 33333333, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
-        {"Am486DX4/120", CPU_Am486DX, 11, 120000000, 3, 20000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21,9,9, 3*5},
+        {"Am486DX4/120", CPU_Am486DX, fpus_builtin, 11, 120000000, 3, 20000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21,9,9, 3*5},
-        {"Am5x86/P75",   CPU_Am486DX, 12, 133333333, 4, 33333333, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*4},
+        {"Am5x86/P75",   CPU_Am486DX, fpus_builtin, 12, 133333333, 4, 33333333, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*4},
-        {"Am5x86/P75+",  CPU_Am486DX, 13, 160000000, 4, 20000000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 4*5},
+        {"Am5x86/P75+",  CPU_Am486DX, fpus_builtin, 13, 160000000, 4, 20000000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 4*5},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Cx486[] =
 {
         /*Cx486/5x86*/
-        {"Cx486S/25",    CPU_Cx486S,   2,  25000000, 1, 25000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
+        {"Cx486S/25",    CPU_Cx486S,  fpus_none,    2,  25000000, 1, 25000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
-        {"Cx486S/33",    CPU_Cx486S,   3,  33333333, 1, 33333333, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"Cx486S/33",    CPU_Cx486S,  fpus_none,    3,  33333333, 1, 33333333, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"Cx486S/40",    CPU_Cx486S,   4,  40000000, 1, 20000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
+        {"Cx486S/40",    CPU_Cx486S,  fpus_none,    4,  40000000, 1, 20000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
-        {"Cx486DX/33",   CPU_Cx486DX,  3,  33333333, 1, 33333333, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
+        {"Cx486DX/33",   CPU_Cx486DX, fpus_builtin, 3,  33333333, 1, 33333333, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
-        {"Cx486DX/40",   CPU_Cx486DX,  4,  40000000, 1, 20000000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
+        {"Cx486DX/40",   CPU_Cx486DX, fpus_builtin, 4,  40000000, 1, 20000000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
-        {"Cx486DX2/50",  CPU_Cx486DX,  5,  50000000, 2, 25000000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
+        {"Cx486DX2/50",  CPU_Cx486DX, fpus_builtin, 5,  50000000, 2, 25000000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 2*3},
-        {"Cx486DX2/66",  CPU_Cx486DX,  6,  66666666, 2, 33333333, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
+        {"Cx486DX2/66",  CPU_Cx486DX, fpus_builtin, 6,  66666666, 2, 33333333, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*4},
-        {"Cx486DX2/80",  CPU_Cx486DX,  8,  80000000, 2, 20000000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14,16,16, 2*5},
+        {"Cx486DX2/80",  CPU_Cx486DX, fpus_builtin, 8,  80000000, 2, 20000000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14,16,16, 2*5},
-        {"Cx486DX4/75",  CPU_Cx486DX,  7,  75000000, 3, 25000000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3},
+        {"Cx486DX4/75",  CPU_Cx486DX, fpus_builtin, 7,  75000000, 3, 25000000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 3*3},
-        {"Cx486DX4/100", CPU_Cx486DX, 10, 100000000, 3, 33333333, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
+        {"Cx486DX4/100", CPU_Cx486DX, fpus_builtin, 10, 100000000, 3, 33333333, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
-        {"Cx5x86/100",   CPU_Cx5x86,  10, 100000000, 3, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
+        {"Cx5x86/100",   CPU_Cx5x86,  fpus_builtin, 10, 100000000, 3, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15,9,9, 3*4},
-        {"Cx5x86/120",   CPU_Cx5x86,  11, 120000000, 3, 20000000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21,9,9, 3*5},
+        {"Cx5x86/120",   CPU_Cx5x86,  fpus_builtin, 11, 120000000, 3, 20000000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21,9,9, 3*5},
-        {"Cx5x86/133",   CPU_Cx5x86,  12, 133333333, 4, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*4},
+        {"Cx5x86/133",   CPU_Cx5x86,  fpus_builtin, 12, 133333333, 4, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*4},
         {"",             -1,        0, 0, 0}
 };
 
- CPU cpus_6x86[] =
+CPU cpus_6x86[] =
- {
+{
-          /*Cyrix 6x86*/
+        /*Cyrix 6x86*/
-          {"6x86-P90",  CPU_Cx6x86, 17,     80000000, 3, 40000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8,8,6,6, 2*5},
+        {"6x86-P90",     CPU_Cx6x86, fpus_builtin, 17,     80000000, 3, 40000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8,8,6,6, 2*5},
-          {"6x86-PR120+",  CPU_Cx6x86, 17,   100000000, 3, 25000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
+        {"6x86-PR120+",  CPU_Cx6x86, fpus_builtin, 17,   100000000, 3, 25000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
-          {"6x86-PR133+",  CPU_Cx6x86, 17,   110000000, 3, 27500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
+        {"6x86-PR133+",  CPU_Cx6x86, fpus_builtin, 17,   110000000, 3, 27500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
-          {"6x86-PR150+",  CPU_Cx6x86, 17,   120000000, 3, 30000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"6x86-PR150+",  CPU_Cx6x86, fpus_builtin, 17,   120000000, 3, 30000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-          {"6x86-PR166+",  CPU_Cx6x86, 17,   133333333, 3, 33333333, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86-PR166+",  CPU_Cx6x86, fpus_builtin, 17,   133333333, 3, 33333333, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-          {"6x86-PR200+",  CPU_Cx6x86, 17,   150000000, 3, 37500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
+        {"6x86-PR200+",  CPU_Cx6x86, fpus_builtin, 17,   150000000, 3, 37500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
 
-          /*Cyrix 6x86L*/
+        /*Cyrix 6x86L*/
-          {"6x86L-PR133+",  CPU_Cx6x86L, 19,   110000000, 3, 27500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
+        {"6x86L-PR133+",  CPU_Cx6x86L, fpus_builtin, 19,   110000000, 3, 27500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
-          {"6x86L-PR150+",  CPU_Cx6x86L, 19,   120000000, 3, 30000000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"6x86L-PR150+",  CPU_Cx6x86L, fpus_builtin, 19,   120000000, 3, 30000000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-          {"6x86L-PR166+",  CPU_Cx6x86L, 19,   133333333, 3, 33333333, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86L-PR166+",  CPU_Cx6x86L, fpus_builtin, 19,   133333333, 3, 33333333, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-          {"6x86L-PR200+",  CPU_Cx6x86L, 19,   150000000, 3, 37500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
+        {"6x86L-PR200+",  CPU_Cx6x86L, fpus_builtin, 19,   150000000, 3, 37500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
 
-          /*Cyrix 6x86MX*/
+        /*Cyrix 6x86MX*/
-          {"6x86MX-PR166",  CPU_Cx6x86MX, 18, 133333333, 3, 33333333, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86MX-PR166",  CPU_Cx6x86MX, fpus_builtin, 18, 133333333, 3, 33333333, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-          {"6x86MX-PR200",  CPU_Cx6x86MX, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"6x86MX-PR200",  CPU_Cx6x86MX, fpus_builtin, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-          {"6x86MX-PR233",  CPU_Cx6x86MX, 18, 188888888, 3, 37500000, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*9)/2},
+        {"6x86MX-PR233",  CPU_Cx6x86MX, fpus_builtin, 18, 188888888, 3, 37500000, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*9)/2},
-          {"6x86MX-PR266",  CPU_Cx6x86MX, 18, 207500000, 3, 41666667, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7, (5*10)/2},
+        {"6x86MX-PR266",  CPU_Cx6x86MX, fpus_builtin, 18, 207500000, 3, 41666667, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7, (5*10)/2},
-          {"6x86MX-PR300",  CPU_Cx6x86MX, 18, 233333333, 3, 33333333, 0x600, 0x600, 0x0454, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,7,7, (7*8)/2},
-          {"6x86MX-PR333",  CPU_Cx6x86MX, 18, 250000000, 3, 41666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 20,20,9,9, 3*10},
-          {"6x86MX-PR366",  CPU_Cx6x86MX, 18, 250000000, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 3*10},
-          {"6x86MX-PR400",  CPU_Cx6x86MX, 18, 285000000, 3, 31666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*11},
-          {"",             -1,        0, 0, 0}
- };
 
+        /*Cyrix M II*/
+        {"M II-200",  CPU_Cx6x86MX, fpus_builtin, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0854, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7,   (5*8)/2},
+        {"M II-233",  CPU_Cx6x86MX, fpus_builtin, 18, 188888888, 3, 37500000, 0x601, 0x601, 0x0854, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7,   (5*9)/2},
+        {"M II-266",  CPU_Cx6x86MX, fpus_builtin, 18, 207500000, 3, 41666667, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7,   (5*10)/2},
+        {"M II-300",  CPU_Cx6x86MX, fpus_builtin, 18, 233333333, 3, 33333333, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,7,7,   (7*8)/2},
+        {"M II-333",  CPU_Cx6x86MX, fpus_builtin, 18, 250000000, 3, 41666667, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 20,20,9,9,   3*10},
 
+        {"",             -1,        0, 0, 0}
+};
+
+CPU cpus_6x86_SS7[] =
+{
+        /*Cyrix 6x86*/
+        {"6x86-P90",  CPU_Cx6x86, fpus_builtin, 17,     80000000, 3, 40000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8,8,6,6, 2*5},
+        {"6x86-PR120+",  CPU_Cx6x86, fpus_builtin, 17,   100000000, 3, 25000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
+        {"6x86-PR133+",  CPU_Cx6x86, fpus_builtin, 17,   110000000, 3, 27500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
+        {"6x86-PR150+",  CPU_Cx6x86, fpus_builtin, 17,   120000000, 3, 30000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"6x86-PR166+",  CPU_Cx6x86, fpus_builtin, 17,   133333333, 3, 33333333, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86-PR200+",  CPU_Cx6x86, fpus_builtin, 17,   150000000, 3, 37500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
+
+        /*Cyrix 6x86L*/
+        {"6x86L-PR133+",  CPU_Cx6x86L, fpus_builtin, 19,   110000000, 3, 27500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*7},
+        {"6x86L-PR150+",  CPU_Cx6x86L, fpus_builtin, 19,   120000000, 3, 30000000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"6x86L-PR166+",  CPU_Cx6x86L, fpus_builtin, 19,   133333333, 3, 33333333, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86L-PR200+",  CPU_Cx6x86L, fpus_builtin, 19,   150000000, 3, 37500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*9},
+
+        /*Cyrix 6x86MX*/
+        {"6x86MX-PR166",  CPU_Cx6x86MX, fpus_builtin, 18, 133333333, 3, 33333333, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"6x86MX-PR200",  CPU_Cx6x86MX, fpus_builtin, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"6x86MX-PR233",  CPU_Cx6x86MX, fpus_builtin, 18, 188888888, 3, 37500000, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*9)/2},
+        {"6x86MX-PR266",  CPU_Cx6x86MX, fpus_builtin, 18, 207500000, 3, 41666667, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7, (5*10)/2},
+
+        /*Cyrix M II*/
+        {"M II-200",  CPU_Cx6x86MX, fpus_builtin, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0854, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7,   (5*8)/2},
+        {"M II-233",  CPU_Cx6x86MX, fpus_builtin, 18, 188888888, 3, 37500000, 0x601, 0x601, 0x0854, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7,   (5*9)/2},
+        {"M II-266",  CPU_Cx6x86MX, fpus_builtin, 18, 207500000, 3, 41666667, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7,   (5*10)/2},
+        {"M II-300",  CPU_Cx6x86MX, fpus_builtin, 18, 233333333, 3, 33333333, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,7,7,   (7*8)/2},
+        {"M II-333",  CPU_Cx6x86MX, fpus_builtin, 18, 250000000, 3, 41666667, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 20,20,9,9,   3*10},
+        {"M II-366",  CPU_Cx6x86MX, fpus_builtin, 18, 250000000, 3, 33333333, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 3*10},
+        {"M II-400",  CPU_Cx6x86MX, fpus_builtin, 18, 285000000, 3, 31666667, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,   3*11},
+        {"M II-433",  CPU_Cx6x86MX, fpus_builtin, 18, 300000000, 3, 33333333, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,   3*12},
+        {"",             -1,        0, 0, 0}
+};
 
 CPU cpus_WinChip[] =
 {
         /*IDT WinChip*/
-        {"WinChip 75",   CPU_WINCHIP,  7,  75000000, 2, 25000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4, (3*6)/2},
+        {"WinChip 75",   CPU_WINCHIP, fpus_builtin,  7,  75000000, 2, 25000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4, (3*6)/2},
-        {"WinChip 90",   CPU_WINCHIP,  9,  90000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4, (3*7)/2},
+        {"WinChip 90",   CPU_WINCHIP, fpus_builtin,  9,  90000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4, (3*7)/2},
-        {"WinChip 100",  CPU_WINCHIP, 10, 100000000, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4, (3*8)/2},
+        {"WinChip 100",  CPU_WINCHIP, fpus_builtin, 10, 100000000, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4, (3*8)/2},
-        {"WinChip 120",  CPU_WINCHIP, 11, 120000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*7},
+        {"WinChip 120",  CPU_WINCHIP, fpus_builtin, 11, 120000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*7},
-        {"WinChip 133",  CPU_WINCHIP, 12, 133333333, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*8},
+        {"WinChip 133",  CPU_WINCHIP, fpus_builtin, 12, 133333333, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 2*8},
-        {"WinChip 150",  CPU_WINCHIP, 13, 150000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"WinChip 150",  CPU_WINCHIP, fpus_builtin, 13, 150000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"WinChip 166",  CPU_WINCHIP, 15, 166666666, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"WinChip 166",  CPU_WINCHIP, fpus_builtin, 15, 166666666, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"WinChip 180",  CPU_WINCHIP, 16, 180000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*7},
+        {"WinChip 180",  CPU_WINCHIP, fpus_builtin, 16, 180000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*7},
-        {"WinChip 200",  CPU_WINCHIP, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
+        {"WinChip 200",  CPU_WINCHIP, fpus_builtin, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
-        {"WinChip 240",  CPU_WINCHIP, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
+        {"WinChip 240",  CPU_WINCHIP, fpus_builtin, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
-        {"WinChip 2/200",  CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
+        {"WinChip 2/200",  CPU_WINCHIP2, fpus_builtin, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
-        {"WinChip 2/240",  CPU_WINCHIP2, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
+        {"WinChip 2/240",  CPU_WINCHIP2, fpus_builtin, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
-        {"WinChip 2A/200",  CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
+        {"WinChip 2A/200",  CPU_WINCHIP2, fpus_builtin, 17, 200000000, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
-        {"WinChip 2A/233",  CPU_WINCHIP2, 17, 233333333, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, (7*8)/2},
+        {"WinChip 2A/233",  CPU_WINCHIP2, fpus_builtin, 17, 233333333, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, (7*8)/2},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_WinChip_SS7[] =
 {
         /*IDT WinChip (Super Socket 7)*/
-        {"WinChip 200",     CPU_WINCHIP,  17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
+        {"WinChip 200",     CPU_WINCHIP,  fpus_builtin, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
-        {"WinChip 225",     CPU_WINCHIP,  17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
+        {"WinChip 225",     CPU_WINCHIP,  fpus_builtin, 17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
-        {"WinChip 240",     CPU_WINCHIP,  17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
+        {"WinChip 240",     CPU_WINCHIP,  fpus_builtin, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
-        {"WinChip 2/200",   CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
+        {"WinChip 2/200",   CPU_WINCHIP2, fpus_builtin, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
-        {"WinChip 2/225",   CPU_WINCHIP2, 17, 225000000, 3, 37500000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
+        {"WinChip 2/225",   CPU_WINCHIP2, fpus_builtin, 17, 225000000, 3, 37500000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
-        {"WinChip 2/240",   CPU_WINCHIP2, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
+        {"WinChip 2/240",   CPU_WINCHIP2, fpus_builtin, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
-        {"WinChip 2/250",   CPU_WINCHIP2, 17, 250000000, 6, 41666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
+        {"WinChip 2/250",   CPU_WINCHIP2, fpus_builtin, 17, 250000000, 6, 41666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
-        {"WinChip 2A/200",  CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 24},
+        {"WinChip 2A/200",  CPU_WINCHIP2, fpus_builtin, 17, 200000000, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 24},
-        {"WinChip 2A/233",  CPU_WINCHIP2, 17, 233333333, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 28},
+        {"WinChip 2A/233",  CPU_WINCHIP2, fpus_builtin, 17, 233333333, 3, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 28},
-        {"WinChip 2A/266",  CPU_WINCHIP2, 17, 233333333, 6, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 28},
+        {"WinChip 2A/266",  CPU_WINCHIP2, fpus_builtin, 17, 233333333, 6, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 28},
-        {"WinChip 2A/300",  CPU_WINCHIP2, 17, 250000000, 6, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
+        {"WinChip 2A/300",  CPU_WINCHIP2, fpus_builtin, 17, 250000000, 6, 33333333, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 30},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Pentium5V[] =
 {
         /*Intel Pentium (5V, socket 4)*/
-        {"Pentium 60",       CPU_PENTIUM,     6,  60000000, 1, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3, 7},
+        {"Pentium 60",            CPU_PENTIUM, fpus_builtin, 6,  60000000, 1, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3, 7},
-        {"Pentium 66",       CPU_PENTIUM,     6,  66666666, 1, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3, 8},
+        {"Pentium 66",            CPU_PENTIUM, fpus_builtin, 6,  66666666, 1, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3, 8},
-        {"Pentium OverDrive 120",CPU_PENTIUM,    14, 120000000, 2, 30000000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"Pentium OverDrive 120", CPU_PENTIUM, fpus_builtin, 14, 120000000, 2, 30000000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-        {"Pentium OverDrive 133",CPU_PENTIUM,    16, 133333333, 2, 33333333, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"Pentium OverDrive 133", CPU_PENTIUM, fpus_builtin, 16, 133333333, 2, 33333333, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_PentiumS5[] =
 {
         /*Intel Pentium (Socket 5)*/
-        {"Pentium 75",       CPU_PENTIUM,     9,  75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4, (3*6)/2},
+        {"Pentium 75",       CPU_PENTIUM,    fpus_builtin,  9,  75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4, (3*6)/2},
-        {"Pentium 90",       CPU_PENTIUM,    12,  90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*7)/2},
+        {"Pentium 90",       CPU_PENTIUM,    fpus_builtin, 12,  90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*7)/2},
-        {"Pentium 100/50",   CPU_PENTIUM,    13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
+        {"Pentium 100/50",   CPU_PENTIUM,    fpus_builtin, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
-        {"Pentium 100/66",   CPU_PENTIUM,    13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*8)/2},
+        {"Pentium 100/66",   CPU_PENTIUM,    fpus_builtin, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*8)/2},
-        {"Pentium 120",      CPU_PENTIUM,    14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"Pentium 120",      CPU_PENTIUM,    fpus_builtin, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-        {"Pentium 133",      CPU_PENTIUM,    16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"Pentium 133",      CPU_PENTIUM,    fpus_builtin, 16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-        {"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
+        {"Pentium OverDrive 125",CPU_PENTIUM,fpus_builtin, 15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
-        {"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium OverDrive 150",CPU_PENTIUM,fpus_builtin, 17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium OverDrive 166",CPU_PENTIUM,fpus_builtin, 17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium OverDrive MMX 125",       CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
+        {"Pentium OverDrive MMX 125",       CPU_PENTIUMMMX, fpus_builtin, 15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
-        {"Pentium OverDrive MMX 150/60",    CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium OverDrive MMX 150/60",    CPU_PENTIUMMMX, fpus_builtin, 17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Pentium OverDrive MMX 166",       CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium OverDrive MMX 166",       CPU_PENTIUMMMX, fpus_builtin, 19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium OverDrive MMX 180",       CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*7},
+        {"Pentium OverDrive MMX 180",       CPU_PENTIUMMMX, fpus_builtin, 20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*7},
-        {"Pentium OverDrive MMX 200",       CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium OverDrive MMX 200",       CPU_PENTIUMMMX, fpus_builtin, 21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_Pentium[] =
 {
         /*Intel Pentium*/
-        {"Pentium 75",       CPU_PENTIUM,     9,  75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4, (3*6)/2},
+        {"Pentium 75",       CPU_PENTIUM,    fpus_builtin,  9,  75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4, (3*6)/2},
-        {"Pentium 90",       CPU_PENTIUM,    12,  90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*7)/2},
+        {"Pentium 90",       CPU_PENTIUM,    fpus_builtin, 12,  90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*7)/2},
-        {"Pentium 100/50",   CPU_PENTIUM,    13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
+        {"Pentium 100/50",   CPU_PENTIUM,    fpus_builtin, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 2*6},
-        {"Pentium 100/66",   CPU_PENTIUM,    13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*8)/2},
+        {"Pentium 100/66",   CPU_PENTIUM,    fpus_builtin, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4, (3*8)/2},
-        {"Pentium 120",      CPU_PENTIUM,    14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"Pentium 120",      CPU_PENTIUM,    fpus_builtin, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-        {"Pentium 133",      CPU_PENTIUM,    16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"Pentium 133",      CPU_PENTIUM,    fpus_builtin, 16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-        {"Pentium 150",      CPU_PENTIUM,    17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium 150",      CPU_PENTIUM,    fpus_builtin, 17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Pentium 166",      CPU_PENTIUM,    19, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium 166",      CPU_PENTIUM,    fpus_builtin, 19, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium 200",      CPU_PENTIUM,    21, 200000000, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium 200",      CPU_PENTIUM,    fpus_builtin, 21, 200000000, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
-        {"Pentium MMX 166",  CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium MMX 166",  CPU_PENTIUMMMX, fpus_builtin, 19, 166666666, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium MMX 200",  CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium MMX 200",  CPU_PENTIUMMMX, fpus_builtin, 21, 200000000, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
-        {"Pentium MMX 233",  CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, (7*8)/2},
+        {"Pentium MMX 233",  CPU_PENTIUMMMX, fpus_builtin, 24, 233333333, 4, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, (7*8)/2},
-        {"Mobile Pentium MMX 120",  CPU_PENTIUMMMX, 14, 120000000, 2, 30000000, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
+        {"Mobile Pentium MMX 120",       CPU_PENTIUMMMX, fpus_builtin, 14, 120000000, 2, 30000000, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*7},
-        {"Mobile Pentium MMX 133",  CPU_PENTIUMMMX, 16, 133333333, 2, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
+        {"Mobile Pentium MMX 133",       CPU_PENTIUMMMX, fpus_builtin, 16, 133333333, 2, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 2*8},
-        {"Mobile Pentium MMX 150",  CPU_PENTIUMMMX, 17, 150000000, 3, 30000000, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Mobile Pentium MMX 150",       CPU_PENTIUMMMX, fpus_builtin, 17, 150000000, 3, 30000000, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Mobile Pentium MMX 166",  CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Mobile Pentium MMX 166",       CPU_PENTIUMMMX, fpus_builtin, 19, 166666666, 3, 33333333, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Mobile Pentium MMX 200",  CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Mobile Pentium MMX 200",       CPU_PENTIUMMMX, fpus_builtin, 21, 200000000, 3, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
-        {"Mobile Pentium MMX 233",  CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, (7*8)/2},
+        {"Mobile Pentium MMX 233",       CPU_PENTIUMMMX, fpus_builtin, 24, 233333333, 4, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, (7*8)/2},
-        {"Mobile Pentium MMX 266",  CPU_PENTIUMMMX, 26, 266666666, 4, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 4*8},
+        {"Mobile Pentium MMX 266",       CPU_PENTIUMMMX, fpus_builtin, 26, 266666666, 4, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 4*8},
-        {"Mobile Pentium MMX 300",  CPU_PENTIUMMMX, 28, 300000000, 5, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, (9*8)/2},
+        {"Mobile Pentium MMX 300",       CPU_PENTIUMMMX, fpus_builtin, 28, 300000000, 5, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, (9*8)/2},
-        {"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
+        {"Pentium OverDrive 125",        CPU_PENTIUM,    fpus_builtin, 15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
-        {"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium OverDrive 150",        CPU_PENTIUM,    fpus_builtin, 17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium OverDrive 166",        CPU_PENTIUM,    fpus_builtin, 17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium OverDrive MMX 125",       CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
+        {"Pentium OverDrive MMX 125",    CPU_PENTIUMMMX, fpus_builtin, 15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, (5*6)/2},
-        {"Pentium OverDrive MMX 150/60",    CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, fpus_builtin, 17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
-        {"Pentium OverDrive MMX 166",       CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium OverDrive MMX 166",    CPU_PENTIUMMMX, fpus_builtin, 19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
-        {"Pentium OverDrive MMX 180",       CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*7},
+        {"Pentium OverDrive MMX 180",    CPU_PENTIUMMMX, fpus_builtin, 20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*7},
-        {"Pentium OverDrive MMX 200",       CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium OverDrive MMX 200",    CPU_PENTIUMMMX, fpus_builtin, 21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
         {"",             -1,        0, 0, 0}
 };
 
 CPU cpus_K6_S7[] =
 {
         /*AMD K6*/
-        {"K6/166",          CPU_K6,    19, 166666666, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
+        {"K6/166",          CPU_K6,    fpus_builtin, 19, 166666666, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
-        {"K6/200",          CPU_K6,    21, 200000000, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
+        {"K6/200",          CPU_K6,    fpus_builtin, 21, 200000000, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
-        {"K6/233",          CPU_K6,    24, 233333333, 4, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+        {"K6/233",          CPU_K6,    fpus_builtin, 24, 233333333, 4, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-        {"K6/266",          CPU_K6,    26, 266666666, 4, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+        {"K6/266",          CPU_K6,    fpus_builtin, 26, 266666666, 4, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-        {"K6/300",          CPU_K6,    28, 300000000, 5, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+        {"K6/300",          CPU_K6,    fpus_builtin, 28, 300000000, 5, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
-        {"K6-2/233",        CPU_K6_2,  24, 233333333, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+        {"K6-2/233",        CPU_K6_2,  fpus_builtin, 24, 233333333, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-        {"K6-2/266",        CPU_K6_2,  26, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+        {"K6-2/266",        CPU_K6_2,  fpus_builtin, 26, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-        {"K6-2/300 AFR-66", CPU_K6_2,  28, 300000000, 5, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+        {"K6-2/300 AFR-66", CPU_K6_2,  fpus_builtin, 28, 300000000, 5, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
         {"",                -1,        0, 0, 0}
 };
 
 CPU cpus_K6_SS7[] =
 {
         /*AMD K6*/
-        {"K6/166",      CPU_K6,    19, 166666666, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
+        {"K6/166",      CPU_K6,    fpus_builtin, 19, 166666666, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
-        {"K6/200",      CPU_K6,    21, 200000000, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
+        {"K6/200",      CPU_K6,    fpus_builtin, 21, 200000000, 3, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
-        {"K6/233",      CPU_K6,    24, 233333333, 4, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+        {"K6/233",      CPU_K6,    fpus_builtin, 24, 233333333, 4, 33333333, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-        {"K6/266",      CPU_K6,    26, 266666666, 4, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+        {"K6/266",      CPU_K6,    fpus_builtin, 26, 266666666, 4, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-        {"K6/300",      CPU_K6,    28, 300000000, 5, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+        {"K6/300",      CPU_K6,    fpus_builtin, 28, 300000000, 5, 33333333, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
-        {"K6-2/233",    CPU_K6_2,  24, 233333333, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
+        {"K6-2/233",    CPU_K6_2,  fpus_builtin, 24, 233333333, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
-        {"K6-2/266",    CPU_K6_2,  26, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
+        {"K6-2/266",    CPU_K6_2,  fpus_builtin, 26, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
-        {"K6-2/300",    CPU_K6_2,  28, 300000000, 5, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
+        {"K6-2/300",    CPU_K6_2,  fpus_builtin, 28, 300000000, 5, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
-        {"K6-2/333",    CPU_K6_2,  28, 333333333, 5, 31666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
+        {"K6-2/333",    CPU_K6_2,  fpus_builtin, 28, 333333333, 5, 31666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
-        {"K6-2/350",    CPU_K6_2,  28, 350000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 42},
+        {"K6-2/350",    CPU_K6_2,  fpus_builtin, 28, 350000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 42},
-        {"K6-2/366",    CPU_K6_2,  28, 366666666, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 44},
+        {"K6-2/366",    CPU_K6_2,  fpus_builtin, 28, 366666666, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 44},
-        {"K6-2/380",    CPU_K6_2,  28, 380000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 46},
+        {"K6-2/380",    CPU_K6_2,  fpus_builtin, 28, 380000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 46},
-        {"K6-2/400",    CPU_K6_2,  28, 400000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
+        {"K6-2/400",    CPU_K6_2,  fpus_builtin, 28, 400000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
-        {"K6-2/450",    CPU_K6_2,  28, 450000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
+        {"K6-2/450",    CPU_K6_2,  fpus_builtin, 28, 450000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
-        {"K6-2/475",    CPU_K6_2,  28, 475000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
+        {"K6-2/475",    CPU_K6_2,  fpus_builtin, 28, 475000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
-        {"K6-2/500",    CPU_K6_2,  28, 500000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
+        {"K6-2/500",    CPU_K6_2,  fpus_builtin, 28, 500000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
-        {"K6-2/533",    CPU_K6_2,  28, 533333333, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 64},
+        {"K6-2/533",    CPU_K6_2,  fpus_builtin, 28, 533333333, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 64},
-        {"K6-2/550",    CPU_K6_2,  28, 550000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 66},
+        {"K6-2/550",    CPU_K6_2,  fpus_builtin, 28, 550000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 66},
-        {"K6-2+/450",   CPU_K6_2P, 28, 450000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
+        {"K6-2+/450",   CPU_K6_2P, fpus_builtin, 28, 450000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
-        {"K6-2+/475",   CPU_K6_2P, 28, 475000000, 5, 31666667, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
+        {"K6-2+/475",   CPU_K6_2P, fpus_builtin, 28, 475000000, 5, 31666667, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
-        {"K6-2+/500",   CPU_K6_2P, 28, 500000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
+        {"K6-2+/500",   CPU_K6_2P, fpus_builtin, 28, 500000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
-        {"K6-2+/533",   CPU_K6_2P, 28, 533333333, 5, 31666667, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 64},
+        {"K6-2+/533",   CPU_K6_2P, fpus_builtin, 28, 533333333, 5, 31666667, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 64},
-        {"K6-2+/550",   CPU_K6_2P, 28, 550000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 66},
+        {"K6-2+/550",   CPU_K6_2P, fpus_builtin, 28, 550000000, 5, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 66},
-        {"K6-III/400",  CPU_K6_3,  28, 400000000, 5, 33333333, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
+        {"K6-III/400",  CPU_K6_3,  fpus_builtin, 28, 400000000, 5, 33333333, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
-        {"K6-III/450",  CPU_K6_3,  28, 450000000, 5, 33333333, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
+        {"K6-III/450",  CPU_K6_3,  fpus_builtin, 28, 450000000, 5, 33333333, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
-        {"K6-III+/400", CPU_K6_3P, 28, 400000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
+        {"K6-III+/400", CPU_K6_3P, fpus_builtin, 28, 400000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 48},
-        {"K6-III+/450", CPU_K6_3P, 28, 450000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
+        {"K6-III+/450", CPU_K6_3P, fpus_builtin, 28, 450000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 54},
-        {"K6-III+/475", CPU_K6_3P, 28, 475000000, 5, 31666667, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
+        {"K6-III+/475", CPU_K6_3P, fpus_builtin, 28, 475000000, 5, 31666667, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 57},
-        {"K6-III+/500", CPU_K6_3P, 28, 500000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
+        {"K6-III+/500", CPU_K6_3P, fpus_builtin, 28, 500000000, 5, 33333333, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 60},
         {"",             -1,        0, 0, 0}
 };
 
+CPU cpus_PentiumPro[] =
+{
+        /*Intel Pentium Pro*/
+        {"Pentium Pro 150", CPU_PENTIUMPRO, fpus_builtin, 17, 150000000, 3, 30000000, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*7)/2},
+        {"Pentium Pro 166", CPU_PENTIUMPRO, fpus_builtin, 19, 166666666, 3, 33333333, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, (5*8)/2},
+        {"Pentium Pro 180", CPU_PENTIUMPRO, fpus_builtin, 20, 180000000, 3, 30000000, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium Pro 200", CPU_PENTIUMPRO, fpus_builtin, 21, 200000000, 3, 33333333, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 3*8},
+        {"Pentium II Overdrive 300", CPU_PENTIUM_2, fpus_builtin, 20, 300000000, 3, 30000000, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 36},
+        {"Pentium II Overdrive 333", CPU_PENTIUM_2, fpus_builtin, 21, 333333333, 3, 33333333, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 40},
+        {"",             -1,        0, 0, 0}
+};
+
+CPU cpus_Slot1_100MHz[] =
+{
+        /*Intel Pentium II*/
+        {"Pentium II/233", CPU_PENTIUM_2, fpus_builtin, 20, 233333333, 3, 33333333, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 28},
+        {"Pentium II/266", CPU_PENTIUM_2, fpus_builtin, 20, 266666666, 3, 33333333, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 32},
+        {"Pentium II/300", CPU_PENTIUM_2, fpus_builtin, 20, 300000000, 3, 33333333, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 36},
+        {"Pentium II/333", CPU_PENTIUM_2, fpus_builtin, 20, 333333333, 3, 33333333, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 40},
+        {"Pentium II/350", CPU_PENTIUM_2, fpus_builtin, 20, 350000000, 3, 33333333, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 42},
+        {"Pentium II/400", CPU_PENTIUM_2, fpus_builtin, 20, 400000000, 3, 33333333, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 48},
+        {"Pentium II/450", CPU_PENTIUM_2, fpus_builtin, 20, 450000000, 3, 33333333, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 54},
+        {"Celeron 266",    CPU_CELERON,   fpus_builtin, 20, 266666666, 3, 33333333, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 32},
+        {"Celeron 300",    CPU_CELERON,   fpus_builtin, 20, 300000000, 3, 33333333, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 36},
+        {"Celeron-A 300",  CPU_CELERON_A, fpus_builtin, 20, 300000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 40},
+        {"Celeron 333",    CPU_CELERON_A, fpus_builtin, 20, 333333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 44},
+        {"Celeron 366",    CPU_CELERON_A, fpus_builtin, 20, 366666666, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 48},
+        {"Celeron 400",    CPU_CELERON_A, fpus_builtin, 20, 400000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 52},
+        {"Celeron 433",    CPU_CELERON_A, fpus_builtin, 20, 433333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 56},
+        {"Celeron 466",    CPU_CELERON_A, fpus_builtin, 20, 466666666, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 60},
+        {"Celeron 500",    CPU_CELERON_A, fpus_builtin, 20, 500000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 64},
+        {"Celeron 533",    CPU_CELERON_A, fpus_builtin, 20, 533333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 68},
+        {"",             -1,        0, 0, 0}
+};
+
+CPU cpus_VIA_100MHz[] =
+{
+        /*VIA Cyrix III*/
+        {"Cyrix III/500", CPU_CYRIX_III, fpus_builtin, 20, 500000000, 3, 33333333, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  64},
+/*Below are disabled as Windows 98 won't boot. This is most likely a limitation of the timer system*/
+/*        {"Cyrix III/550", CPU_CYRIX_III, fpus_builtin, 20, 550000000, 3, 33333333, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  70},
+        {"Cyrix III/600", CPU_CYRIX_III, fpus_builtin, 20, 600000000, 3, 33333333, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  76},
+        {"Cyrix III/650", CPU_CYRIX_III, fpus_builtin, 20, 650000000, 3, 33333333, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  82},
+        {"Cyrix III/700", CPU_CYRIX_III, fpus_builtin, 20, 700000000, 3, 33333333, 0x663, 0x663, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  88},
+        {"C3/750",        CPU_CYRIX_III, fpus_builtin, 20, 750000000, 3, 33333333, 0x673, 0x673, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9,  94},
+        {"C3/800",        CPU_CYRIX_III, fpus_builtin, 20, 800000000, 3, 33333333, 0x673, 0x673, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 100},*/
+        {"",             -1,        0, 0, 0}
+};

src/cs8230.c

@@ -0,0 +1,120 @@
+/*CS8230 CHIPSet consists of :
+        82c301 bus controller
+        82c302 page/interleave memory controller
+        82a303 high address buffer
+        82a304 low address buffer
+        82b305 data buffer
+        82a306 control buffer*/
+#include "ibm.h"
+#include "cs8230.h"
+#include "io.h"
+#include "mem.h"
+
+static struct
+{
+        int idx;
+        uint8_t regs[256];
+} cs8230;
+
+static void shadow_control(uint32_t addr, uint32_t size, int state)
+{
+//        pclog("shadow_control: addr=%08x size=%04x state=%02x\n", addr, size, state);
+        switch (state)
+        {
+                case 0x00:
+                mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                break;
+                case 0x01:
+                mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
+                break;
+                case 0x10:
+                mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
+                break;
+                case 0x11:
+                mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                break;
+        }
+        flushmmucache_nopc();
+}
+
+static void rethink_shadow_mappings(void)
+{
+        int c;
+        
+        for (c = 0; c < 4*8; c++) /*Addresses 40000-bffff in 16k blocks*/
+        {
+                if (cs8230.regs[0xa + (c >> 3)] & (1 << (c & 7)))
+                        mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /*IO channel*/
+                else
+                        mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/
+        }
+        for (c = 0; c < 2*8; c++) /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/
+        {
+                if (cs8230.regs[0xe + (c >> 3)] & (1 << (c & 7)))
+                        mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /*IO channel*/
+                else
+                        shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230.regs[9] >> (3-(c >> 2))) & 0x11);
+        }
+}
+
+static uint8_t cs8230_read(uint16_t port, void *p)
+{
+        uint8_t ret = 0xff;
+        
+        if (port & 1)
+        {
+                switch (cs8230.idx)
+                {
+                        case 0x04: /*82C301 ID/version*/
+                        ret = cs8230.regs[cs8230.idx] & ~0xe3;
+                        break;
+
+                        case 0x08: /*82C302 ID/Version*/
+                        ret = cs8230.regs[cs8230.idx] & ~0xe0;
+                        break;
+                        
+                        case 0x05: case 0x06: /*82C301 registers*/
+                        case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/
+                        case 0x0d: case 0x0e: case 0x0f: 
+                        case 0x10: case 0x11: case 0x12: case 0x13:
+                        case 0x28: case 0x29: case 0x2a:
+                        ret = cs8230.regs[cs8230.idx];
+                        break;
+                }
+        }
+        
+        return ret;
+}
+
+static void cs8230_write(uint16_t port, uint8_t val, void *p)
+{
+        if (!(port & 1))
+                cs8230.idx = val;
+        else
+        {
+//                pclog("cs8230_write: reg=%02x val=%02x\n", cs8230.idx, val);
+                cs8230.regs[cs8230.idx] = val;
+                switch (cs8230.idx)
+                {
+                        case 0x09: /*RAM/ROM Configuration in boot area*/
+                        case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/
+                        rethink_shadow_mappings();
+                        break;
+                }
+        }
+}
+
+void cs8230_init(void)
+{
+        memset(&cs8230, 0, sizeof(cs8230));
+        
+        io_sethandler(0x0022, 0x0002,
+                        cs8230_read, NULL, NULL,
+                        cs8230_write, NULL, NULL,
+                        NULL);
+	if (mem_size > 768)
+        {
+                mem_mapping_set_addr(&ram_mid_mapping, 0xa0000, mem_size > 1024 ? 0x60000 : 0x20000 + (mem_size - 768) * 1024);
+                mem_mapping_set_exec(&ram_mid_mapping, ram + 0xa0000);
+        }
+}

src/cs8230.h

@@ -0,0 +1 @@
+void cs8230_init(void);

src/disc.c

@@ -143,7 +143,7 @@ void disc_poll()
         {
                 disc_notfound--;
                 if (!disc_notfound)
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_AM_NOT_FOUND);
         }
 }
 

src/disc.h

@@ -37,7 +37,7 @@ void fdc_callback();
 int  fdc_data(uint8_t dat);
 void fdc_spindown();
 void fdc_finishread();
-void fdc_notfound();
+void fdc_notfound(int reason);
 void fdc_datacrcerror();
 void fdc_headercrcerror();
 void fdc_writeprotect();

src/disc_fdi.c

@@ -3,6 +3,7 @@
 #include "ibm.h"
 #include "disc.h"
 #include "disc_fdi.h"
+#include "fdc.h"
 #include "fdi2raw.h"
 
 static struct
@@ -314,7 +315,7 @@ void fdi_poll()
                 if (fdi_revs == 3)
                 {
 //                        pclog("Not found!\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_NOT_FOUND);
                         fdi_inread = fdi_inreadaddr = 0;
                         return;
                 }

src/disc_sector.c

@@ -47,6 +47,8 @@ static uint8_t disc_sector_fill;
 static int cur_sector, cur_byte;
 static int index_count;
 
+static int disc_sector_status;
+
 void disc_sector_reset(int drive, int side)
 {
         disc_sector_count[drive][side] = 0;
@@ -90,6 +92,8 @@ void disc_sector_readsector(int drive, int sector, int track, int side, int rate
         disc_sector_sector = sector;
 	disc_sector_n = sector_size;
         index_count = 0;
+        
+        disc_sector_status = FDC_STATUS_AM_NOT_FOUND;
 }
 
 void disc_sector_writesector(int drive, int sector, int track, int side, int rate, int sector_size)
@@ -103,6 +107,8 @@ void disc_sector_writesector(int drive, int sector, int track, int side, int rat
         disc_sector_sector = sector;
 	disc_sector_n = sector_size;
         index_count = 0;
+
+        disc_sector_status = FDC_STATUS_AM_NOT_FOUND;
 }
 
 void disc_sector_readaddress(int drive, int track, int side, int rate)
@@ -114,6 +120,8 @@ void disc_sector_readaddress(int drive, int track, int side, int rate)
         disc_sector_side  = side;
         disc_sector_drive = drive;
         index_count = 0;
+
+        disc_sector_status = FDC_STATUS_AM_NOT_FOUND;
 }
 
 void disc_sector_format(int drive, int track, int side, int rate, uint8_t fill)
@@ -179,7 +187,7 @@ void disc_sector_poll()
                 if (index_count > 1)
                 {
 //                        pclog("Find sector not found\n");
-                        fdc_notfound();
+                        fdc_notfound(disc_sector_status);
                         disc_sector_state = STATE_IDLE;
                         break;
                 }
@@ -187,10 +195,11 @@ void disc_sector_poll()
                     disc_sector_side != s->h,
                     disc_sector_sector != s->r,
                     fdc_get_bitcell_period() != get_bitcell_period());*/
-                if (cur_byte || disc_sector_track != s->c ||
+                if (!cur_byte && fdc_get_bitcell_period() == get_bitcell_period() &&
-                    disc_sector_side != s->h ||
+                    fdd_can_read_medium(disc_sector_drive ^ fdd_swap))
-                    disc_sector_sector != s->r ||
+                        disc_sector_status = FDC_STATUS_NOT_FOUND; /*Disc readable, assume address marker found*/
-		    disc_sector_n != s->n ||
+                    
+                if (cur_byte ||
                     fdc_get_bitcell_period() != get_bitcell_period() ||
 		    !fdd_can_read_medium(disc_sector_drive ^ fdd_swap) ||
                     disc_intersector_delay)
@@ -198,6 +207,16 @@ void disc_sector_poll()
                         advance_byte();
                         break;
                 }
+                if (disc_sector_track != s->c ||
+                    disc_sector_side != s->h ||
+                    disc_sector_sector != s->r ||
+		    disc_sector_n != s->n)
+                {
+                        if (disc_sector_track != s->c)
+                                disc_sector_status = (disc_sector_track == 0xff) ? FDC_STATUS_BAD_CYLINDER : FDC_STATUS_WRONG_CYLINDER;
+                        advance_byte();
+                        break;
+                }
                 disc_sector_state = STATE_READ_SECTOR;
                 case STATE_READ_SECTOR:
 //                pclog("STATE_READ_SECTOR: cur_byte=%i %i\n", cur_byte, disc_intersector_delay);
@@ -218,10 +237,14 @@ void disc_sector_poll()
 		if (!(fdd_can_read_medium(disc_sector_drive ^ fdd_swap)))
 		{
 //			pclog("Medium is of a density not supported by the drive\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_AM_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
 		}
+                if (!cur_byte && fdc_get_bitcell_period() == get_bitcell_period() &&
+                    fdd_can_read_medium(disc_sector_drive ^ fdd_swap))
+                        disc_sector_status = FDC_STATUS_NOT_FOUND; /*Disc readable, assume address marker found*/
+
                 if (cur_byte || !index_count || fdc_get_bitcell_period() != get_bitcell_period() ||
                     disc_intersector_delay)
                 {
@@ -244,14 +267,14 @@ void disc_sector_poll()
 		if (!(fdd_can_read_medium(disc_sector_drive ^ fdd_swap)))
 		{
 //			pclog("Medium is of a density not supported by the drive\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_AM_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
 		}
                 if (index_count)
                 {
 //                        pclog("Find next sector hit end of track\n");
-                        fdc_notfound();
+                        fdc_notfound(disc_sector_status);
                         disc_sector_state = STATE_IDLE;
                         break;
                 }
@@ -277,10 +300,15 @@ void disc_sector_poll()
 		if (!(fdd_can_read_medium(disc_sector_drive ^ fdd_swap)))
 		{
 //			pclog("Medium is of a density not supported by the drive\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_AM_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
 		}
+
+                if (!cur_byte && fdc_get_bitcell_period() == get_bitcell_period() &&
+                    fdd_can_read_medium(disc_sector_drive ^ fdd_swap))
+                        disc_sector_status = FDC_STATUS_NOT_FOUND; /*Disc readable, assume address marker found*/
+
                 if (writeprot[disc_sector_drive])
                 {
                         fdc_writeprotect();
@@ -290,20 +318,27 @@ void disc_sector_poll()
                 if (index_count > 1)
                 {
 //                        pclog("Write find sector not found\n");
-                        fdc_notfound();
+                        fdc_notfound(disc_sector_status);
                         disc_sector_state = STATE_IDLE;
                         break;
                 }
-                if (cur_byte || disc_sector_track != s->c ||
+                if (cur_byte ||
-                    disc_sector_side != s->h ||
-                    disc_sector_sector != s->r ||
-		    disc_sector_n != s->n ||
                     fdc_get_bitcell_period() != get_bitcell_period() ||
                     disc_intersector_delay)
                 {
                         advance_byte();
                         break;
                 }
+                if (disc_sector_track != s->c ||
+                    disc_sector_side != s->h ||
+                    disc_sector_sector != s->r ||
+		    disc_sector_n != s->n)
+                {
+                        if (disc_sector_track != s->c)
+                                disc_sector_status = (disc_sector_track == 0xff) ? FDC_STATUS_BAD_CYLINDER : FDC_STATUS_WRONG_CYLINDER;
+                        advance_byte();
+                        break;
+                }
                 disc_sector_state = STATE_WRITE_SECTOR;
                 case STATE_WRITE_SECTOR:
                 data = fdc_getdata(cur_byte == ((128 << s->n) - 1));
@@ -323,14 +358,19 @@ void disc_sector_poll()
 		if (!(fdd_can_read_medium(disc_sector_drive ^ fdd_swap)))
 		{
 //			pclog("Medium is of a density not supported by the drive\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_AM_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
 		}
+
+                if (!cur_byte && fdc_get_bitcell_period() == get_bitcell_period() &&
+                    fdd_can_read_medium(disc_sector_drive ^ fdd_swap))
+                        disc_sector_status = FDC_STATUS_NOT_FOUND; /*Disc readable, assume address marker found*/
+
                 if (index_count)
                 {
 //                        pclog("Find next sector hit end of track\n");
-                        fdc_notfound();
+                        fdc_notfound(disc_sector_status);
                         disc_sector_state = STATE_IDLE;
                         break;
                 }
@@ -343,6 +383,7 @@ void disc_sector_poll()
                 disc_sector_state = STATE_READ_ADDRESS;
                 case STATE_READ_ADDRESS:
                 fdc_sectorid(s->c, s->h, s->r, s->n, 0, 0);
+                advance_byte();
                 disc_sector_state = STATE_IDLE;
                 break;
                 
@@ -362,13 +403,13 @@ void disc_sector_poll()
 		if (!(fdd_can_read_medium(disc_sector_drive ^ fdd_swap)))
 		{
 //			pclog("Medium is of a density not supported by the drive\n");
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
 		}
                 if (fdc_get_bitcell_period() != get_bitcell_period())
                 {
-                        fdc_notfound();
+                        fdc_notfound(FDC_STATUS_NOT_FOUND);
                         disc_sector_state = STATE_IDLE;
                         break;
                 }

src/f82c710_upc.c

@@ -0,0 +1,529 @@
+/*
+ * Chips & Technologies F82C710 Universal Peripheral Controller (UPC)
+ *
+ * Copyright (c) 2020 Eluan Costa Miranda <eluancm@gmail.com> All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * =============================================================================
+ *
+ * This SuperIO chip is commonly seem paired with the Single-chip AT (SCAT)
+ * chip. Only the functionality needed for the Hyundai Super-286TR BIOS is
+ * implented for now.
+ *
+ * One of the goals of this chip was getting rid of jumpers and have everything
+ * configured by software, but there is no configuration for serial and
+ * parallel IRQs. Because of that, motherboards still supply jumpers for these
+ * two signals.
+ *
+ */
+
+#include "ibm.h"
+
+#include "fdc.h"
+#include "ide.h"
+#include "io.h"
+#include "lpt.h"
+#include "serial.h"
+#include "x86.h"
+#include "keyboard_at.h"
+#include "pic.h"
+
+#define UPC_MOUSE_DEV_IDLE     0x01      /* bit 0, Device Idle */
+#define UPC_MOUSE_RX_FULL      0x02      /* bit 1, Device Char received */
+#define UPC_MOUSE_TX_IDLE      0x04      /* bit 2, Device XMIT Idle */
+#define UPC_MOUSE_RESET        0x08      /* bit 3, Device Reset */
+#define UPC_MOUSE_INTS_ON      0x10      /* bit 4, Device Interrupt On */
+#define UPC_MOUSE_ERROR_FLAG   0x20      /* bit 5, Device Error */
+#define UPC_MOUSE_CLEAR        0x40      /* bit 6, Device Clear */
+#define UPC_MOUSE_ENABLE       0x80      /* bit 7, Device Enable */
+
+typedef struct upc_t
+{
+        int configuration_state; // state of algorithm to enter configuration mode
+        int configuration_mode;
+        uint8_t next_value;     // next expected value of configuration algorithm
+        uint16_t cri_addr; // cri = configuration index register, addr is even
+        uint16_t cap_addr; // cap = configuration access port, addr is odd and is cri_addr + 1
+        uint8_t cri; // currently indexed register
+
+        // these regs are not affected by reset
+        uint8_t regs[15]; // there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode
+
+        int serial_irq;
+        int parallel_irq; // TODO: currently not implemented in PCem
+
+        int mouse_irq;
+        uint16_t mdata_addr;    // Address of PS/2 data register
+        uint16_t mstat_addr;    // Address of PS/2 status register
+        uint8_t mouse_status;   // Mouse interface status register
+        uint8_t mouse_data;     // Mouse interface data register
+        void (*mouse_write)(uint8_t val, void *p);
+        void *mouse_p;
+        pc_timer_t mouse_delay_timer;
+} upc_t;
+
+static upc_t upc;
+
+uint8_t upc_config_read(uint16_t port, void *priv);
+void upc_config_write(uint16_t port, uint8_t val, void *priv);
+
+void upc_mouse_disable(upc_t *upc);
+void upc_mouse_enable(upc_t *upc);
+uint8_t upc_mouse_read(uint16_t port, void *priv);
+void upc_mouse_write(uint16_t port, uint8_t val, void *priv);
+void upc_mouse_poll(void *priv);
+
+void upc_update_config(upc_t *upc)
+{
+        switch(upc->cri)
+        {
+                case 0:
+                if (upc->regs[0] & 0x4)
+                {
+                        serial1_set(upc->regs[4] * 4, upc->serial_irq);
+                        pclog("UPC: UART at %04X, irq %d\n", upc->regs[4] * 4, upc->serial_irq);
+                }
+                else
+                {
+                        serial1_remove();
+                        pclog("UPC: UART disabled\n");
+                }
+                if (upc->regs[0] & 0x8)
+                {
+                        lpt1_init(upc->regs[6] * 4);
+                        pclog("UPC: PARALLEL at %04X, irq %d\n", upc->regs[6] * 4, upc->parallel_irq);
+                }
+                else
+                {
+                        lpt1_remove();
+                        pclog("UPC: PARALLEL disabled\n");
+                }
+                if ((upc->regs[0] & 0x60) != 0)
+                        pclog("UPC: Oscillator control not implemented!\n");
+                break;
+
+                case 1:
+                if ((upc->regs[1] & 0x80) != 0)
+                        pclog("UPC: Restricted serial reset not implemented!\n");
+                if ((upc->regs[1] & 0x80) != 0)
+                        pclog("UPC: Restricted serial reset not implemented!\n");
+                if ((upc->regs[1] & 0x40) != 0)
+                        pclog("UPC: Bidirectional parallel port support not implemented!\n");
+                if ((upc->regs[1] & 0x38) != 0)
+                        pclog("UPC: UART force CTS, DSR, DCD not implemented!\n");
+                break;
+
+                case 2:
+                if ((upc->regs[2] & 0x70) != 0)
+                        pclog("UPC: UART clock control not implemented!\n");
+                break;
+
+                case 9:
+                if (upc->regs[9] == 0xb0)
+                        pclog("UPC: GPCS not implemented! (at default address: %04X)\n", upc->regs[9] * 4);
+                else if (upc->regs[9] != 0)
+                        pclog("UPC: GPCS not implemented! (at address: %04X)\n", upc->regs[9] * 4);
+                break;
+
+                case 12:
+                /* Adding the IDE and floppy controllers when they are already present causes problems.*/
+                /* FIX: remove floppy and IDE controllers before adding them again if needed. */
+                fdc_remove();
+                ide_pri_disable();
+                if ((upc->regs[12] & 0x40) != 0)
+                {
+                        pclog("UPC: IDE XT mode not implemented!\n");
+                }
+                else
+                {
+                        if (upc->regs[12] & 0x80)
+                        {
+                                ide_pri_enable();
+                                pclog("UPC: AT IDE enabled\n");
+                        }
+                        else
+                        {
+                                pclog("UPC: AT IDE disabled\n");
+                        }
+                }
+
+                if (upc->regs[12] & 0x20)
+                {
+                        fdc_add();
+                        pclog("UPC: FDC enabled\n");
+                }
+                else
+                {
+                        pclog("UPC: FDC disabled\n");
+                }
+
+                if ((upc->regs[12] & 0x10) != 0)
+                        pclog("UPC: FDC power down mode not implemented!\n");
+                if ((upc->regs[12] & 0x0C) != 0)
+                        pclog("UPC: RTCCS not implemented!\n");
+                if ((upc->regs[12] & 0x01) != 0)
+                        pclog("UPC: PS/2 mouse port power down not implemented!\n");
+                break;
+
+                case 13:
+                if (upc->regs[13] != 0)
+                {
+                        upc->mdata_addr = upc->regs[13] * 4;
+                        upc->mstat_addr = upc->mdata_addr + 1;
+                        pclog("UPC: PS/2 mouse port at %04X, irq %d\n", upc->mdata_addr, upc->mouse_irq);
+                        upc_mouse_enable(upc);
+                }
+                else
+                {
+                        pclog("UPC: PS/2 mouse port disabled\n");
+                        upc_mouse_disable(upc);
+                }
+
+                case 14:
+                if (upc->regs[14] != 0)
+                        pclog("UPC: Test mode not implemented!\n");
+                break;
+        }
+}
+
+uint8_t upc_config_read(uint16_t port, void *priv)
+{
+        upc_t *upc = (upc_t *)priv;
+        uint8_t temp = 0xff;
+
+        if (upc->configuration_mode)
+        {
+                if (port == upc->cri_addr)
+                {
+                        temp = upc->cri;
+                }
+                else if (port == upc->cap_addr)
+                {
+                        if (upc->cri == 0xf)
+                                temp = upc->cri_addr / 4;
+                        else
+                                temp = upc->regs[upc->cri];
+                }
+        }
+
+//        pclog("UPC READ : %04X, %02X\n", port, temp);
+        return temp;
+}
+
+void upc_config_write(uint16_t port, uint8_t val, void *priv)
+{
+        upc_t *upc = (upc_t *)priv;
+        int configuration_state_event = 0;
+
+//        pclog("UPC WRITE: %04X, %02X\n", port, val);
+
+        switch(port)
+        {
+                case 0x2fa:
+                        /* Execute configuration step 1 for any value except 9, ff or 36 */
+                        if (upc->configuration_state == 0)
+                        {
+                                configuration_state_event = 1;
+                                /* next value should be the 1's complement of the current one */
+                                upc->next_value = 0xff - val;
+                        }
+                        else if (upc->configuration_state == 4)
+                        {
+                                uint8_t addr_verify = upc->cri_addr / 4;
+                                addr_verify += val;
+                                if (addr_verify == 0xff)
+                                {
+                                        upc->configuration_mode = 1;
+                                        // TODO: is the value of cri reset here or when exiting configuration mode?
+                                        io_sethandler(upc->cri_addr, 0x0002, upc_config_read, NULL, NULL, upc_config_write, NULL, NULL, upc);
+                                        pclog("UPC: in configuration mode at %04X\n", upc->cri_addr);
+                                }
+                                else
+                                {
+                                        upc->configuration_mode = 0;
+                                        pclog("UPC: configuration mode failed (sum = %02X)\n", addr_verify);
+                                }
+                        }
+                        break;
+                case 0x3fa:
+                        /* go to configuration step 2 if value is the expected one */
+                        if (upc->configuration_state == 1 && val == upc->next_value)
+                                configuration_state_event = 1;
+                        else if (upc->configuration_state == 2 && val == 0x36)
+                                configuration_state_event = 1;
+                        else if (upc->configuration_state == 3)
+                        {
+                                upc->cri_addr = val * 4;
+                                upc->cap_addr = upc->cri_addr + 1;
+                                configuration_state_event = 1;
+                        }
+                        break;
+                default:
+                        break;
+        }
+        if (upc->configuration_mode)
+        {
+                if (port == upc->cri_addr)
+                {
+                        upc->cri = val & 0xf;
+
+                }
+                else if (port == upc->cap_addr)
+                {
+                        if (upc->cri == 0xf)
+                        {
+                                pclog("UPC: exiting configuration mode\n");
+                                upc->configuration_mode = 0;
+                                io_removehandler(upc->cri_addr, 0x0002, upc_config_read, NULL, NULL, upc_config_write, NULL, NULL, upc);
+                        }
+                        else
+                        {
+                                upc->regs[upc->cri] = val;
+                                /* configuration should be updated at each register write, otherwise PC5086 do not detect ports correctly */
+                                upc_update_config(upc);
+                        }
+                }
+        }
+
+        // TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly?
+        if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
+                upc->configuration_state++;
+        else
+                upc->configuration_state = 0;
+}
+
+static void *upc_init()
+{
+        pclog("UPC INIT\n");
+
+        /* Disable all peripherals. upc_update_config will enable configured peripherals */
+        serial1_remove();
+        serial2_remove();
+        lpt1_remove();
+        lpt2_remove();
+        fdc_remove();
+        ide_pri_disable();
+        ide_sec_disable();
+        serial1_set_has_fifo(0);
+
+        memset(&upc, 0, sizeof(upc));
+
+        upc.serial_irq = device_get_config_int("serial_irq");
+        upc.parallel_irq = device_get_config_int("parallel_irq");
+
+        // because of these addresses, serial ports must be 16450 without fifos
+        io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, upc_config_write, NULL, NULL, &upc);
+        io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, upc_config_write, NULL, NULL, &upc);
+
+        upc.regs[0] = 0x0c;
+        upc.regs[1] = 0x00;
+        upc.regs[2] = 0x00;
+        upc.regs[3] = 0x00;
+        upc.regs[4] = 0xfe;
+        upc.regs[5] = 0x00;
+        upc.regs[6] = 0x9e;
+        upc.regs[7] = 0x00;
+        upc.regs[8] = 0x00;
+        upc.regs[9] = 0xb0;
+        upc.regs[10] = 0x00;
+        upc.regs[11] = 0x00;
+        upc.regs[12] = 0xa0;
+        upc.regs[13] = 0x00;
+        upc.regs[14] = 0x00;
+
+        for (upc.cri = 0; upc.cri < 15; upc.cri++)
+                upc_update_config(&upc);
+        upc.cri = 0;
+
+        /********************* Initialize mouse interface ********************/
+        if(romset == ROM_PC5086)    /* IRQ is 2 for PC5086 and 12 for others */
+                upc.mouse_irq = 2;
+        else
+                upc.mouse_irq = 12;
+        upc.mdata_addr = upc.regs[13] * 4;
+        upc.mstat_addr = upc.mdata_addr + 1;
+        upc.mouse_status = UPC_MOUSE_DEV_IDLE | UPC_MOUSE_TX_IDLE;
+        upc.mouse_data = 0xff;
+        /* Set timer for mouse polling */
+        timer_add(&upc.mouse_delay_timer, upc_mouse_poll, &upc, 1);
+
+        return &upc;
+}
+
+static device_config_t upc_config[] =
+{
+        {
+                .name = "serial_irq",
+                .description = "Serial Port IRQ",
+                .type = CONFIG_SELECTION,
+                .selection =
+                {
+                        {
+                                .description = "IRQ 4 (for address 0x3F8/COM1)",
+                                .value = 4
+                        },
+                        {
+                                .description = "IRQ 3 (for address 0x2F8/COM2)",
+                                .value = 3
+                        },
+                        {
+                                .description = "Disabled",
+                                .value = 0 // TODO: see if this breaks PCem's PIC
+                        }
+                },
+                .default_int = 4
+        },
+        {
+                .name = "parallel_irq",
+                .description = "Parallel Port IRQ",
+                .type = CONFIG_SELECTION,
+                .selection =
+                {
+                        {
+                                .description = "IRQ 7 (for address 0x378/LPTB)",
+                                .value = 7
+                        },
+                        {
+                                .description = "IRQ 5 (for address 0x278/LPTC)",
+                                .value = 5
+                        },
+                        {
+                                .description = "Disabled",
+                                .value = 0 // TODO: see if this breaks PCem's PIC
+                        }
+                },
+                .default_int = 7
+        },
+        // For the Hyundai Super-286TR, the only other jumper is the Color/Mono one and it's handled by the at keyboard controller code.
+        {
+                .type = -1
+        }
+};
+
+
+device_t f82c710_upc_device =
+{
+        "F82C710 UPC",
+        0,
+        upc_init,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        upc_config
+};
+
+/****************** PS/2 mouse port *********************/
+uint8_t upc_mouse_read(uint16_t port, void *priv)
+{
+        upc_t *upc = (upc_t *)priv;
+        uint8_t temp = 0xff;
+        if (port == upc->mstat_addr)
+        {
+                temp = upc->mouse_status;
+        }
+
+        if (port == upc->mdata_addr && (upc->mouse_status & UPC_MOUSE_RX_FULL))
+        {
+                temp = upc->mouse_data;
+                upc->mouse_data = 0xff;
+                upc->mouse_status &= ~UPC_MOUSE_RX_FULL;
+                upc->mouse_status |= UPC_MOUSE_DEV_IDLE;
+                // pclog("%04X:%04X UPC mouse READ: %04X, %02X\n", CS, cpu_state.pc, port, temp);
+        }
+
+        // pclog("%04X:%04X UPC mouse READ: %04X, %02X\n", CS, cpu_state.pc, port, temp);
+        return temp;
+}
+
+void upc_mouse_write(uint16_t port, uint8_t val, void *priv)
+{
+        // pclog("%04X:%04X UPC mouse WRITE: %04X, %02X\n", CS, cpu_state.pc, port, val);
+
+        upc_t *upc = (upc_t *)priv;
+        if (port == upc->mstat_addr)
+        {
+                /* write status bits
+                 * DEV_IDLE, TX_IDLE, RX_FULL and ERROR_FLAG bits are unchanged
+                 */
+                upc->mouse_status = (val & 0xD8) | (upc->mouse_status & 0x27);
+                if (upc->mouse_status & UPC_MOUSE_ENABLE)
+                        mouse_scan = 1;
+                else
+                        mouse_scan = 0;
+                if (upc->mouse_status & (UPC_MOUSE_CLEAR | UPC_MOUSE_RESET))
+                {
+                        /* if CLEAR or RESET bit is set, clear mouse queue */
+                        mouse_queue_start = mouse_queue_end;
+                        upc->mouse_status &= ~UPC_MOUSE_RX_FULL;
+                        upc->mouse_status |= UPC_MOUSE_DEV_IDLE | UPC_MOUSE_TX_IDLE;
+                        mouse_scan = 0;
+                }
+        }
+
+        if (port == upc->mdata_addr)
+        {
+                if ((upc->mouse_status & UPC_MOUSE_TX_IDLE) && (upc->mouse_status & UPC_MOUSE_ENABLE))
+                {
+                        upc->mouse_data = val;
+                        if (upc->mouse_write)
+                                upc->mouse_write(val, upc->mouse_p);
+                }
+        }
+}
+
+void upc_mouse_disable(upc_t *upc)
+{
+        io_removehandler(upc->mdata_addr, 0x0002, upc_mouse_read, NULL, NULL, upc_mouse_write, NULL, NULL, upc);
+}
+
+void upc_mouse_enable(upc_t *upc)
+{
+        io_sethandler(upc->mdata_addr, 0x0002, upc_mouse_read, NULL, NULL, upc_mouse_write, NULL, NULL, upc);
+}
+
+void upc_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p)
+{
+        upc.mouse_write = mouse_write;
+        upc.mouse_p = p;
+}
+
+void upc_mouse_poll(void *priv)
+{
+        upc_t *upc = (upc_t *)priv;
+        timer_advance_u64(&upc->mouse_delay_timer, (1000 * TIMER_USEC));
+
+        /* check if there is something in the mouse queue */
+        if (mouse_queue_start != mouse_queue_end)
+        {
+                // pclog("Mouse timer. %d %d %02X %02X\n", mouse_queue_start, mouse_queue_end, upc->mouse_status, upc->mouse_data);
+	        if ((upc->mouse_status & UPC_MOUSE_ENABLE) && !(upc->mouse_status & UPC_MOUSE_RX_FULL))
+                {
+	                upc->mouse_data = mouse_queue[mouse_queue_start];
+                        mouse_queue_start = (mouse_queue_start + 1) & 0xf;
+                        /* update mouse status */
+                        upc->mouse_status |= UPC_MOUSE_RX_FULL;
+                        upc->mouse_status &= ~(UPC_MOUSE_DEV_IDLE);
+                        // pclog("Reading %02X from the mouse queue at %i %i. New status is %02X\n", upc->mouse_data, mouse_queue_start, mouse_queue_end, upc->mouse_status);
+                        /* raise IRQ if enabled */
+                        if (upc->mouse_status & UPC_MOUSE_INTS_ON)
+                        {
+                                picint(1 << upc->mouse_irq);
+                                // pclog("upc_mouse : take IRQ %d\n", upc->mouse_irq);
+                        }
+                }
+        }
+}

src/f82c710_upc.h

@@ -0,0 +1,6 @@
+#include "device.h"
+
+void upc_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p);
+
+extern device_t f82c710_upc_device;
+

src/fdc.c

@@ -5,12 +5,23 @@
 #include "disc.h"
 #include "disc_sector.h"
 #include "dma.h"
+#include "fdc.h"
 #include "fdd.h"
 #include "io.h"
 #include "pic.h"
 #include "timer.h"
 #include "x86.h"
 
+#define ST1_DE (1 << 5)
+#define ST1_ND (1 << 2)
+#define ST1_NW (1 << 1)
+#define ST1_MA (1 << 0)
+
+#define ST2_DD (1 << 5)
+#define ST2_WC (1 << 4) /*Wrong cylinder*/
+#define ST2_BC (1 << 1) /*Bad cylinder*/
+#define ST2_MD (1 << 0)
+
 static int fdc_reset_stat = 0;
 /*FDC*/
 typedef struct FDC
@@ -34,7 +45,6 @@ typedef struct FDC
         int format_state;
         int tc;
         int written;
-        int in_seek_mt;
 
         int pcjr, ps1;
         
@@ -87,7 +97,7 @@ void fdc_reset()
         fdc.lock = 0;
         fdc.head = 0;
         fdc.abort = 0;
-        if (!AT && romset != ROM_XI8088)
+        if (!AT && romset != ROM_XI8088 && romset != ROM_PC5086)
         {
                 fdc.rate = 2;
                 // fdc_update_rate();
@@ -349,11 +359,6 @@ void fdc_write(uint16_t addr, uint8_t val, void *priv)
                 }
                 else
                 {
-                        if (val&4)
-                        {
-                                fdc.stat=0x80;
-                                fdc.pnum=fdc.ptot=0;
-                        }
                         if ((val&4) && !(fdc.dor&4))
                         {
 				timer_set_delay_u64(&fdc.timer, 8 * TIMER_USEC);
@@ -404,11 +409,10 @@ void fdc_write(uint16_t addr, uint8_t val, void *priv)
                 {
                         fdc.tc = 0;
                         fdc.data_ready = 0;
-                        fdc.in_seek_mt = 0;
 
                         fdc.command=val;
 //                        pclog("Starting FDC command %02X\n",fdc.command);
-                        switch (fdc.command&0x1F)
+                        switch (fdc.command)
                         {
 				case 1: /*Mode*/
 				if (!fdc.is_nsc)  goto bad_command;
@@ -419,23 +423,23 @@ void fdc_write(uint16_t addr, uint8_t val, void *priv)
                                 fdc.format_state = 0;
                                 break;
 
-                                case 2: /*Read track*/
+                                case 0x02: case 0x42: /*Read track*/
                                 fdc.pnum=0;
                                 fdc.ptot=8;
                                 fdc.stat=0x90;
                                 fdc.pos=0;
                                 break;
-                                case 3: /*Specify*/
+                                case 0x03: /*Specify*/
                                 fdc.pnum=0;
                                 fdc.ptot=2;
                                 fdc.stat=0x90;
                                 break;
-                                case 4: /*Sense drive status*/
+                                case 0x04: /*Sense drive status*/
                                 fdc.pnum=0;
                                 fdc.ptot=1;
                                 fdc.stat=0x90;
                                 break;
-                                case 5: /*Write data*/
+                                case 0x05: case 0x45: case 0x85: case 0xc5: /*Write data*/
 //                                printf("Write data!\n");
                                 fdc.pnum=0;
                                 fdc.ptot=8;
@@ -443,18 +447,19 @@ void fdc_write(uint16_t addr, uint8_t val, void *priv)
                                 fdc.pos=0;
 //                                readflash=1;
                                 break;
-                                case 6: /*Read data*/
+                                case 0x06: case 0x26: case 0x46: case 0x66: /*Read data*/
+                                case 0x86: case 0xa6: case 0xc6: case 0xe6:
                                 fdc.pnum=0;
                                 fdc.ptot=8;
                                 fdc.stat=0x90;
                                 fdc.pos=0;
                                 break;
-                                case 7: /*Recalibrate*/
+                                case 0x07: /*Recalibrate*/
                                 fdc.pnum=0;
                                 fdc.ptot=1;
                                 fdc.stat=0x90;
                                 break;
-                                case 8: /*Sense interrupt status*/
+                                case 0x08: /*Sense interrupt status*/
                                 if (fdc.int_pending || fdc_reset_stat)
                                 {
 //                                        printf("Sense interrupt status %i\n",curdrive);
@@ -471,20 +476,20 @@ void fdc_write(uint16_t addr, uint8_t val, void *priv)
                 			timer_set_delay_u64(&fdc.timer, 100 * TIMER_USEC);
                                 }
                                 break;
-                                case 10: /*Read sector ID*/
+                                case 0x0a: case 0x4a: /*Read sector ID*/
                                 fdc.pnum=0;
                                 fdc.ptot=1;
                                 fdc.stat=0x90;
                                 fdc.pos=0;
                                 break;
-                                case 0x0d: /*Format track*/
+                                case 0x0d: case 0x4d: case 0x8d: case 0xcd: /*Format track*/
                                 fdc.pnum=0;
                                 fdc.ptot=5;
                                 fdc.stat=0x90;
                                 fdc.pos=0;
                                 fdc.format_state = 0;
                                 break;
-                                case 15: /*Seek*/
+                                case 0x0f: /*Seek*/
                                 fdc.pnum=0;
                                 fdc.ptot=2;
                                 fdc.stat=0x90;
@@ -552,15 +557,15 @@ bad_command:
                                 
 //                                pclog("Got all params %02X\n", fdc.command);
                                 fdc.stat=0x30;
-                                discint=fdc.command&0x1F;
         			timer_set_delay_u64(&fdc.timer, 256 * TIMER_USEC);
 //                                fdc.drive = fdc.params[0] & 3;
                                 disc_drivesel = fdc.drive & 1;
                                 fdc_reset_stat = 0;
                                 disc_set_drivesel(fdc.drive & 1);
-                                switch (discint)
+                                discint = fdc.command & 0x1f;
+                                switch (fdc.command)
                                 {
-                                        case 2: /*Read a track*/
+                                        case 0x02: case 0x42: /*Read track*/
 					fdc_rate(fdc.drive);
                                         fdc.head=fdc.params[2];
                                         fdc.sector=fdc.params[3];
@@ -576,7 +581,7 @@ bad_command:
                                         fdc.inread = 1;
                                         break;
 
-                                        case 3: /*Specify*/
+                                        case 0x03: /*Specify*/
                                         fdc.stat=0x80;
                                         fdc.specify[0] = fdc.params[0];
                                         fdc.specify[1] = fdc.params[1];
@@ -584,18 +589,20 @@ bad_command:
                                         timer_disable(&fdc.timer);
                                         break;
 
-                                        case 5: /*Write data*/
+                                        case 0x05: case 0x45: case 0x85: case 0xc5: /*Write data*/
 					fdc_rate(fdc.drive);
                                         fdc.head=fdc.params[2];
                                         fdc.sector=fdc.params[3];
                                         fdc.sector_size = fdc.params[4];
                                         fdc.eot[fdc.drive] = fdc.params[5];
-                                        if (fdc.config & 0x40)
-                                                fdd_seek(fdc.drive, fdc.params[1] - fdc.track[fdc.drive]);
-                                        fdc.track[fdc.drive]=fdc.params[1];
                                         fdc.rw_track = fdc.params[1];
+                                        if (fdc.config & 0x40)
+                                        {
+                                                fdd_seek(fdc.drive, fdc.rw_track - fdc.track[fdc.drive]);
+                                                fdc.track[fdc.drive] = fdc.rw_track;
+                                        }
 
-                                        disc_writesector(fdc.drive, fdc.sector, fdc.track[fdc.drive], fdc.head, fdc.rate, fdc.params[4]);
+                                        disc_writesector(fdc.drive, fdc.sector, fdc.rw_track, fdc.head, fdc.rate, fdc.params[4]);
                                         timer_disable(&fdc.timer);
                                         fdc.written = 0;
                                         readflash_set(READFLASH_FDC, fdc.drive);
@@ -605,24 +612,27 @@ bad_command:
 //                                        ioc_fiq(IOC_FIQ_DISC_DATA);
                                         break;
                                         
-                                        case 6: /*Read data*/
+                                        case 0x06: case 0x26: case 0x46: case 0x66: /*Read data*/
+                                        case 0x86: case 0xa6: case 0xc6: case 0xe6:
 					fdc_rate(fdc.drive);
                                         fdc.head=fdc.params[2];
                                         fdc.sector=fdc.params[3];
                                         fdc.sector_size = fdc.params[4];
                                         fdc.eot[fdc.drive] = fdc.params[5];
-                                        if (fdc.config & 0x40)
-                                                fdd_seek(fdc.drive, fdc.params[1] - fdc.track[fdc.drive]);
-                                        fdc.track[fdc.drive]=fdc.params[1];
                                         fdc.rw_track = fdc.params[1];
+                                        if (fdc.config & 0x40)
+                                        {
+                                                fdd_seek(fdc.drive, fdc.rw_track - fdc.track[fdc.drive]);
+                                                fdc.track[fdc.drive] = fdc.rw_track;
+                                        }
                                         
-                                        disc_readsector(fdc.drive, fdc.sector, fdc.track[fdc.drive], fdc.head, fdc.rate, fdc.params[4]);
+                                        disc_readsector(fdc.drive, fdc.sector, fdc.rw_track, fdc.head, fdc.rate, fdc.params[4]);
                                         timer_disable(&fdc.timer);
                                         readflash_set(READFLASH_FDC, fdc.drive);
                                         fdc.inread = 1;
                                         break;
                                         
-                                        case 7: /*Recalibrate*/
+                                        case 0x07: /*Recalibrate*/
                                         fdc.stat =  1 << fdc.drive;
                                         timer_disable(&fdc.timer);
                                         time = fdd_seek(fdc.drive, SEEK_RECALIBRATE);
@@ -630,7 +640,7 @@ bad_command:
                                                 timer_set_delay_u64(&fdc.timer, time);
                                         break;
 
-                                        case 0x0d: /*Format*/
+                                        case 0x0d: case 0x4d: case 0x8d: case 0xcd: /*Format*/
 					fdc_rate(fdc.drive);
                                         fdc.head = (fdc.params[0] & 4) ? 1 : 0;
                                         fdc.format_state = 1;
@@ -638,9 +648,9 @@ bad_command:
                                         fdc.stat = 0x30;
                                         break;
                                         
-                                        case 0xf: /*Seek*/
+                                        case 0x0f: /*Seek*/
                                         fdc.stat =  1 << fdc.drive;
-                                        fdc.head = (fdc.params[0] & 4) ? 1 : 0;
+                                        fdc.head = 0;
                                         timer_disable(&fdc.timer);
                                         time = fdd_seek(fdc.drive, fdc.params[1] - fdc.track[fdc.drive]);
                                         if (time)
@@ -648,19 +658,23 @@ bad_command:
 //                                        pclog("Seek to %i\n", fdc.params[1]);
                                         break;
                                         
-                                        case 10: /*Read sector ID*/
+                                        case 0x0a: case 0x4a: /*Read sector ID*/
 					fdc_rate(fdc.drive);
                                         timer_disable(&fdc.timer);
                                         fdc.head = (fdc.params[0] & 4) ? 1 : 0;                                        
 //                                        pclog("Read sector ID %i %i\n", fdc.rate, fdc.drive);
                                         disc_readaddress(fdc.drive, fdc.track[fdc.drive], fdc.head, fdc.rate);
                                         break;
+                                        
+                                        case 0x94: /*Unlock*/
+                                        discint = 0x94;
+                                        break;
                                 }
                         }
                 }
                 return;
                 case 7:
-                if (!AT && romset != ROM_XI8088)
+                if (!AT && romset != ROM_XI8088 && romset != ROM_PC5086)
                         return;
                 fdc.rate=val&3;
 
@@ -760,10 +774,6 @@ uint8_t fdc_read(uint16_t addr, void *priv)
                         temp=fdc.dat;
                         fdc.data_ready = 0;
                 }
-                if (discint==0xA) 
-		{
-			timer_set_delay_u64(&fdc.timer, 1024 * TIMER_USEC);
-		}
                 fdc.stat &= 0xf0;
                 break;
                 case 7: /*Disk change*/
@@ -791,7 +801,6 @@ uint8_t fdc_read(uint16_t addr, void *priv)
 void fdc_callback()
 {
         int temp;
-        int doseek = 0;
         int drive;
         
 //        pclog("fdc_callback %i\n", discint);
@@ -860,102 +869,82 @@ void fdc_callback()
                 discint = 0;
                 return;
                 case 5: /*Write data*/
-                if (!fdc.in_seek_mt)
+                readflash_set(READFLASH_FDC, fdc.drive);
+                if (fdc.sector == fdc.params[5])
                 {
-                        readflash_set(READFLASH_FDC, fdc.drive);
+                        fdc.sector = 1;
-                        fdc.sector++;
+                        if (fdc.command & 0x80)
-                        if (fdc.sector > fdc.params[5])
                         {
-                                fdc.sector = 1;
+                                fdc.head ^= 1;
-                                if (fdc.command & 0x80)
+                                if (!fdc.head)
-                                {
-                                        fdc.head ^= 1;
-                                        if (!fdc.head)
-                                        {
-                                                fdc.rw_track++;
-                                                doseek = 1;
-                                        }
-                                }
-                                else
                                 {
                                         fdc.rw_track++;
                                         fdc.tc = 1;
                                 }
                         }
-                        if (fdc.tc)
+                        else
                         {
-                                discint=-2;
+                                fdc.rw_track++;
-                                fdc_int();
+                                fdc.tc = 1;
-                                fdc.stat=0xD0;
-                                fdc.res[4]=(fdc.head?4:0)|fdc.drive;
-                                fdc.res[5]=fdc.res[6]=0;
-                                fdc.res[7]=fdc.rw_track;
-                                fdc.res[8]=fdc.head;
-                                fdc.res[9]=fdc.sector;
-                                fdc.res[10]=fdc.params[4];
-                                paramstogo=7;
-                                return;
-                        }
-                        if (doseek)
-                        {
-                                fdd_seek(fdc.drive, 1);
-                                fdc.in_seek_mt = 1;
-                                /*Allow seek to complete before starting next sector write*/
-                                return;
                         }
                 }
-                fdc.in_seek_mt = 0;
+                else
+                        fdc.sector++;
+                if (fdc.tc)
+                {
+                        discint=-2;
+                        fdc_int();
+                        fdc.stat=0xD0;
+                        fdc.res[4]=(fdc.head?4:0)|fdc.drive;
+                        fdc.res[5]=fdc.res[6]=0;
+                        fdc.res[7]=fdc.rw_track;
+                        fdc.res[8]=fdc.head;
+                        fdc.res[9]=fdc.sector;
+                        fdc.res[10]=fdc.params[4];
+                        paramstogo=7;
+                        return;
+                }
                 disc_writesector(fdc.drive, fdc.sector, fdc.rw_track, fdc.head, fdc.rate, fdc.params[4]);
 //                ioc_fiq(IOC_FIQ_DISC_DATA);
                 return;
                 case 6: /*Read data*/
 //                rpclog("Read data %i\n", fdc.tc);
-                if (!fdc.in_seek_mt)
+                readflash_set(READFLASH_FDC, fdc.drive);
+                if (fdc.sector == fdc.params[5])
                 {
-                        readflash_set(READFLASH_FDC, fdc.drive);
+                        fdc.sector = 1;
-                        fdc.sector++;
+                        if (fdc.command & 0x80)
-                        if (fdc.sector > fdc.params[5])
                         {
-                                fdc.sector = 1;
+                                fdc.head ^= 1;
-                                if (fdc.command & 0x80)
+                                if (!fdc.head)
-                                {
-                                        fdc.head ^= 1;
-                                        if (!fdc.head)
-                                        {
-                                                fdc.rw_track++;
-                                                doseek = 1;
-                                        }
-                                }
-                                else
                                 {
                                         fdc.rw_track++;
                                         fdc.tc = 1;
                                 }
                         }
-                        if (fdc.tc)
+                        else
                         {
-                                fdc.inread = 0;
+                                fdc.rw_track++;
-                                discint=-2;
+                                fdc.tc = 1;
-                                fdc_int();
-                                fdc.stat=0xD0;
-                                fdc.res[4]=(fdc.head?4:0)|fdc.drive;
-                                fdc.res[5]=fdc.res[6]=0;
-                                fdc.res[7]=fdc.rw_track;
-                                fdc.res[8]=fdc.head;
-                                fdc.res[9]=fdc.sector;
-                                fdc.res[10]=fdc.params[4];
-                                paramstogo=7;
-                                return;
-                        }                        
-                        if (doseek)
-                        {
-                                fdd_seek(fdc.drive, 1);
-                                fdc.in_seek_mt = 1;
-                                /*Allow seek to complete before starting next sector read*/
-                                return;
                         }
                 }
-                fdc.in_seek_mt = 0;
+                else
+                        fdc.sector++;
+                if (fdc.tc)
+                {
+                        fdc.inread = 0;
+                        discint=-2;
+                        fdc_int();
+                        fdc.stat=0xD0;
+                        fdc.res[4]=(fdc.head?4:0)|fdc.drive;
+                        fdc.res[5]=fdc.res[6]=0;
+                        fdc.res[7]=fdc.rw_track;
+                        fdc.res[8]=fdc.head;
+                        fdc.res[9]=fdc.sector;
+                        fdc.res[10]=fdc.params[4];
+                        paramstogo=7;
+                        return;
+                }
                 disc_readsector(fdc.drive, fdc.sector, fdc.rw_track, fdc.head, fdc.rate, fdc.params[4]);
                 fdc.inread = 1;
                 return;
@@ -1054,14 +1043,16 @@ void fdc_callback()
                 return;
                 case 0x0e: /*Dump registers*/
                 fdc.stat = (fdc.stat & 0xf) | 0xd0;
-                fdc.res[3] = fdc.track[0];
+                fdc.res[1] = fdc.track[0];
-                fdc.res[4] = fdc.track[1];
+                fdc.res[2] = fdc.track[1];
-                fdc.res[5] = 0;
+                fdc.res[3] = 0;
-                fdc.res[6] = 0;
+                fdc.res[4] = 0;
-                fdc.res[7] = fdc.specify[0];
+                fdc.res[5] = fdc.specify[0];
-                fdc.res[8] = fdc.specify[1];
+                fdc.res[6] = fdc.specify[1];
-                fdc.res[9] = fdc.eot[fdc.drive];
+                fdc.res[7] = fdc.eot[fdc.drive];
-                fdc.res[10] = (fdc.perp & 0x7f) | ((fdc.lock) ? 0x80 : 0);
+                fdc.res[8] = (fdc.perp & 0x7f) | ((fdc.lock) ? 0x80 : 0);
+                fdc.res[9] = fdc.config;
+                fdc.res[10] = fdc.pretrk;
                 paramstogo=10;
                 discint=0;
                 return;
@@ -1206,15 +1197,33 @@ void fdc_finishread()
 //        rpclog("fdc_finishread\n");
 }
 
-void fdc_notfound()
+void fdc_notfound(int reason)
 {
+//        pclog("fdc_notfound: reason=%i\n", reason);
         timer_disable(&fdc.timer);
 
         fdc_int();
         fdc.stat=0xD0;
         fdc.res[4]=0x40|(fdc.head?4:0)|fdc.drive;
-        fdc.res[5]=5;
+        switch (reason)
-        fdc.res[6]=0;
+        {
+                case FDC_STATUS_AM_NOT_FOUND:
+                fdc.res[5] = ST1_ND | ST1_MA;
+                fdc.res[6] = 0;
+                break;
+                case FDC_STATUS_NOT_FOUND:
+                fdc.res[5] = ST1_ND;
+                fdc.res[6] = 0;
+                break;
+                case FDC_STATUS_WRONG_CYLINDER:
+                fdc.res[5] = ST1_ND;
+                fdc.res[6] = ST2_WC;
+                break;
+                case FDC_STATUS_BAD_CYLINDER:
+                fdc.res[5] = ST1_ND;
+                fdc.res[6] = ST2_WC | ST2_BC;
+                break;
+        }
         fdc.res[7] = fdc.rw_track;
         fdc.res[8] = fdc.head;
         fdc.res[9] = fdc.sector;
@@ -1389,6 +1398,11 @@ void fdc_discchange_clear(int drive)
                 disc_changed[drive] = 0;
 }
 
+int fdc_discchange_read()
+{
+        return (disc_changed[fdc.drive] || drive_empty[fdc.drive]) ? 1 : 0;
+}
+
 void fdc_set_dskchg_activelow()
 {
         fdc.dskchg_activelow = 1;

src/fdc.h

@@ -7,6 +7,7 @@ void fdc_reset();
 void fdc_poll();
 void fdc_abort();
 void fdc_discchange_clear(int drive);
+int fdc_discchange_read();
 void fdc_set_dskchg_activelow();
 void fdc_3f1_enable(int enable);
 void fdc_set_ps1();
@@ -23,3 +24,13 @@ void fdc_update_boot_drive(int boot_drive);
 void fdc_update_densel_polarity(int densel_polarity);
 void fdc_update_densel_force(int densel_force);
 void fdc_update_drvrate(int drive, int drvrate);
+
+
+
+enum
+{
+        FDC_STATUS_AM_NOT_FOUND,
+        FDC_STATUS_NOT_FOUND,
+        FDC_STATUS_WRONG_CYLINDER,
+        FDC_STATUS_BAD_CYLINDER
+};

src/fdc37c93x.c

@@ -0,0 +1,253 @@
+#include "ibm.h"
+
+#include "fdc.h"
+#include "fdd.h"
+#include "io.h"
+#include "lpt.h"
+#include "serial.h"
+#include "fdc37c93x.h"
+
+typedef struct fdc37c93x_t
+{
+        int index;
+        
+        uint8_t global_regs[0x30];
+        uint8_t fdc_regs[0x100];
+        uint8_t ide1_regs[0x100];
+        uint8_t ide2_regs[0x100];
+        uint8_t lpt_regs[0x100];
+        uint8_t com1_regs[0x100];
+        uint8_t com2_regs[0x100];
+        uint8_t rtc_regs[0x100];
+        uint8_t kbd_regs[0x100];
+        uint8_t auxio_regs[0x100];
+        uint8_t accessbus_regs[0x100];
+        
+        uint8_t lock[2];
+} fdc37c93x_t;
+
+static fdc37c93x_t fdc37c93x_global;
+
+static void write_lock(fdc37c93x_t *fdc37c93x, uint8_t val)
+{
+        if (val == 0x55 && fdc37c93x->lock[1] == 0x55)
+                fdc_3f1_enable(0);
+        if (fdc37c93x->lock[0] == 0x55 && fdc37c93x->lock[1] == 0x55 && val != 0x55)
+                fdc_3f1_enable(1);
+
+        fdc37c93x->lock[0] = fdc37c93x->lock[1];
+        fdc37c93x->lock[1] = val;
+}
+
+void fdc37c93x_write(uint16_t port, uint8_t val, void *p)
+{
+        fdc37c93x_t *fdc37c93x = (fdc37c93x_t *)p;
+
+//        pclog("Write SuperIO %04x %02x\n", port, val);
+        if (fdc37c93x->lock[0] == 0x55 && fdc37c93x->lock[1] == 0x55)
+        {
+                if (port == 0x3f0)
+                {
+                        if (val == 0xaa)
+                                write_lock(fdc37c93x, val);
+                        else
+                                fdc37c93x->index = val;
+                }
+                else
+                {
+                        uint16_t addr;
+                        int irq;
+                        
+//                        pclog("fdc37c93x_write: index=%02x dev=%i val=%02x\n", fdc37c93x->index, fdc37c93x->global_regs[7], val);
+                        if (fdc37c93x->index < 0x30)
+                        {
+                                if (fdc37c93x->index != 0x20 && fdc37c93x->index != 0x21)
+                                        fdc37c93x->global_regs[fdc37c93x->index] = val;
+                        }
+                        else switch (fdc37c93x->global_regs[7])
+                        {
+                                case 0:
+                                fdc37c93x->fdc_regs[fdc37c93x->index] = val;
+                                break;
+                                case 1:
+                                fdc37c93x->ide1_regs[fdc37c93x->index] = val;
+                                break;
+                                case 2:
+                                fdc37c93x->ide2_regs[fdc37c93x->index] = val;
+                                break;
+                                case 3:
+                                fdc37c93x->lpt_regs[fdc37c93x->index] = val;
+                                break;
+                                case 4:
+                                fdc37c93x->com1_regs[fdc37c93x->index] = val;
+                                break;
+                                case 5:
+                                fdc37c93x->com2_regs[fdc37c93x->index] = val;
+                                break;
+                                case 6:
+                                fdc37c93x->rtc_regs[fdc37c93x->index] = val;
+                                break;
+                                case 7:
+                                fdc37c93x->kbd_regs[fdc37c93x->index] = val;
+                                break;
+                                case 8:
+                                fdc37c93x->auxio_regs[fdc37c93x->index] = val;
+                                break;
+                                case 9:
+                                fdc37c93x->accessbus_regs[fdc37c93x->index] = val;
+                                break;
+                        }
+
+                        fdc_remove();
+                        if ((fdc37c93x->global_regs[0x22] & 0x01) && (fdc37c93x->fdc_regs[0x30] & 0x01))
+                        {
+//                                pclog("FDC enabled\n");
+                                fdc_add();
+                        }
+/*                        else
+                                pclog("FDC disabled\n");*/
+
+                        lpt1_remove();
+                        lpt2_remove();
+                        addr = (fdc37c93x->lpt_regs[0x61] & 0xfc) | ((fdc37c93x->lpt_regs[0x60] & 3) << 8);
+                        if ((fdc37c93x->global_regs[0x22] & (1 << 3)) && (fdc37c93x->lpt_regs[0x30] & 0x01))
+                        {
+//                                pclog("LPT addr = %04x\n", addr);
+                                lpt1_init(addr);
+                        }
+/*                        else
+                                pclog("LPT disabled\n");*/
+                        
+                        serial1_remove();
+                        addr = (fdc37c93x->com1_regs[0x61] & 0xf8) | ((fdc37c93x->com1_regs[0x60] & 3) << 8);
+                        irq = fdc37c93x->com1_regs[0x70] & 0xf;
+                        if ((fdc37c93x->global_regs[0x22] & (1 << 4)) && (fdc37c93x->com1_regs[0x30] & 0x01))
+                        {
+//                                pclog("COM1 addr = %04x, IRQ = %i\n", addr, irq);
+                                serial1_set(addr, irq);
+                        }
+/*                        else
+                                pclog("COM1 disabled\n");*/
+
+                        serial2_remove();
+                        addr = (fdc37c93x->com2_regs[0x61] & 0xf8) | ((fdc37c93x->com2_regs[0x60] & 3) << 8);
+                        irq = fdc37c93x->com2_regs[0x70] & 0xf;
+                        if ((fdc37c93x->global_regs[0x22] & (1 << 5)) && (fdc37c93x->com2_regs[0x30] & 0x01))
+                        {
+//                                pclog("COM2 addr = %04x, IRQ = %i\n", addr, irq);
+                                serial2_set(addr, irq);
+                        }
+/*                        else
+                                pclog("COM2 disabled\n");*/
+
+
+			fdc_update_enh_mode(fdc37c93x->fdc_regs[0xf0] & 1);
+
+			fdc_update_densel_force((fdc37c93x->fdc_regs[0xf1] & 0x0c) >> 2);
+			fdd_swap = (fdc37c93x->fdc_regs[0xf0] & (1 << 4)) ? 1 : 0;
+                }
+        }
+        else
+        {
+                if (port == 0x3f0)
+                        write_lock(fdc37c93x, val);
+        }
+}
+
+uint8_t fdc37c93x_read(uint16_t port, void *p)
+{
+        fdc37c93x_t *fdc37c93x = (fdc37c93x_t *)p;
+        
+//        pclog("Read SuperIO %04x %02x\n", port, fdc37c665_curreg);
+        if (fdc37c93x->lock[0] == 0x55 && fdc37c93x->lock[1] == 0x55)
+        {
+                if (port == 0x3f1)
+                {
+                        if (fdc37c93x->index < 0x30)
+                                return fdc37c93x->global_regs[fdc37c93x->index];
+                        else switch (fdc37c93x->global_regs[7])
+                        {
+                                case 0:
+                                return fdc37c93x->fdc_regs[fdc37c93x->index];
+                                case 1:
+                                return fdc37c93x->ide1_regs[fdc37c93x->index];
+                                case 2:
+                                return fdc37c93x->ide2_regs[fdc37c93x->index];
+                                case 3:
+                                return fdc37c93x->lpt_regs[fdc37c93x->index];
+                                case 4:
+                                return fdc37c93x->com1_regs[fdc37c93x->index];
+                                case 5:
+                                return fdc37c93x->com2_regs[fdc37c93x->index];
+                                case 6:
+                                return fdc37c93x->rtc_regs[fdc37c93x->index];
+                                case 7:
+                                return fdc37c93x->kbd_regs[fdc37c93x->index];
+                                case 8:
+                                return fdc37c93x->auxio_regs[fdc37c93x->index];
+                                case 9:
+                                return fdc37c93x->accessbus_regs[fdc37c93x->index];
+                        }
+                }
+        }
+        return 0xff;
+}
+
+void fdc37c932fr_init()
+{
+        fdc37c93x_t *fdc37c93x = &fdc37c93x_global;
+        int c;
+        
+        io_sethandler(0x03f0, 0x0002, fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL,  fdc37c93x);
+
+        fdc_update_is_nsc(0);
+
+        memset(&fdc37c93x_global, 0, sizeof(fdc37c93x_global));
+
+        fdc37c93x->global_regs[0x03] = 0x03;
+        fdc37c93x->global_regs[0x20] = 0x03;
+        fdc37c93x->global_regs[0x21] = 0x01;
+        fdc37c93x->global_regs[0x24] = 0x04;
+        fdc37c93x->global_regs[0x26] = 0xf0;
+        fdc37c93x->global_regs[0x27] = 0x03;
+        
+        fdc37c93x->fdc_regs[0x60] = 0x03;
+        fdc37c93x->fdc_regs[0x61] = 0xf0;
+        fdc37c93x->fdc_regs[0x70] = 0x06;
+        fdc37c93x->fdc_regs[0x74] = 0x02;
+        fdc37c93x->fdc_regs[0xf0] = 0x0e;
+        fdc37c93x->fdc_regs[0xf2] = 0xff;
+        
+        fdc37c93x->ide1_regs[0x60] = 0x01;
+        fdc37c93x->ide1_regs[0x61] = 0xf0;
+        fdc37c93x->ide1_regs[0x62] = 0x03;
+        fdc37c93x->ide1_regs[0x63] = 0xf6;
+        fdc37c93x->ide1_regs[0x70] = 0x0e;
+        fdc37c93x->ide1_regs[0xf0] = 0x0c;
+        fdc37c93x->ide1_regs[0xf1] = 0x0d;
+
+        fdc37c93x->lpt_regs[0x74] = 0x04;
+        fdc37c93x->lpt_regs[0xf0] = 0x3c;
+
+        fdc37c93x->com2_regs[0x74] = 0x04;
+        fdc37c93x->com2_regs[0xf1] = 0x02;
+        fdc37c93x->com2_regs[0xf2] = 0x03;
+
+        fdc37c93x->rtc_regs[0x63] = 0x70;
+        fdc37c93x->rtc_regs[0xf4] = 0x03;
+
+        fdc37c93x->auxio_regs[0xb1] = 0x80;
+        fdc37c93x->auxio_regs[0xc0] = 0x01;
+        fdc37c93x->auxio_regs[0xc1] = 0x01;
+        fdc37c93x->auxio_regs[0xc5] = 0x01;
+        fdc37c93x->auxio_regs[0xc6] = 0x01;
+        fdc37c93x->auxio_regs[0xc7] = 0x01;
+        fdc37c93x->auxio_regs[0xc8] = 0x01;
+        fdc37c93x->auxio_regs[0xc9] = 0x80;
+        for (c = 0xcb; c < 0xee; c++)
+                fdc37c93x->auxio_regs[c] = 0x01;
+        
+	fdc_update_densel_polarity(1);
+	fdc_update_densel_force(0);
+	fdd_swap = 0;
+}

src/fdc37c93x.h

@@ -0,0 +1 @@
+extern void fdc37c932fr_init();

src/gameport.c

@@ -87,15 +87,19 @@ typedef struct gameport_t
 
 static gameport_t *gameport_global = NULL;
 
-static uint64_t gameport_time(int axis)
+static void gameport_time(gameport_t *gameport, int nr, int axis)
 {
         if (axis == AXIS_NOT_PRESENT)
-                return 0;
+        {
-
+                timer_disable(&gameport->axis[nr].timer);
-        axis += 32768;
+        }
-        axis = (axis * 100) / 65; /*Axis now in ohms*/
+        else
-        axis = (axis * 11) / 1000;
+        {
-        return TIMER_USEC * (axis + 24); /*max = 11.115 ms*/
+                axis += 32768;
+                axis = (axis * 100) / 65; /*Axis now in ohms*/
+                axis = (axis * 11) / 1000;
+                timer_set_delay_u64(&gameport->axis[nr].timer, TIMER_USEC * (axis + 24)); /*max = 11.115 ms*/
+        }
 }
 
 void gameport_write(uint16_t addr, uint8_t val, void *p)
@@ -105,10 +109,10 @@ void gameport_write(uint16_t addr, uint8_t val, void *p)
         gameport->state |= 0x0f;
 //        pclog("gameport_write : joysticks_present=%i\n", joysticks_present);
 
-        timer_set_delay_u64(&gameport->axis[0].timer, gameport_time(gameport->joystick->read_axis(gameport->joystick_dat, 0)));
+        gameport_time(gameport, 0, gameport->joystick->read_axis(gameport->joystick_dat, 0));
-        timer_set_delay_u64(&gameport->axis[1].timer, gameport_time(gameport->joystick->read_axis(gameport->joystick_dat, 1)));
+        gameport_time(gameport, 1, gameport->joystick->read_axis(gameport->joystick_dat, 1));
-        timer_set_delay_u64(&gameport->axis[2].timer, gameport_time(gameport->joystick->read_axis(gameport->joystick_dat, 2)));
+        gameport_time(gameport, 2, gameport->joystick->read_axis(gameport->joystick_dat, 2));
-        timer_set_delay_u64(&gameport->axis[3].timer, gameport_time(gameport->joystick->read_axis(gameport->joystick_dat, 3)));
+        gameport_time(gameport, 3, gameport->joystick->read_axis(gameport->joystick_dat, 3));
 
         gameport->joystick->write(gameport->joystick_dat);
         

src/hdd.c

@@ -9,6 +9,7 @@
 #include "mfm_xebec.h"
 #include "scsi_53c400.h"
 #include "scsi_aha1540.h"
+#include "scsi_ibm.h"
 #include "xtide.h"
 
 char hdd_controller_name[16];
@@ -39,6 +40,7 @@ static struct
         {"[IDE] XTIDE (PS/1)",                    "xtide_ps1",  &xtide_ps1_device,     0, 1, 0},
         {"[SCSI] Adaptec AHA-1542C",              "aha1542c",   &scsi_aha1542c_device, 0, 0, 1},
         {"[SCSI] BusLogic BT-545S",               "bt545s",     &scsi_bt545s_device,   0, 0, 1},
+        {"[SCSI] IBM SCSI Adapter with Cache",    "ibmscsi_mca",&scsi_ibm_device,      0, 0, 1},
         {"[SCSI] Longshine LCS-6821N",            "lcs6821n",   &scsi_lcs6821n_device, 0, 0, 1},
         {"[SCSI] Rancho RT1000B",                 "rt1000b",    &scsi_rt1000b_device,  0, 0, 1},
         {"[SCSI] Trantor T130B",                  "t130b",      &scsi_t130b_device,    0, 0, 1},

src/hdd_esdi.c

@@ -917,7 +917,7 @@ static void *esdi_init()
                 
         timer_add(&esdi->callback_timer, esdi_callback, esdi, 0);
         
-        mca_add(esdi_mca_read, esdi_mca_write, esdi);
+        mca_add(esdi_mca_read, esdi_mca_write, NULL, esdi);
         
         esdi->pos_regs[0] = 0xff;
         esdi->pos_regs[1] = 0xdd;

src/hdd_file.c

@@ -5,6 +5,8 @@
 
 #include "ibm.h"
 #include "hdd_file.h"
+#include "minivhd/minivhd.h"
+#include "minivhd/minivhd_util.h"
 
 void hdd_load_ext(hdd_file_t *hdd, const char *fn, int spt, int hpc, int tracks, int read_only)
 {
@@ -12,17 +14,52 @@ void hdd_load_ext(hdd_file_t *hdd, const char *fn, int spt, int hpc, int tracks,
         {
 		/* Try to open existing hard disk image */
 		if (read_only)
-        		hdd->f = fopen64(fn, "rb");
+                        hdd->f = (void*)fopen64(fn, "rb");
+		else
+                        hdd->f = (void*)fopen64(fn, "rb+");
+                if (hdd->f != NULL)
+                {
+                        hdd->img_type = HDD_IMG_RAW;
+                        /* Check if the file we opened is a VHD */
+                        if (mvhd_file_is_vhd((FILE*)hdd->f))
+                        {
+                                int err;
+                                fclose((FILE*)hdd->f);
+                                MVHDMeta *vhdm = mvhd_open(fn, (bool)read_only, &err);
+                                if (vhdm == NULL)
+                                {
+                                        hdd->f = NULL;
+                                        if (err == MVHD_ERR_FILE)
+                                        {
+                                                pclog("Cannot open VHD file '%s' : %s",
+                                                        fn, strerror(mvhd_errno));
+                                        }
+                                        else
+                                        {
+                                                pclog("Cannot open VHD file '%s' : %s",
+                                                        fn, mvhd_strerr(err));
+                                        }
+                                        return;
+                                }
+                                else if (err == MVHD_ERR_TIMESTAMP)
+                                {
+                                        pclog("VHD: Parent/child timestamp mismatch");
+                                        mvhd_close(vhdm);
+                                        hdd->f = NULL;
+                                        return;
+                                }
+                                hdd->f = (void*)vhdm;
+                                hdd->img_type = HDD_IMG_VHD;
+                        }
+                }
 		else
-        		hdd->f = fopen64(fn, "rb+");
-		if (hdd->f == NULL)
                 {
 			/* Failed to open existing hard disk image */
 			if (errno == ENOENT && !read_only)
                         {
 				/* Failed because it does not exist,
 				   so try to create new file */
-				hdd->f = fopen64(fn, "wb+");
+				hdd->f = (void*)fopen64(fn, "wb+");
 				if (hdd->f == NULL)
                                 {
 					pclog("Cannot create file '%s': %s",
@@ -37,13 +74,24 @@ void hdd_load_ext(hdd_file_t *hdd, const char *fn, int spt, int hpc, int tracks,
 				      fn, strerror(errno));
 				return;
 			}
+                        hdd->img_type = HDD_IMG_RAW;
 		}
 	}
-
+        if (hdd->img_type == HDD_IMG_VHD)
-        hdd->spt = spt;
+        {
-        hdd->hpc = hpc;
+                MVHDMeta *vhdm = (MVHDMeta*)hdd->f;
-        hdd->tracks = tracks;
+                MVHDGeom geom = mvhd_get_geometry(vhdm);
-        hdd->sectors = spt * hpc * tracks;
+                hdd->spt = geom.spt;
+                hdd->hpc = geom.heads;
+                hdd->tracks = geom.cyl;
+        }
+        else if (hdd->img_type == HDD_IMG_RAW)
+        {
+                hdd->spt = spt;
+                hdd->hpc = hpc;
+                hdd->tracks = tracks;
+        }
+        hdd->sectors = hdd->spt * hdd->hpc * hdd->tracks;
         hdd->read_only = read_only;
 }
 
@@ -56,68 +104,99 @@ void hdd_close(hdd_file_t *hdd)
 {
         if (hdd->f)
         {
-                fclose(hdd->f);
+                if (hdd->img_type == HDD_IMG_VHD)
-                hdd->f = NULL;
+                        mvhd_close((MVHDMeta*)hdd->f);
+                else if (hdd->img_type == HDD_IMG_RAW)
+                        fclose((FILE*)hdd->f);
         }
+        hdd->img_type = HDD_IMG_RAW;
+        hdd->f = NULL;
 }
 
 int hdd_read_sectors(hdd_file_t *hdd, int offset, int nr_sectors, void *buffer)
 {
-        off64_t addr;
+        if (hdd->img_type == HDD_IMG_VHD)
-        int transfer_sectors = nr_sectors;
+        {
+                return mvhd_read_sectors((MVHDMeta*)hdd->f, offset, nr_sectors, buffer);
+        }
+        else if (hdd->img_type == HDD_IMG_RAW)
+        {
+                off64_t addr;
+                int transfer_sectors = nr_sectors;
 
-        if ((hdd->sectors - offset) < transfer_sectors)
+                if ((hdd->sectors - offset) < transfer_sectors)
-                transfer_sectors = hdd->sectors - offset;
+                        transfer_sectors = hdd->sectors - offset;
-        addr = (uint64_t)offset * 512;
+                addr = (uint64_t)offset * 512;
 
-        fseeko64(hdd->f, addr, SEEK_SET);
+                fseeko64((FILE*)hdd->f, addr, SEEK_SET);
-        fread(buffer, transfer_sectors*512, 1, hdd->f);
+                fread(buffer, transfer_sectors*512, 1, (FILE*)hdd->f);
 
-        if (nr_sectors != transfer_sectors)
+                if (nr_sectors != transfer_sectors)
-                return 1;
+                        return 1;
-        return 0;
+                return 0;
+        }
+        /* Keep the compiler happy */
+        return 1;
 }
 
 int hdd_write_sectors(hdd_file_t *hdd, int offset, int nr_sectors, void *buffer)
 {
-        off64_t addr;
+        if (hdd->img_type == HDD_IMG_VHD)
-        int transfer_sectors = nr_sectors;
+        {
+                return mvhd_write_sectors((MVHDMeta*)hdd->f, offset, nr_sectors, buffer);
+        }
+        else if (hdd->img_type == HDD_IMG_RAW)
+        {
+                off64_t addr;
+                int transfer_sectors = nr_sectors;
 
-        if (hdd->read_only)
+                if (hdd->read_only)
-                return 1;
+                        return 1;
 
-        if ((hdd->sectors - offset) < transfer_sectors)
+                if ((hdd->sectors - offset) < transfer_sectors)
-                transfer_sectors = hdd->sectors - offset;
+                        transfer_sectors = hdd->sectors - offset;
-        addr = (uint64_t)offset * 512;
+                addr = (uint64_t)offset * 512;
 
-        fseeko64(hdd->f, addr, SEEK_SET);
+                fseeko64((FILE*)hdd->f, addr, SEEK_SET);
-        fwrite(buffer, transfer_sectors*512, 1, hdd->f);
+                fwrite(buffer, transfer_sectors*512, 1, (FILE*)hdd->f);
 
-        if (nr_sectors != transfer_sectors)
+                if (nr_sectors != transfer_sectors)
-                return 1;
+                        return 1;
-        return 0;
+                return 0;
+        }
+        /* Keep the compiler happy */
+        return 1;
 }
 
 int hdd_format_sectors(hdd_file_t *hdd, int offset, int nr_sectors)
 {
-        off64_t addr;
+        if (hdd->img_type == HDD_IMG_VHD)
-        int c;
+        {
-        uint8_t zero_buffer[512];
+                return mvhd_format_sectors((MVHDMeta*)hdd->f, offset, nr_sectors);
-        int transfer_sectors = nr_sectors;
+        }
+        else if (hdd->img_type == HDD_IMG_RAW)
+        {
+                off64_t addr;
+                int c;
+                uint8_t zero_buffer[512];
+                int transfer_sectors = nr_sectors;
 
-        if (hdd->read_only)
+                if (hdd->read_only)
-                return 1;
+                        return 1;
 
-        memset(zero_buffer, 0, 512);
+                memset(zero_buffer, 0, 512);
                 
-        if ((hdd->sectors - offset) < transfer_sectors)
+                if ((hdd->sectors - offset) < transfer_sectors)
-                transfer_sectors = hdd->sectors - offset;
+                        transfer_sectors = hdd->sectors - offset;
-        addr = (uint64_t)offset * 512;
+                addr = (uint64_t)offset * 512;
-        fseeko64(hdd->f, addr, SEEK_SET);
+                fseeko64((FILE*)hdd->f, addr, SEEK_SET);
-        for (c = 0; c < transfer_sectors; c++)
+                for (c = 0; c < transfer_sectors; c++)
-                fwrite(zero_buffer, 512, 1, hdd->f);
+                        fwrite(zero_buffer, 512, 1, (FILE*)hdd->f);
 
-        if (nr_sectors != transfer_sectors)
+                if (nr_sectors != transfer_sectors)
-                return 1;
+                        return 1;
-        return 0;
+                return 0;
+        }
+        /* Keep the compiler happy */
+        return 1;
 }

src/hdd_file.h

@@ -1,11 +1,18 @@
+typedef enum hdd_img_type
+{
+        HDD_IMG_RAW,
+        HDD_IMG_VHD,
+} hdd_img_type;
+
 typedef struct hdd_file_t
 {
-        FILE *f;
+        void *f;
         int spt;
         int hpc;
         int tracks;
         int sectors;
         int read_only;
+        hdd_img_type img_type;
 } hdd_file_t;
 
 void hdd_load(hdd_file_t *hdd, int d, const char *fn);

src/headland.c

@@ -8,16 +8,173 @@
 
 static int headland_index;
 static uint8_t headland_regs[256];
+static uint8_t headland_port_92 = 0xFC, headland_ems_mar = 0, headland_cri = 0;
+static uint8_t headland_regs_cr[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+static uint16_t headland_ems_mr[64];
+
+static mem_mapping_t headland_low_mapping;
+static mem_mapping_t headland_ems_mapping[64];
+static mem_mapping_t headland_mid_mapping;
+static mem_mapping_t headland_high_mapping;
+static mem_mapping_t headland_4000_9FFF_mapping[24];
+
+// TODO - Headland chipset's memory address mapping emulation isn't fully implemented yet, so memory configuration is hardcoded now.
+static int headland_mem_conf_cr0[41] = { 0x00, 0x00, 0x20, 0x40, 0x60, 0xA0, 0x40, 0xE0,
+                                         0xA0, 0xC0, 0xE0, 0xE0, 0xC0, 0xE0, 0xE0, 0xE0,
+                                         0xE0, 0x20, 0x40, 0x40, 0xA0, 0xC0, 0xE0, 0xE0,
+                                         0xC0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
+                                         0x20, 0x40, 0x60, 0x60, 0xC0, 0xE0, 0xE0, 0xE0,
+                                         0xE0 };
+static int headland_mem_conf_cr1[41] = { 0x00, 0x40, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40,
+                                         0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+                                         0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+                                         0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+                                         0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+                                         0x40 };
+
+uint32_t get_headland_addr(uint32_t addr, uint16_t *mr)
+{
+        if (mr && (headland_regs_cr[0] & 2) && (*mr & 0x200))
+        {
+                addr = (addr & 0x3fff) | ((*mr & 0x1F) << 14);
+
+                if(headland_regs_cr[1] & 0x40)
+                {
+                        if((headland_regs_cr[4] & 0x80) && (headland_regs_cr[6] & 1))
+                        {
+                                if(headland_regs_cr[0] & 0x80)
+                                {
+                                        addr |= (*mr & 0x60) << 14;
+                                        if(*mr & 0x100)
+                                                addr += ((*mr & 0xC00) << 13) + (((*mr & 0x80) + 0x80) << 15);
+                                        else
+                                                addr += (*mr & 0x80) << 14;
+                                }
+                                else if(*mr & 0x100)
+                                        addr += ((*mr & 0xC00) << 13) + (((*mr & 0x80) + 0x20) << 15);
+                                else
+                                        addr += (*mr & 0x80) << 12;
+                        }
+                        else if(headland_regs_cr[0] & 0x80)
+                                addr |= (*mr & 0x100) ? ((*mr & 0x80) + 0x400) << 12 : (*mr & 0xE0) << 14;
+                        else
+                                addr |= (*mr & 0x100) ? ((*mr & 0xE0) + 0x40) << 14 : (*mr & 0x80) << 12; 
+                }
+                else
+                {
+                        if((headland_regs_cr[4] & 0x80) && (headland_regs_cr[6] & 1))
+                        {
+                                if(headland_regs_cr[0] & 0x80)
+                                {
+                                        addr |= ((*mr & 0x60) << 14);
+                                        if(*mr & 0x180)
+                                                addr += ((*mr & 0xC00) << 13) + (((*mr & 0x180) - 0x60) << 16);
+                                }
+                                else
+                                        addr |= ((*mr & 0x60) << 14) | ((*mr & 0x180) << 16) | ((*mr & 0xC00) << 13);
+                        }
+                        else if(headland_regs_cr[0] & 0x80)
+                                addr |= (*mr & 0x1E0) << 14;
+                        else
+                                addr |= (*mr & 0x180) << 12;
+                }
+        }
+        else if(mr == NULL && (headland_regs_cr[0] & 4) == 0 && mem_size >= 1024 && addr >= 0x100000)
+                addr -= 0x60000;
+
+        return addr;
+}
+
+void headland_set_global_EMS_state(int state)
+{
+        int i;
+        uint32_t base_addr, virt_addr;
+
+        for(i=0; i<32; i++)
+        {
+                base_addr = (i + 16) << 14;
+                if(i >= 24)
+                        base_addr += 0x20000;
+                if((state & 2) && (headland_ems_mr[((state & 1) << 5) | i] & 0x200))
+                {
+                        virt_addr = get_headland_addr(base_addr, &headland_ems_mr[((state & 1) << 5) | i]);
+                        if(i < 24) mem_mapping_disable(&headland_4000_9FFF_mapping[i]);
+                        mem_mapping_disable(&headland_ems_mapping[(((state ^ 1) & 1) << 5) | i]);
+                        mem_mapping_enable(&headland_ems_mapping[((state & 1) << 5) | i]);
+                        if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], ram + virt_addr);
+                        else mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], NULL);
+                }
+                else
+                {
+                        mem_mapping_set_exec(&headland_ems_mapping[((state & 1) << 5) | i], ram + base_addr);
+                        mem_mapping_disable(&headland_ems_mapping[(((state ^ 1) & 1) << 5) | i]);
+                        mem_mapping_disable(&headland_ems_mapping[((state & 1) << 5) | i]);
+
+                        if(i < 24)
+                                mem_mapping_enable(&headland_4000_9FFF_mapping[i]);
+                }
+        }
+        flushmmucache();
+}
+
+void headland_memmap_state_update()
+{
+        int i;
+        uint32_t addr;
+
+        for(i=0;i<24;i++)
+        {
+                addr = get_headland_addr(0x40000 + (i << 14), NULL);
+                mem_mapping_set_exec(&headland_4000_9FFF_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
+                //pclog("headland_memmap_state_update : Address %06X to %06X\n", 0x40000 + (i << 14), addr);
+        }
+
+        mem_set_mem_state(0xA0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+
+        if (mem_size > 640)
+        {
+                if ((headland_regs_cr[0] & 4) == 0)
+                {
+                        mem_mapping_set_addr(&headland_mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
+                        mem_mapping_set_exec(&headland_mid_mapping, ram + 0xA0000);
+                        if (mem_size > 1024)
+                        {
+                                mem_mapping_set_addr(&headland_high_mapping, 0x160000, (mem_size - 1024) << 10);
+                                mem_mapping_set_exec(&headland_high_mapping, ram + 0x100000);
+                        }
+                }
+                else
+                {
+                        mem_mapping_set_addr(&headland_mid_mapping, 0xA0000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
+                        mem_mapping_set_exec(&headland_mid_mapping, ram + 0xA0000);
+                        if (mem_size > 1024)
+                        {
+                                mem_mapping_set_addr(&headland_high_mapping, 0x100000, (mem_size - 1024) << 10);
+                                mem_mapping_set_exec(&headland_high_mapping, ram + 0x100000);
+                        }
+                }
+        }
+
+        headland_set_global_EMS_state(headland_regs_cr[0] & 3);
+}
 
 void headland_write(uint16_t addr, uint8_t val, void *priv)
 {
-        if (addr & 1)
+        uint8_t old_val, index;
+        uint32_t base_addr, virt_addr;
+
+        switch(addr)
         {
-                uint8_t old_val = headland_regs[headland_index];
+                case 0x22:
+                headland_index = val;
+                break;
+
+                case 0x23:
+                old_val = headland_regs[headland_index];
                 
                 if (headland_index == 0xc1 && !is486) val = 0;
                 headland_regs[headland_index] = val;
-                pclog("Headland write %02X %02X\n",headland_index,val);
+                //pclog("Headland write %02X %02X at %04X:%04X\n",headland_index,val,CS,cpu_state.oldpc);
                 if (headland_index == 0x82)
                 {
                         if (val & 0x10)
@@ -30,23 +187,348 @@ void headland_write(uint16_t addr, uint8_t val, void *priv)
                         if ((val & 1) && !(old_val & 1))
                                 softresetx86();
                 }
+                break;
+
+                case 0x92:
+                if ((mem_a20_alt ^ val) & 2)
+                {
+                         mem_a20_alt = val & 2;
+                         mem_a20_recalc();
+                }
+                if ((~headland_port_92 & val) & 1)
+                {
+                         softresetx86();
+                        cpu_set_edx();
+                }
+                headland_port_92 = val | 0xFC;
+                break;
+
+                case 0x1EC:
+                //pclog("Set EMS Map Register to %02X(actually FF%02X) at %04X:%04X\n", val, val, CS, cpu_state.oldpc);
+                headland_ems_mr[headland_ems_mar & 0x3F] = val | 0xFF00;
+                index = headland_ems_mar & 0x1F;
+                base_addr = (index + 16) << 14;
+                if(index >= 24)
+                        base_addr += 0x20000;
+                if((headland_regs_cr[0] & 2) && ((headland_regs_cr[0] & 1) == ((headland_ems_mar & 0x20) >> 5)))
+                {
+                        virt_addr = get_headland_addr(base_addr, &headland_ems_mr[headland_ems_mar & 0x3F]);
+                        if(index < 24) mem_mapping_disable(&headland_4000_9FFF_mapping[index]);
+                        if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + virt_addr);
+                        else mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], NULL);
+                        mem_mapping_enable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
+                        pclog("Map page %d(address %05X) to address %06X\n", index, base_addr, virt_addr);
+                        flushmmucache();
+                }
+                if(headland_ems_mar & 0x80) headland_ems_mar++;
+                break;
+
+                case 0x1ED:
+                //pclog("Set Control Register Index to %02X at %04X:%04X\n", val, CS, cpu_state.oldpc);
+                headland_cri = val;
+                break;
+
+                case 0x1EE:
+                //pclog("Set EMS Map Address Register to %02X at %04X:%04X\n", val, CS, cpu_state.oldpc);
+                headland_ems_mar = val;
+                break;
+
+                case 0x1EF:
+                //pclog("Set Control Register %1X to %02X at %04X:%04X\n", headland_cri, val, CS, cpu_state.oldpc);
+                old_val = headland_regs_cr[headland_cri];
+                switch(headland_cri)
+                {
+                        case 0:
+                        headland_regs_cr[0] = (val & 0x1F) | headland_mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
+                        mem_set_mem_state(0xE0000, 0x10000, (val & 8 ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
+                        mem_set_mem_state(0xF0000, 0x10000, (val & 0x10 ? MEM_READ_INTERNAL: MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
+                        headland_memmap_state_update();
+                        break;
+                        case 1:
+                        headland_regs_cr[1] = (val & 0xBF) | headland_mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
+                        headland_memmap_state_update();
+                        break;
+                        case 2:
+                        case 3:
+                        case 5:
+                        headland_regs_cr[headland_cri] = val;
+                        headland_memmap_state_update();
+                        break;
+                        case 4:
+                        headland_regs_cr[4] = (headland_regs_cr[4] & 0xF0) | (val & 0x0F);
+                        if(val & 1)
+                        {
+                                mem_mapping_disable(&bios_mapping[0]);
+                                mem_mapping_disable(&bios_mapping[1]);
+                                mem_mapping_disable(&bios_mapping[2]);
+                                mem_mapping_disable(&bios_mapping[3]);
+                        }
+                        else
+                        {
+                                mem_mapping_enable(&bios_mapping[0]);
+                                mem_mapping_enable(&bios_mapping[1]);
+                                mem_mapping_enable(&bios_mapping[2]);
+                                mem_mapping_enable(&bios_mapping[3]);
+                        }
+                        break;
+                        case 6:
+                        if(headland_regs_cr[4] & 0x80)
+                        {
+                                headland_regs_cr[headland_cri] = (val & 0xFE) | (mem_size > 8192 ? 1 : 0);
+                                headland_memmap_state_update();
+                        }
+                        break;
+                        default:
+                        break;
+                }
+                break;
+
+                default:
+                break;
+        }
+}
+
+void headland_writew(uint16_t addr, uint16_t val, void *priv)
+{
+        uint8_t index;
+        uint32_t base_addr, virt_addr;
+
+        switch(addr)
+        {
+                case 0x1EC:
+                //pclog("Set EMS Map Register to %04X at %04X:%04X\n", val, CS, cpu_state.oldpc);
+                headland_ems_mr[headland_ems_mar & 0x3F] = val;
+                index = headland_ems_mar & 0x1F;
+                base_addr = (index + 16) << 14;
+                if(index >= 24)
+                        base_addr += 0x20000;
+                if((headland_regs_cr[0] & 2) && (headland_regs_cr[0] & 1) == ((headland_ems_mar & 0x20) >> 5))
+                {
+                        if(val & 0x200)
+                        {
+                                virt_addr = get_headland_addr(base_addr, &headland_ems_mr[headland_ems_mar & 0x3F]);
+                                if(index < 24) mem_mapping_disable(&headland_4000_9FFF_mapping[index]);
+                                if(virt_addr < (mem_size << 10)) mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + virt_addr);
+                                else mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], NULL);
+                                mem_mapping_enable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
+                                //pclog("Map page %d(address %05X) to address %07X(val=%04X)\n", index, base_addr, virt_addr, val);
+                        }
+                        else
+                        {
+                                mem_mapping_set_exec(&headland_ems_mapping[headland_ems_mar & 0x3F], ram + base_addr);
+                                mem_mapping_disable(&headland_ems_mapping[headland_ems_mar & 0x3F]);
+                                if(index < 24) mem_mapping_enable(&headland_4000_9FFF_mapping[index]);
+                                //pclog("Unmap page %d(address %05X)\n", index, base_addr);
+                        }
+                        flushmmucache();
+                }
+                if(headland_ems_mar & 0x80) headland_ems_mar++;
+                break;
+
+                default:
+                break;
         }
-        else
-                headland_index = val;
 }
 
 uint8_t headland_read(uint16_t addr, void *priv)
 {
-        if (addr & 1) 
+        uint8_t val;
+
+        switch(addr)
         {
+                case 0x22:
+                val = headland_index;
+                break;
+
+                case 0x23:
                 if ((headland_index >= 0xc0 || headland_index == 0x20) && cpu_iscyrix)
-                        return 0xff; /*Don't conflict with Cyrix config registers*/
+                        val = 0xff; /*Don't conflict with Cyrix config registers*/
-                return headland_regs[headland_index];
+                else
+                        val = headland_regs[headland_index];
+                break;
+
+                case 0x92:
+                val = headland_port_92 | 0xFC;
+                break;
+
+                case 0x1EC:
+                val = headland_ems_mr[headland_ems_mar & 0x3F];
+                if(headland_ems_mar & 0x80) headland_ems_mar++;
+                break;
+
+                case 0x1ED:
+                val = headland_cri;
+                break;
+
+                case 0x1EE:
+                val = headland_ems_mar;
+                break;
+
+                case 0x1EF:
+                switch(headland_cri)
+                {
+                        case 0:
+                        val = (headland_regs_cr[0] & 0x1F) | headland_mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
+                        break;
+                        case 1:
+                        val = (headland_regs_cr[1] & 0xBF) | headland_mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
+                        break;
+                        case 6:
+                        if(headland_regs_cr[4] & 0x80)
+                                val = (headland_regs_cr[6] & 0xFE) | (mem_size > 8192 ? 1 : 0);
+                        else
+                                val = 0;
+                        break;
+                        default:
+                        val = headland_regs_cr[headland_cri];
+                        break;
+                }
+                break;
+
+                default:
+                val = 0xFF;
+                break;
         }
-        return headland_index;
+
+        return val;
+}
+
+uint16_t headland_readw(uint16_t addr, void *priv)
+{
+        uint16_t val;
+
+        switch(addr)
+        {
+                case 0x1EC:
+                val = headland_ems_mr[headland_ems_mar & 0x3F] | ((headland_regs_cr[4] & 0x80) ? 0xF000 : 0xFC00);
+                if(headland_ems_mar & 0x80) headland_ems_mar++;
+                break;
+
+                default:
+                val = 0xFFFF;
+                break;
+        }
+
+        return val;
+}
+
+uint8_t mem_read_headlandb(uint32_t addr, void *priv)
+{
+        uint8_t val = 0xff;
+
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                val = ram[addr];
+
+        return val;
+}
+
+void mem_write_headlandb(uint32_t addr, uint8_t val, void *priv)
+{
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                  ram[addr] = val;
+}
+
+uint16_t mem_read_headlandw(uint32_t addr, void *priv)
+{
+        uint16_t val = 0xffff;
+
+        if((addr & 0x3FFF) == 0x3FFF) pclog("mem_read_headlandw(%08X, %p) called.\n", addr, priv);
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                val = *(uint16_t *)&ram[addr];
+
+        return val;
+}
+
+void mem_write_headlandw(uint32_t addr, uint16_t val, void *priv)
+{
+        if((addr & 0x3FFF) == 0x3FFF) pclog("mem_write_headlandw(%08X, %04X, %p) called.\n", addr, val, priv);
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                  *(uint16_t *)&ram[addr] = val;
+}
+
+uint32_t mem_read_headlandl(uint32_t addr, void *priv)
+{
+        uint32_t val = 0xffffffff;
+
+        if((addr & 0x3FFF) > 0x3FFC) pclog("mem_read_headlandl(%08X, %p) called.\n", addr, priv);
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                val = *(uint32_t *)&ram[addr];
+
+        return val;
+}
+
+void mem_write_headlandl(uint32_t addr, uint32_t val, void *priv)
+{
+        if((addr & 0x3FFF) > 0x3FFC) pclog("mem_write_headland(%08X, %08X, %p) called.\n", addr, val, priv);
+        addr = get_headland_addr(addr, priv);
+        if (addr < (mem_size << 10))
+                  *(uint32_t *)&ram[addr] = val;
 }
 
 void headland_init()
 {
-        io_sethandler(0x0022, 0x0002, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
+        int i;
+
+        for(i=0; i<8; i++)
+                headland_regs_cr[i] = 0;
+        headland_regs_cr[0] = 4;
+
+        switch(romset)
+        {
+                case ROM_AMI386SX:
+                // Remark - Previously distributed AMI386 BIOS doesn't seem to be for the Headland chipset. 
+                io_sethandler(0x0022, 0x0002, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
+                break;
+                case ROM_AMA932J:
+                headland_regs_cr[4] = 0x20;
+                io_sethandler(0x0092, 0x0001, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
+                break;
+                default:
+                headland_regs_cr[4] = 0;
+                break;
+        }
+
+        io_sethandler(0x01EC, 0x0001, headland_read, headland_readw, NULL, headland_write, headland_writew, NULL, NULL);
+        io_sethandler(0x01ED, 0x0003, headland_read, NULL, NULL, headland_write, NULL, NULL, NULL);
+
+        for(i=0; i<64; i++)
+                headland_ems_mr[i] = 0;
+
+        mem_mapping_disable(&ram_low_mapping);
+        mem_mapping_disable(&ram_mid_mapping);
+        mem_mapping_disable(&ram_high_mapping);
+
+        mem_mapping_add(&headland_low_mapping, 0, 0x40000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram, MEM_MAPPING_INTERNAL, NULL);
+
+        if(mem_size > 640)
+        {
+                mem_mapping_add(&headland_mid_mapping, 0xA0000, 0x60000, mem_read_headlandb,    mem_read_headlandw,    mem_read_headlandl,    mem_write_headlandb, mem_write_headlandw, mem_write_headlandl,   ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
+                mem_mapping_enable(&headland_mid_mapping);
+        }
+
+        if(mem_size > 1024)
+        {
+                mem_mapping_add(&headland_high_mapping, 0x100000, ((mem_size - 1024) * 1024), mem_read_headlandb,    mem_read_headlandw,    mem_read_headlandl,    mem_write_headlandb, mem_write_headlandw, mem_write_headlandl,   ram + 0x100000, MEM_MAPPING_INTERNAL, NULL);
+                mem_mapping_enable(&headland_high_mapping);
+        }
+
+        for (i = 0; i < 24; i++)
+        {
+                mem_mapping_add(&headland_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, mem_size > 256 + (i << 4) ? ram + 0x40000 + (i << 14) : NULL, MEM_MAPPING_INTERNAL, NULL);
+                mem_mapping_enable(&headland_4000_9FFF_mapping[i]);
+        }
+
+        for (i = 0; i < 64; i++)
+        {
+                headland_ems_mr[i] = 0;
+                mem_mapping_add(&headland_ems_mapping[i], ((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000, mem_read_headlandb, mem_read_headlandw, mem_read_headlandl, mem_write_headlandb, mem_write_headlandw, mem_write_headlandl, ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14), 0, &headland_ems_mr[i]);
+                mem_mapping_disable(&headland_ems_mapping[i]);
+        }
+
+        headland_memmap_state_update();
 }

src/i430fx.c

@@ -106,6 +106,30 @@ void i430fx_write(int func, int addr, uint8_t val, void *priv)
                         i430fx_map(0xec000, 0x04000, val >> 4);
                 pclog("i430fx_write : PAM6 write %02X\n", val);
                 break;
+
+                case 0x72: /*SMRAM*/
+                pclog("Write SMRAM %02x\n", val);
+                val = (val & 0x78) | 2; /*SMRAM always at A0000-BFFFF*/
+                val |= (card_i430fx[0x72] & 0x10); /*D_LCK can not be cleared by software*/
+                if (val & 0x10) /*D_LCK locks D_OPEN and G_SMRAME*/
+                {
+                        val &= ~0x48; /*D_OPEN is forced to 0, G_SMRAME is read only*/
+                        val |= (card_i430fx[0x72] & 0x08);
+                }
+                if ((card_i430fx[0x72] ^ val) & 0x40)
+                {
+                        if (val & 0x40) /*SMRAM enabled*/
+                        {
+                                pclog("Enable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        }
+                        else
+                        {
+                                pclog("Disable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        }
+                }
+                break;
         }
                 
         card_i430fx[addr] = val;
@@ -119,21 +143,15 @@ uint8_t i430fx_read(int func, int addr, void *priv)
         return card_i430fx[addr];
 }
 
-static uint8_t trc = 0;
+static void i430fx_smram_enable(void)
-
-void i430fx_trc_write(uint16_t port, uint8_t val, void *p)
 {
-        if ((val & 4) && !(trc & 4))
+        if (card_i430fx[0x72] & 8)
-        {
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
-                if (val & 2) /*Hard reset*/
+}
-                {
+static void i430fx_smram_disable(void)
-                        i430fx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/
+{
-                        keyboard_at_reset(); /*Reset keyboard controller to reset system flag*/
+        if (card_i430fx[0x72] & 8)
-                }
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
-                resetx86();
-        }
-                
-        trc = val;
 }
 
 void i430fx_init()
@@ -159,5 +177,11 @@ void i430fx_init()
 //        card_i430fx[0x74] = 0x0e;
 //        card_i430fx[0x78] = 0x23;
 
-        io_sethandler(0x0cf9, 0x0001, NULL, NULL, NULL, i430fx_trc_write, NULL, NULL, NULL);
+        smram_enable = i430fx_smram_enable;
+        smram_disable = i430fx_smram_disable;
+}
+
+void i430fx_reset()
+{
+        i430fx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/
 }

src/i430fx.h

@@ -1 +1,2 @@
 void i430fx_init();
+void i430fx_reset();

src/i430hx.c

@@ -0,0 +1,186 @@
+#include <string.h>
+
+#include "ibm.h"
+#include "io.h"
+#include "mem.h"
+#include "pci.h"
+
+#include "i430hx.h"
+
+static uint8_t card_i430hx[256];
+
+static void i430hx_map(uint32_t addr, uint32_t size, int state)
+{
+        switch (state & 3)
+        {
+                case 0:
+                mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                break;
+                case 1:
+                mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
+                break;
+                case 2:
+                mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
+                break;
+                case 3:
+                mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                break;
+        }
+        flushmmucache_nopc();        
+}
+
+void i430hx_write(int func, int addr, uint8_t val, void *priv)
+{
+        if (func)
+           return;
+           
+        if (addr >= 0x10 && addr < 0x4f)
+                return;
+                
+        switch (addr)
+        {
+                case 0x00: case 0x01: case 0x02: case 0x03:
+                case 0x08: case 0x09: case 0x0a: case 0x0b:
+                case 0x0c: case 0x0e:
+                return;
+                
+                case 0x04: /*Command register*/
+                val &= 0x02;
+                val |= 0x04;
+                break;
+                case 0x05:
+                val = 0;
+                break;
+                
+                case 0x06: /*Status*/
+                val = 0;
+                break;
+                case 0x07:
+                val &= 0x80;
+                val |= 0x02;
+                break;
+                
+                case 0x59: /*PAM0*/
+                if ((card_i430hx[0x59] ^ val) & 0xf0)
+                {
+                        i430hx_map(0xf0000, 0x10000, val >> 4);
+//                        shadowbios = (val & 0x10);
+                }
+                pclog("i430hx_write : PAM0 write %02X\n", val);
+                break;
+                case 0x5a: /*PAM1*/
+                if ((card_i430hx[0x5a] ^ val) & 0x0f)
+                        i430hx_map(0xc0000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5a] ^ val) & 0xf0)
+                        i430hx_map(0xc4000, 0x04000, val >> 4);
+                break;
+                case 0x5b: /*PAM2*/
+                if ((card_i430hx[0x5b] ^ val) & 0x0f)
+                        i430hx_map(0xc8000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5b] ^ val) & 0xf0)
+                        i430hx_map(0xcc000, 0x04000, val >> 4);
+                break;
+                case 0x5c: /*PAM3*/
+                if ((card_i430hx[0x5c] ^ val) & 0x0f)
+                        i430hx_map(0xd0000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5c] ^ val) & 0xf0)
+                        i430hx_map(0xd4000, 0x04000, val >> 4);
+                break;
+                case 0x5d: /*PAM4*/
+                if ((card_i430hx[0x5d] ^ val) & 0x0f)
+                        i430hx_map(0xd8000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5d] ^ val) & 0xf0)
+                        i430hx_map(0xdc000, 0x04000, val >> 4);
+                break;
+                case 0x5e: /*PAM5*/
+                if ((card_i430hx[0x5e] ^ val) & 0x0f)
+                        i430hx_map(0xe0000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5e] ^ val) & 0xf0)
+                        i430hx_map(0xe4000, 0x04000, val >> 4);
+                pclog("i430hx_write : PAM5 write %02X\n", val);
+                break;
+                case 0x5f: /*PAM6*/
+                if ((card_i430hx[0x5f] ^ val) & 0x0f)
+                        i430hx_map(0xe8000, 0x04000, val & 0xf);
+                if ((card_i430hx[0x5f] ^ val) & 0xf0)
+                        i430hx_map(0xec000, 0x04000, val >> 4);
+                pclog("i430hx_write : PAM6 write %02X\n", val);
+                break;
+
+                case 0x72: /*SMRAM*/
+                pclog("Write SMRAM %02x\n", val);
+                val = (val & 0x78) | 2; /*SMRAM always at A0000-BFFFF*/
+                val |= (card_i430hx[0x72] & 0x10); /*D_LCK can not be cleared by software*/
+                if (val & 0x10) /*D_LCK locks D_OPEN and G_SMRAME*/
+                {
+                        val &= ~0x48; /*D_OPEN is forced to 0, G_SMRAME is read only*/
+                        val |= (card_i430hx[0x72] & 0x08);
+                }
+                if ((card_i430hx[0x72] ^ val) & 0x40)
+                {
+                        if (val & 0x40) /*SMRAM enabled*/
+                        {
+                                pclog("Enable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        }
+                        else
+                        {
+                                pclog("Disable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        }
+                }
+                break;
+        }
+                
+        card_i430hx[addr] = val;
+}
+
+uint8_t i430hx_read(int func, int addr, void *priv)
+{
+        if (func)
+           return 0xff;
+
+        return card_i430hx[addr];
+}
+ 
+static void i430hx_smram_enable(void)
+{
+        if (card_i430hx[0x72] & 8)
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+}
+static void i430hx_smram_disable(void)
+{
+        if (card_i430hx[0x72] & 8)
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+}
+
+void i430hx_init()
+{
+        pci_add_specific(0, i430hx_read, i430hx_write, NULL);
+        
+        memset(card_i430hx, 0, 256);
+        card_i430hx[0x00] = 0x86; card_i430hx[0x01] = 0x80; /*Intel*/
+        card_i430hx[0x02] = 0x50; card_i430hx[0x03] = 0x12; /*82439HX*/
+        card_i430hx[0x04] = 0x06; card_i430hx[0x05] = 0x00;
+        card_i430hx[0x07] = 0x02;
+        card_i430hx[0x08] = 0x00; /*A0 stepping*/
+        card_i430hx[0x0B] = 0x06;
+        card_i430hx[0x51] = 0x20;
+        card_i430hx[0x52] = 0xB5; /*512kb cache*/
+        card_i430hx[0x56] = 0x52; /*DRAM control*/
+        card_i430hx[0x59] = 0x40; 
+        card_i430hx[0x5A] = card_i430hx[0x5B] = card_i430hx[0x5C] = card_i430hx[0x5D] = 0x44;
+        card_i430hx[0x5E] = card_i430hx[0x5F] = 0x44; 
+        card_i430hx[0x60] = card_i430hx[0x61] = card_i430hx[0x62] = card_i430hx[0x63] = 0x02;
+        card_i430hx[0x64] = card_i430hx[0x5F] = 0x02; 
+        card_i430hx[0x65] = card_i430hx[0x66] = card_i430hx[0x67] = 0x02;
+        card_i430hx[0x68] = 0x11;
+
+        smram_enable = i430hx_smram_enable;
+        smram_disable = i430hx_smram_disable;
+}
+
+void i430hx_reset()
+{
+        i430hx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/
+}

src/i430hx.h

@@ -0,0 +1,2 @@
+void i430hx_init();
+void i430hx_reset();

src/i430lx.c

@@ -1,10 +1,12 @@
 #include <string.h>
 
 #include "ibm.h"
+#include "ide.h"
 #include "io.h"
 #include "keyboard_at.h"
 #include "mem.h"
 #include "pci.h"
+#include "sio.h"
 #include "x86.h"
 
 #include "i430lx.h"
@@ -106,6 +108,30 @@ void i430lx_write(int func, int addr, uint8_t val, void *priv)
                         i430lx_map(0xec000, 0x04000, val >> 4);
                 pclog("i430lx_write : PAM6 write %02X\n", val);
                 break;
+
+                case 0x72: /*SMRAM*/
+                pclog("Write SMRAM %02x\n", val);
+                val = (val & 0x38) | 2; /*SMRAM always at A0000-BFFFF*/
+                val |= (card_i430lx[0x72] & 0x08); /*D_LCK can not be cleared by software*/
+                if (val & 0x08) /*D_LCK locks D_OPEN*/
+                {
+                        val &= ~0x20; /*D_OPEN is forced to 0*/
+                }
+                val |= (card_i430lx[0x72] & 0x08);
+                if ((card_i430lx[0x72] ^ val) & 0x20)
+                {
+                        if (val & 0x20) /*SMRAM enabled*/
+                        {
+                                pclog("Enable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        }
+                        else
+                        {
+                                pclog("Disable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        }
+                }
+                break;
         }
                 
         card_i430lx[addr] = val;
@@ -133,14 +159,27 @@ void i430lx_trc_write(uint16_t port, uint8_t val, void *p)
                 if (val & 2) /*Hard reset*/
                 {
                         i430lx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/
+                        card_i430lx[0x72] = 0; /*Also clear SMRAM register so BIOS will relocate SMBASE*/
                         keyboard_at_reset(); /*Reset keyboard controller to reset system flag*/
+                        ide_reset_devices();
+                        resetx86();
                 }
-                resetx86();
+                else
+                        softresetx86();
         }
 
         trc = val;
 }
 
+static void i430lx_smram_enable(void)
+{
+        mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+}
+static void i430lx_smram_disable(void)
+{
+        mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+}
+
 void i430lx_init()
 {
         pci_add_specific(0, i430lx_read, i430lx_write, NULL);
@@ -166,4 +205,7 @@ void i430lx_init()
 //        card_i430lx[0x78] = 0x23;
 
         io_sethandler(0x0cf9, 0x0001, i430lx_trc_read, NULL, NULL, i430lx_trc_write, NULL, NULL, NULL);
+
+        smram_enable = i430lx_smram_enable;
+        smram_disable = i430lx_smram_disable;
 }

src/i430vx.c

@@ -105,6 +105,30 @@ void i430vx_write(int func, int addr, uint8_t val, void *priv)
                         i430vx_map(0xec000, 0x04000, val >> 4);
                 pclog("i430vx_write : PAM6 write %02X\n", val);
                 break;
+
+                case 0x72: /*SMRAM*/
+                pclog("Write SMRAM %02x\n", val);
+                val = (val & 0x78) | 2; /*SMRAM always at A0000-BFFFF*/
+                val |= (card_i430vx[0x72] & 0x10); /*D_LCK can not be cleared by software*/
+                if (val & 0x10) /*D_LCK locks D_OPEN and G_SMRAME*/
+                {
+                        val &= ~0x48; /*D_OPEN is forced to 0, G_SMRAME is read only*/
+                        val |= (card_i430vx[0x72] & 0x08);
+                }
+                if ((card_i430vx[0x72] ^ val) & 0x40)
+                {
+                        if (val & 0x40) /*SMRAM enabled*/
+                        {
+                                pclog("Enable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+                        }
+                        else
+                        {
+                                pclog("Disable SMRAM\n");
+                                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+                        }
+                }
+                break;
         }
                 
         card_i430vx[addr] = val;
@@ -118,6 +142,16 @@ uint8_t i430vx_read(int func, int addr, void *priv)
         return card_i430vx[addr];
 }
  
+static void i430vx_smram_enable(void)
+{
+        if (card_i430vx[0x72] & 8)
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+}
+static void i430vx_smram_disable(void)
+{
+        if (card_i430vx[0x72] & 8)
+                mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
+}
 
 void i430vx_init()
 {
@@ -141,4 +175,12 @@ void i430vx_init()
         card_i430vx[0x72] = 0x02;
         card_i430vx[0x74] = 0x0e;
         card_i430vx[0x78] = 0x23;
+
+        smram_enable = i430vx_smram_enable;
+        smram_disable = i430vx_smram_disable;
+}
+
+void i430vx_reset()
+{
+        i430vx_write(0, 0x59, 0xf, NULL); /*Should reset all PCI devices, but just set PAM0 to point to ROM for now*/
 }