Implement non-extended-ALU extended writes on HT216-32. Fixes Windows 3.1 built-in Video 7 drivers.
This commit is contained in:
SarahW
parent
d49aab7782
commit
a5fc447950
1 changed files with 285 additions and 32 deletions
317
src/vid_ht216.c
317
src/vid_ht216.c
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@ -421,6 +421,233 @@ static inline uint8_t extalu(int op, uint8_t input_a, uint8_t input_b)
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return val;
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}
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static void ht216_dm_write(ht216_t *ht216, uint32_t addr, uint8_t cpu_dat, uint8_t cpu_dat_unexpanded)
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{
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svga_t *svga = &ht216->svga;
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uint8_t vala, valb, valc, vald, wm = svga->writemask;
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int writemask2 = svga->writemask;
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uint8_t fg_data[4] = {0,0,0,0};
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if (!(svga->gdcreg[6] & 1))
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svga->fullchange = 2;
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if (svga->chain4 || svga->fb_only)
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{
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writemask2=1<<(addr&3);
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addr&=~3;
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}
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else if (svga->chain2_write)
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{
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writemask2 &= ~0xa;
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if (addr & 1)
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writemask2 <<= 1;
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addr &= ~1;
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addr <<= 2;
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}
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else
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{
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addr<<=2;
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}
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if (addr >= svga->vram_max)
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return;
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svga->changedvram[addr >> 12]=changeframecount;
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switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBMC)
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{
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case 0x00:
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fg_data[0] = fg_data[1] = fg_data[2] = fg_data[3] = cpu_dat;
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break;
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case 0x04:
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if (ht216->ht_regs[0xfe] & HT_REG_FE_FBRC)
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{
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if (addr & 4)
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{
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fg_data[0] = (cpu_dat_unexpanded & (1 << (((addr + 4) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[1] = (cpu_dat_unexpanded & (1 << (((addr + 5) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[2] = (cpu_dat_unexpanded & (1 << (((addr + 6) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[3] = (cpu_dat_unexpanded & (1 << (((addr + 7) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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}
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else
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{
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fg_data[0] = (cpu_dat_unexpanded & (1 << (((addr + 0) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[1] = (cpu_dat_unexpanded & (1 << (((addr + 1) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[2] = (cpu_dat_unexpanded & (1 << (((addr + 2) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[3] = (cpu_dat_unexpanded & (1 << (((addr + 3) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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}
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}
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else
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{
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if (addr & 4)
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{
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fg_data[0] = (ht216->ht_regs[0xf5] & (1 << (((addr + 4) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[1] = (ht216->ht_regs[0xf5] & (1 << (((addr + 5) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[2] = (ht216->ht_regs[0xf5] & (1 << (((addr + 6) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[3] = (ht216->ht_regs[0xf5] & (1 << (((addr + 7) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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}
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else
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{
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fg_data[0] = (ht216->ht_regs[0xf5] & (1 << (((addr + 0) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[1] = (ht216->ht_regs[0xf5] & (1 << (((addr + 1) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[2] = (ht216->ht_regs[0xf5] & (1 << (((addr + 2) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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fg_data[3] = (ht216->ht_regs[0xf5] & (1 << (((addr + 3) & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
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}
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}
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break;
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case 0x08:
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fg_data[0] = ht216->ht_regs[0xec];
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fg_data[1] = ht216->ht_regs[0xed];
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fg_data[2] = ht216->ht_regs[0xee];
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fg_data[3] = ht216->ht_regs[0xef];
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break;
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case 0x0c:
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fg_data[0] = ht216->ht_regs[0xec];
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fg_data[1] = ht216->ht_regs[0xed];
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fg_data[2] = ht216->ht_regs[0xee];
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fg_data[3] = ht216->ht_regs[0xef];
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break;
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}
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switch (svga->writemode)
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{
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case 1:
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if (writemask2 & 1) svga->vram[addr] = svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = svga->ld;
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break;
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case 0:
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if (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled))
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{
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if (writemask2 & 1) svga->vram[addr] = fg_data[0];
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if (writemask2 & 2) svga->vram[addr | 0x1] = fg_data[1];
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if (writemask2 & 4) svga->vram[addr | 0x2] = fg_data[2];
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if (writemask2 & 8) svga->vram[addr | 0x3] = fg_data[3];
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}
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else
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{
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if (svga->gdcreg[1] & 1) vala = (svga->gdcreg[0] & 1) ? 0xff : 0;
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else vala = fg_data[0];
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if (svga->gdcreg[1] & 2) valb = (svga->gdcreg[0] & 2) ? 0xff : 0;
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else valb = fg_data[1];
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if (svga->gdcreg[1] & 4) valc = (svga->gdcreg[0] & 4) ? 0xff : 0;
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else valc = fg_data[2];
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if (svga->gdcreg[1] & 8) vald = (svga->gdcreg[0] & 8) ? 0xff : 0;
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else vald = fg_data[3];
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switch (svga->gdcreg[3] & 0x18)
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{
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case 0: /*Set*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | (svga->la & ~svga->gdcreg[8]);
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | (svga->lb & ~svga->gdcreg[8]);
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | (svga->lc & ~svga->gdcreg[8]);
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | (svga->ld & ~svga->gdcreg[8]);
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break;
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case 8: /*AND*/
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if (writemask2 & 1) svga->vram[addr] = (vala | ~svga->gdcreg[8]) & svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb | ~svga->gdcreg[8]) & svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc | ~svga->gdcreg[8]) & svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald | ~svga->gdcreg[8]) & svga->ld;
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break;
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case 0x10: /*OR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | svga->ld;
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break;
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case 0x18: /*XOR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) ^ svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) ^ svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) ^ svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) ^ svga->ld;
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break;
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}
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// pclog("- %02X %02X %02X %02X %08X\n",vram[addr],vram[addr|0x1],vram[addr|0x2],vram[addr|0x3],addr);
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}
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break;
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case 2:
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if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled))
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{
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if (writemask2 & 1) svga->vram[addr] = (((cpu_dat & 1) ? 0xff : 0) & svga->gdcreg[8]) | (svga->la & ~svga->gdcreg[8]);
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if (writemask2 & 2) svga->vram[addr | 0x1] = (((cpu_dat & 2) ? 0xff : 0) & svga->gdcreg[8]) | (svga->lb & ~svga->gdcreg[8]);
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if (writemask2 & 4) svga->vram[addr | 0x2] = (((cpu_dat & 4) ? 0xff : 0) & svga->gdcreg[8]) | (svga->lc & ~svga->gdcreg[8]);
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if (writemask2 & 8) svga->vram[addr | 0x3] = (((cpu_dat & 8) ? 0xff : 0) & svga->gdcreg[8]) | (svga->ld & ~svga->gdcreg[8]);
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}
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else
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{
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vala = ((cpu_dat & 1) ? 0xff : 0);
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valb = ((cpu_dat & 2) ? 0xff : 0);
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valc = ((cpu_dat & 4) ? 0xff : 0);
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vald = ((cpu_dat & 8) ? 0xff : 0);
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switch (svga->gdcreg[3] & 0x18)
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{
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case 0: /*Set*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | (svga->la & ~svga->gdcreg[8]);
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | (svga->lb & ~svga->gdcreg[8]);
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | (svga->lc & ~svga->gdcreg[8]);
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | (svga->ld & ~svga->gdcreg[8]);
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break;
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case 8: /*AND*/
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if (writemask2 & 1) svga->vram[addr] = (vala | ~svga->gdcreg[8]) & svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb | ~svga->gdcreg[8]) & svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc | ~svga->gdcreg[8]) & svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald | ~svga->gdcreg[8]) & svga->ld;
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break;
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case 0x10: /*OR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | svga->ld;
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break;
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case 0x18: /*XOR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) ^ svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) ^ svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) ^ svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) ^ svga->ld;
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break;
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}
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}
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break;
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case 3:
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wm = svga->gdcreg[8];
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svga->gdcreg[8] &= cpu_dat;
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vala = (svga->gdcreg[0] & 1) ? 0xff : 0;
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valb = (svga->gdcreg[0] & 2) ? 0xff : 0;
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valc = (svga->gdcreg[0] & 4) ? 0xff : 0;
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vald = (svga->gdcreg[0] & 8) ? 0xff : 0;
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switch (svga->gdcreg[3] & 0x18)
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{
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case 0: /*Set*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | (svga->la & ~svga->gdcreg[8]);
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | (svga->lb & ~svga->gdcreg[8]);
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | (svga->lc & ~svga->gdcreg[8]);
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | (svga->ld & ~svga->gdcreg[8]);
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break;
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case 8: /*AND*/
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if (writemask2 & 1) svga->vram[addr] = (vala | ~svga->gdcreg[8]) & svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb | ~svga->gdcreg[8]) & svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc | ~svga->gdcreg[8]) & svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald | ~svga->gdcreg[8]) & svga->ld;
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break;
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case 0x10: /*OR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) | svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) | svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) | svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) | svga->ld;
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break;
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case 0x18: /*XOR*/
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if (writemask2 & 1) svga->vram[addr] = (vala & svga->gdcreg[8]) ^ svga->la;
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if (writemask2 & 2) svga->vram[addr | 0x1] = (valb & svga->gdcreg[8]) ^ svga->lb;
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if (writemask2 & 4) svga->vram[addr | 0x2] = (valc & svga->gdcreg[8]) ^ svga->lc;
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if (writemask2 & 8) svga->vram[addr | 0x3] = (vald & svga->gdcreg[8]) ^ svga->ld;
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break;
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}
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svga->gdcreg[8] = wm;
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break;
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}
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}
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static void ht216_dm_extalu_write(ht216_t *ht216, uint32_t addr, uint8_t cpu_dat, uint8_t bit_mask, uint8_t cpu_dat_unexpanded, uint8_t rop_select)
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{
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/*Input B = CD.5
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@ -488,42 +715,49 @@ static void ht216_write_common(ht216_t *ht216, uint32_t addr, uint8_t val)
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01 = Bit mask (3CF:8)
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1x = (3C4:F5)
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*/
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uint8_t bit_mask = 0, rop_select = 0;
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svga_t *svga = &ht216->svga;
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cycles -= video_timing_write_b;
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cycles_lost += video_timing_write_b;
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egawrites++;
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addr &= 0xfffff;
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// pclog("%08X %02x %08x\n", addr, svga->gdcreg[6], svga->banked_mask);
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val = svga_rotate[svga->gdcreg[3] & 7][val];
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switch (ht216->ht_regs[0xcd] & HT_REG_CD_BMSKSL)
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{
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case 0x00:
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bit_mask = svga->gdcreg[8];
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break;
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case 0x04:
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bit_mask = val;
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break;
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case 0x08: case 0x0c:
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bit_mask = ht216->ht_regs[0xf5];
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break;
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}
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switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBRSL)
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{
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case 0x00:
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rop_select = val;
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break;
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case 0x10:
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rop_select = svga->gdcreg[8];
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break;
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case 0x20: case 0x30:
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rop_select = ht216->ht_regs[0xf5];
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break;
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}
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if (ht216->ht_regs[0xcd] & HT_REG_CD_EXALU) /*Extended ALU*/
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{
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uint8_t bit_mask = 0, rop_select = 0;
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switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBRSL)
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{
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case 0x00:
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rop_select = val;
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break;
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case 0x10:
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rop_select = svga->gdcreg[8];
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break;
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case 0x20: case 0x30:
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rop_select = ht216->ht_regs[0xf5];
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break;
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}
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switch (ht216->ht_regs[0xcd] & HT_REG_CD_BMSKSL)
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{
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case 0x00:
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bit_mask = svga->gdcreg[8];
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break;
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case 0x04:
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bit_mask = val;
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break;
|
||||
case 0x08: case 0x0c:
|
||||
bit_mask = ht216->ht_regs[0xf5];
|
||||
break;
|
||||
}
|
||||
|
||||
if (ht216->ht_regs[0xcd] & HT_REG_CD_FP8PCEXP) /*1->8 bit expansion*/
|
||||
{
|
||||
addr = (addr << 3) & 0xfffff;
|
||||
|
|
@ -539,6 +773,23 @@ static void ht216_write_common(ht216_t *ht216, uint32_t addr, uint8_t val)
|
|||
else
|
||||
ht216_dm_extalu_write(ht216, addr, val, bit_mask, val, rop_select);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (ht216->ht_regs[0xcd] & HT_REG_CD_FP8PCEXP) /*1->8 bit expansion*/
|
||||
{
|
||||
addr = (addr << 3) & 0xfffff;
|
||||
ht216_dm_write(ht216, addr, (val & 0x80) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 1, (val & 0x40) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 2, (val & 0x20) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 3, (val & 0x10) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 4, (val & 0x08) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 5, (val & 0x04) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 6, (val & 0x02) ? 0xff : 0, val);
|
||||
ht216_dm_write(ht216, addr + 7, (val & 0x01) ? 0xff : 0, val);
|
||||
}
|
||||
else
|
||||
ht216_dm_write(ht216, addr, val, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void ht216_write(uint32_t addr, uint8_t val, void *p)
|
||||
|
|
@ -552,10 +803,12 @@ static void ht216_write(uint32_t addr, uint8_t val, void *p)
|
|||
addr &= svga->banked_mask;
|
||||
addr = (addr & 0x7fff) + ht216->write_bank[(addr >> 15) & 1];
|
||||
// pclog("phys_addr=%05x\n", addr);
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_write_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
{
|
||||
ht216_write_common(ht216, addr, val);
|
||||
}
|
||||
}
|
||||
static void ht216_writew(uint32_t addr, uint16_t val, void *p)
|
||||
{
|
||||
|
|
@ -564,7 +817,7 @@ static void ht216_writew(uint32_t addr, uint16_t val, void *p)
|
|||
|
||||
addr &= svga->banked_mask;
|
||||
addr = (addr & 0x7fff) + ht216->write_bank[(addr >> 15) & 1];
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_writew_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
{
|
||||
|
|
@ -579,7 +832,7 @@ static void ht216_writel(uint32_t addr, uint32_t val, void *p)
|
|||
|
||||
addr &= svga->banked_mask;
|
||||
addr = (addr & 0x7fff) + ht216->write_bank[(addr >> 15) & 1];
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_writel_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
{
|
||||
|
|
@ -598,7 +851,7 @@ static void ht216_write_linear(uint32_t addr, uint8_t val, void *p)
|
|||
if (!svga->chain4) /*Bits 16 and 17 of linear address seem to be unused in planar modes*/
|
||||
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
|
||||
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_write_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
ht216_write_common(ht216, addr, val);
|
||||
|
|
@ -611,7 +864,7 @@ static void ht216_writew_linear(uint32_t addr, uint16_t val, void *p)
|
|||
if (!svga->chain4)
|
||||
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
|
||||
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_writew_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
{
|
||||
|
|
@ -627,7 +880,7 @@ static void ht216_writel_linear(uint32_t addr, uint32_t val, void *p)
|
|||
if (!svga->chain4)
|
||||
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
|
||||
|
||||
if (!ht216->ht_regs[0xcd])
|
||||
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
|
||||
svga_writel_linear(addr, val, &ht216->svga);
|
||||
else
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue