SarahW
50e7de5214
Merge from trunk
2019-04-18 20:46:38 +01:00
SarahW
84a098bc98
Add read-only cassette emulation to IBM 5150 PC. Patch from JohnElliott.
2019-04-17 20:37:23 +01:00
SarahW
18a293d5cc
Flush MMU cache on CPU soft reset. Fixes hang on reset under some configurations.
2019-04-14 21:40:32 +01:00
SarahW
73c20a723f
Clear integer registers on CPU reset. Fixes hang on reboot on VA-503+.
2019-04-10 20:28:45 +01:00
SarahW
03b5a44aca
More CPU sanitisation.
2019-02-08 21:17:56 +00:00
SarahW
5b58b202a1
More CPU sanitisation.
2019-02-07 22:10:34 +00:00
SarahW
dd68b19f0a
Second CPU sanitising pass.
2019-02-07 21:53:44 +00:00
SarahW
1af0b660b3
First pass at sanitising CPU headers.
2019-02-07 21:30:53 +00:00
SarahW
3c2dbf063e
Remove unused and superfluous variables from mem.c.
2019-02-07 20:23:14 +00:00
SarahW
87031d4d09
Remove readmemb386l() and writememb386l().
2019-02-07 20:18:03 +00:00
SarahW
ca89a51478
Remove redundant oldcs variable - when processing an exception, oldcs and CS are the same.
2019-01-28 20:00:49 +00:00
SarahW
a4d3aa1912
Move flags and eflags variables into cpu_struct.
2018-11-28 09:42:04 +00:00
SarahW
a7d006b637
Rewrote timer code.
...
The new code is based on timestamps, rather than delays. This eliminates the
need to update every timer in timer_process(), which cost a non-trivial amount
of CPU time on low-end machines.
This involved changes to every user of the timer code, so this change almost
certainly introduces bugs.
2018-08-02 22:06:10 +01:00
SarahW
91143d3c68
Move CPU segment structures into cpu_state structure.
2018-07-22 12:56:03 +01:00
SarahW
0f0a1c3223
Perform NULL segment checks upfront in opcode handlers, rather than on every memory access.
...
This removes the need to pass the segment to readmem*l()/writemem*l().
2018-07-18 22:10:18 +01:00
SarahW
056eefb196
Reset internal cache status correctly on soft CPU reset. Fixes CPU speed detection on Elonex PC-425X.
2018-04-19 22:00:33 +01:00
SarahW
919f2dd45d
Implemented CMPXCHG8B on Winchip. Patch from nerd73.
2018-03-03 21:32:56 +00:00
SarahW
b60eff610d
Fix IDT limit on reset. Patch from Greatpsycho.
2018-01-08 20:51:06 +00:00
SarahW
8a5b552a9a
Correct CS:IP initialisation on 286+ reset. Patch from Greatpsycho.
2018-01-08 20:50:48 +00:00
SarahW
bb4fbdd9c2
Fixed >32 bit shifts on 808x CPUs. Fixes Titus the Fox.
2017-11-05 17:17:58 +00:00
SarahW
354d52754c
Indentation fixes. Patch from basic2004.
2017-07-30 08:31:03 +01:00
SarahW
807b710a5d
Improvements to path handling. Patch from bit.
2017-07-06 21:25:10 +01:00
SarahW
1f33b52451
Added VME emulation to Intel DX4, Pentium and Pentium MMX.
...
Temporarily disabled recompilation of CLI and STI.
2017-06-30 20:42:19 +01:00
SarahW
083ca3d4a2
Slight optimisation when DS/SS are 'flat' (base=0, limit=4G).
2017-05-24 21:50:37 +01:00
SarahW
e09d483cf5
Fixed typo in 808x cycle count. Patch from hOMER247.
2017-05-06 18:36:09 +01:00
SarahW
4cb5ddd7f7
Implemented undocumented F6/1 and F7/1 TEST instructions.
...
Implemented undocumented F1 LOCK and ICEBP instructions.
Implemented missing 286 LOADALL functionality.
SMSW now sets all 12 bits to 1 on 286.
Patch from Greatpsycho.
2017-04-28 18:47:38 +01:00
SarahW
f41ad36111
Inline functions in 808x.c marked as static. Patch from AmatCoder.
2017-04-19 16:23:43 +01:00
SarahW
8c7959b3d5
Fixed an additional warning.
2017-04-11 19:53:06 +01:00
SarahW
2b892d2a7a
Fixed compiler warnings for Windows builds.
...
Added -Werror to Windows makefiles.
2017-04-11 19:34:41 +01:00
SarahW
6d1492ca05
Set EAX to 0 on CPU reset - fixes hang with hard reset on PS/2.
2017-04-09 14:51:27 +01:00
SarahW
9c1d8e5022
Add PS/2 Model 50 emulation.
...
This commit also adds basic MCA emulation.
This commit also adds emulation of the PS/2 Type 1 DMA controller.
2017-04-06 22:00:40 +01:00
SarahW
bfc69a4bea
Cleaned up ibm.h a bit
2016-11-28 20:06:17 +00:00
SarahW
1b73963997
Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.
2016-11-25 21:32:02 +00:00
SarahW
3df46b4479
Memory addressing on XT now wraps at 1MB.
2016-10-09 08:53:04 +01:00
SarahW
eb126fd822
Moved more variables into cpu_state structure.
2016-08-21 21:28:23 +01:00
SarahW
c664682758
Move some more variables into cpu_state structure. Minor speedup (~2%).
2016-08-17 21:28:16 +01:00
SarahW
535604b760
Pack decoded ModR/M data into a single word - minor recompiler speedup.
2016-08-14 16:29:54 +01:00
SarahW
c81a91fd72
Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).
2016-04-20 21:39:41 +01:00
TomW
673a3527af
Don't cause illegal instruction exception on unknown REP instruction. Patch from Battler.
2016-03-17 21:47:56 +00:00
TomW
4a0ece4e75
Added 8088/8086 instruction aliases. Patch from Battler.
2016-01-04 20:47:28 +00:00
TomW
79202cc5c0
Changed timer base frequency on XT models to 14.318MHz - PIT, CGA and 4.77MHz CPU should now stay in perfect sync.
2015-11-25 21:50:38 +00:00
TomW
0b06c15ae5
Added missing SETALC instruction to 808x.c
2015-11-25 21:25:21 +00:00
TomW
3d35442da7
Removed duplicate PIT counting from 808x.c - fixes some timing issues with XT machines.
2015-11-25 21:25:01 +00:00
TomW
c47df21a82
XT models can now have less than 640kB RAM.
2015-11-18 20:28:57 +00:00
TomW
2efc56e882
Reset triggered by keyboard controller should now be handled correctly by dynamic recompiler.
2015-08-31 19:31:23 +01:00
TomW
f339f00315
Interpreter and dynamic recompiler now present in a single binary.
2015-08-21 20:55:36 +01:00
TomW
08254b8dfb
Initial 64-bit recompiler.
...
Various 64-bit fixes.
Various fixes to allow building under MinGW-w64.
2015-07-18 12:11:54 +01:00
TomW
6bc394b4c6
Recompiler now handles reset caused by a newly generated codeblock.
2015-07-12 15:22:58 +01:00
TomW
b4592cdea3
Implemented new memory mapping to improve performance of self modifying code.
...
New scheme allows code blocks to cross pages.
Reduced code block size down to 2kB.
2015-01-28 21:58:02 +00:00
TomW
4676daade4
Initial commit of dynamic recompiler.
...
Various CPU changes to support dynamic recompiler.
2014-11-05 21:24:16 +00:00