Moved more variables into cpu_state structure.
This commit is contained in:
SarahW
parent
c664682758
commit
eb126fd822
50 changed files with 1454 additions and 1481 deletions
22
src/386.c
22
src/386.c
|
|
@ -46,7 +46,7 @@ uint32_t rmdat32;
|
|||
#define fetchdat rmdat32
|
||||
uint32_t backupregs[16];
|
||||
extern int oddeven;
|
||||
int inttype,abrt;
|
||||
int inttype;
|
||||
|
||||
|
||||
uint32_t oldcs2;
|
||||
|
|
@ -172,8 +172,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
|
|||
}
|
||||
}
|
||||
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 0; }
|
||||
#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 0
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (cpu_state.abrt) return 0; }
|
||||
#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (cpu_state.abrt) return 0
|
||||
|
||||
#include "x86_flags.h"
|
||||
|
||||
|
|
@ -246,7 +246,7 @@ dontprint=0;
|
|||
opcodestart:
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
|
||||
if (!abrt)
|
||||
if (!cpu_state.abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
opcode = fetchdat & 0xFF;
|
||||
|
|
@ -262,7 +262,7 @@ opcodestart:
|
|||
|
||||
if (!use32) cpu_state.pc &= 0xffff;
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
flags_rebuild();
|
||||
// pclog("Abort\n");
|
||||
|
|
@ -276,19 +276,19 @@ opcodestart:
|
|||
if (testr[6]!=EBP) pclog("EBP corrupted %08X\n",pc);
|
||||
if (testr[7]!=ESP) pclog("ESP corrupted %08X\n",pc);*/
|
||||
/* if (testr[8]!=flags) pclog("FLAGS corrupted %08X\n",pc);*/
|
||||
tempi = abrt;
|
||||
abrt = 0;
|
||||
tempi = cpu_state.abrt;
|
||||
cpu_state.abrt = 0;
|
||||
x86_doabrt(tempi);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
abrt = 0;
|
||||
cpu_state.abrt = 0;
|
||||
CS = oldcs;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
pclog("Double fault %i\n", ins);
|
||||
pmodeint(8, 0);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
abrt = 0;
|
||||
cpu_state.abrt = 0;
|
||||
softresetx86();
|
||||
pclog("Triple fault - reset\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ extern uint16_t ea_rseg;
|
|||
#define check_io_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
|
||||
{ \
|
||||
int tempi = checkio(port); \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
if (tempi) \
|
||||
{ \
|
||||
x86gpf(NULL,0); \
|
||||
|
|
@ -28,7 +28,7 @@ extern uint16_t ea_rseg;
|
|||
#define checkio_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
|
||||
{ \
|
||||
tempi = checkio(port); \
|
||||
if (abrt) break; \
|
||||
if (cpu_state.abrt) break; \
|
||||
if (tempi) \
|
||||
{ \
|
||||
x86gpf(NULL,0); \
|
||||
|
|
@ -74,7 +74,7 @@ static inline uint8_t fastreadb(uint32_t a)
|
|||
if ((a >> 12) == pccache)
|
||||
return *((uint8_t *)&pccache2[a]);
|
||||
t = getpccache(a);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return;
|
||||
pccache = a >> 12;
|
||||
pccache2 = t;
|
||||
|
|
@ -93,7 +93,7 @@ static inline uint16_t fastreadw(uint32_t a)
|
|||
}
|
||||
if ((a>>12)==pccache) return *((uint16_t *)&pccache2[a]);
|
||||
t = getpccache(a);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return;
|
||||
|
||||
pccache = a >> 12;
|
||||
|
|
@ -110,7 +110,7 @@ static inline uint32_t fastreadl(uint32_t a)
|
|||
if ((a>>12)!=pccache)
|
||||
{
|
||||
t = getpccache(a);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return 0;
|
||||
pccache2 = t;
|
||||
pccache=a>>12;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ int cpu_reps, cpu_reps_latched;
|
|||
int cpu_notreps, cpu_notreps_latched;
|
||||
|
||||
int inrecomp = 0;
|
||||
int cpu_recomp_blocks, cpu_recomp_ins, cpu_recomp_full_ins, cpu_new_blocks;
|
||||
int cpu_recomp_blocks, cpu_recomp_full_ins, cpu_new_blocks;
|
||||
int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latched, cpu_new_blocks_latched;
|
||||
|
||||
int cpu_block_end = 0;
|
||||
|
|
@ -52,7 +52,7 @@ uint16_t biosmask;
|
|||
uint32_t rmdat32;
|
||||
uint32_t backupregs[16];
|
||||
int oddeven=0;
|
||||
int inttype,abrt;
|
||||
int inttype;
|
||||
|
||||
|
||||
uint32_t oldcs2;
|
||||
|
|
@ -178,8 +178,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
|
|||
}
|
||||
}
|
||||
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
|
||||
#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 1
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (cpu_state.abrt) return 1; }
|
||||
#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (cpu_state.abrt) return 1
|
||||
|
||||
#include "x86_flags.h"
|
||||
|
||||
|
|
@ -349,7 +349,7 @@ int rep386(int fv)
|
|||
checkio_perm(DX);
|
||||
temp2=inb(DX);
|
||||
writememb(es,DI,temp2);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
|
|
@ -365,7 +365,7 @@ int rep386(int fv)
|
|||
checkio_perm(DX);
|
||||
temp2=inb(DX);
|
||||
writememb(es,EDI,temp2);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
|
|
@ -381,7 +381,7 @@ int rep386(int fv)
|
|||
// pclog("REP INSW %04x %04x:%04x %04x\n", DX, ES, DI, CX);
|
||||
tempw=inw(DX);
|
||||
writememw(es,DI,tempw);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
|
|
@ -396,7 +396,7 @@ int rep386(int fv)
|
|||
{
|
||||
templ=inl(DX);
|
||||
writememl(es,DI,templ);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
|
|
@ -411,7 +411,7 @@ int rep386(int fv)
|
|||
{
|
||||
tempw=inw(DX);
|
||||
writememw(es,EDI,tempw);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
|
|
@ -426,7 +426,7 @@ int rep386(int fv)
|
|||
{
|
||||
templ=inl(DX);
|
||||
writememl(es,EDI,templ);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
|
|
@ -440,7 +440,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
if (flags&D_FLAG) SI--;
|
||||
|
|
@ -456,7 +456,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
if (flags&D_FLAG) ESI--;
|
||||
|
|
@ -472,7 +472,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
// pclog("OUTSW %04X -> %04X\n",SI,tempw);
|
||||
outw(DX,tempw);
|
||||
if (flags&D_FLAG) SI-=2;
|
||||
|
|
@ -488,7 +488,7 @@ int rep386(int fv)
|
|||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
outl(DX, templ);
|
||||
if (flags & D_FLAG) SI -= 4;
|
||||
else SI += 4;
|
||||
|
|
@ -503,7 +503,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
outw(DX,tempw);
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
|
|
@ -518,7 +518,7 @@ int rep386(int fv)
|
|||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
outl(DX, templ);
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
else ESI += 4;
|
||||
|
|
@ -536,8 +536,8 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
writememb(es,DI,temp2); if (abrt) break;
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
writememb(es,DI,temp2); if (cpu_state.abrt) break;
|
||||
// if (output==3) pclog("MOVSB %08X:%04X -> %08X:%04X %02X\n",ds,SI,es,DI,temp2);
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
|
|
@ -555,8 +555,8 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
writememb(es,EDI,temp2); if (abrt) break;
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
writememb(es,EDI,temp2); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
c--;
|
||||
|
|
@ -573,8 +573,8 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
writememw(es,DI,tempw); if (abrt) break;
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
writememw(es,DI,tempw); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { DI-=2; SI-=2; }
|
||||
else { DI+=2; SI+=2; }
|
||||
c--;
|
||||
|
|
@ -591,9 +591,9 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
|
||||
// pclog("MOVSD %08X from %08X to %08X (%04X:%08X)\n", templ, ds+SI, es+DI, CS, pc);
|
||||
writememl(es,DI,templ); if (abrt) break;
|
||||
writememl(es,DI,templ); if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
else { DI+=4; SI+=4; }
|
||||
c--;
|
||||
|
|
@ -610,8 +610,8 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
writememw(es,EDI,tempw); if (abrt) break;
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
writememw(es,EDI,tempw); if (cpu_state.abrt) break;
|
||||
// if (output) pclog("Written %04X from %08X to %08X %i %08X %04X %08X %04X\n",tempw,ds+ESI,es+EDI,c,ds,ES,es,ES);
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
else { EDI+=2; ESI+=2; }
|
||||
|
|
@ -629,9 +629,9 @@ int rep386(int fv)
|
|||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
|
||||
// if ((EDI&0xFFFF0000)==0xA0000) cycles-=12;
|
||||
writememl(es,EDI,templ); if (abrt) break;
|
||||
writememl(es,EDI,templ); if (cpu_state.abrt) break;
|
||||
// if (output) pclog("Load %08X from %08X to %08X %04X %08X %04X %08X\n",templ,ESI,EDI,DS,ds,ES,es);
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
else { EDI+=4; ESI+=4; }
|
||||
|
|
@ -652,7 +652,7 @@ int rep386(int fv)
|
|||
{
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI);
|
||||
temp2=readmemb(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
c--;
|
||||
|
|
@ -670,7 +670,7 @@ int rep386(int fv)
|
|||
{
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
temp2=readmemb(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
c--;
|
||||
|
|
@ -691,7 +691,7 @@ int rep386(int fv)
|
|||
tempw2=readmemw(es,DI);
|
||||
// pclog("%04X %04X %c%c %c%c\n", tempw, tempw2, tempw & 0xff, tempw >> 8, tempw2 & 0xff, tempw2 >> 8);
|
||||
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI-=2; SI-=2; }
|
||||
else { DI+=2; SI+=2; }
|
||||
c--;
|
||||
|
|
@ -709,7 +709,7 @@ int rep386(int fv)
|
|||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
|
||||
templ2=readmeml(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
else { DI+=4; SI+=4; }
|
||||
c--;
|
||||
|
|
@ -727,7 +727,7 @@ int rep386(int fv)
|
|||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
tempw2=readmemw(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
else { EDI+=2; ESI+=2; }
|
||||
c--;
|
||||
|
|
@ -745,7 +745,7 @@ int rep386(int fv)
|
|||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
templ2=readmeml(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
else { EDI+=4; ESI+=4; }
|
||||
c--;
|
||||
|
|
@ -762,7 +762,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
writememb(es,DI,AL);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
|
|
@ -780,7 +780,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
writememb(es,EDI,AL);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
|
|
@ -798,7 +798,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
writememw(es,DI,AX);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
|
|
@ -816,7 +816,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
writememw(es,EDI,AX);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
|
|
@ -834,7 +834,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
writememl(es,DI,EAX);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
|
|
@ -852,7 +852,7 @@ int rep386(int fv)
|
|||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
writememl(es,EDI,EAX);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
|
|
@ -871,7 +871,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI--;
|
||||
else SI++;
|
||||
c--;
|
||||
|
|
@ -886,7 +886,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
c--;
|
||||
|
|
@ -901,7 +901,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=2;
|
||||
else SI+=2;
|
||||
c--;
|
||||
|
|
@ -916,7 +916,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=4;
|
||||
else SI+=4;
|
||||
c--;
|
||||
|
|
@ -931,7 +931,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
c--;
|
||||
|
|
@ -946,7 +946,7 @@ int rep386(int fv)
|
|||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=4;
|
||||
else ESI+=4;
|
||||
c--;
|
||||
|
|
@ -963,7 +963,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI--;
|
||||
|
|
@ -986,7 +986,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
// if (output) pclog("Compare %02X,%02X\n",temp2,AL);
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
|
|
@ -1009,7 +1009,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
|
|
@ -1031,7 +1031,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
|
|
@ -1053,7 +1053,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
|
|
@ -1075,7 +1075,7 @@ int rep386(int fv)
|
|||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
|
|
@ -1100,7 +1100,7 @@ int rep386(int fv)
|
|||
if (rep32&0x200) ECX=c;
|
||||
else CX=c;
|
||||
CPU_BLOCK_END();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
//pclog("rep cpu_block_end=%d %p\n", cpu_block_end, (void *)&cpu_block_end);
|
||||
// if (output) pclog("%03X %03X\n",rep32,use32);
|
||||
}
|
||||
|
|
@ -1113,7 +1113,7 @@ int checkio(int port)
|
|||
t = readmemw(tr.base, 0x66);
|
||||
cpl_override = 0;
|
||||
// pclog("CheckIO 1 %08X %04x %02x\n",tr.base, eflags, _cs.access);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
// pclog("CheckIO %04X %01X %01X %02X %04X %04X %08X ",CS,CPL,IOPL,port,t,t+(port>>3),tr.base+t+(port>>3));
|
||||
if ((t+(port>>3))>tr.limit) return 1;
|
||||
cpl_override = 1;
|
||||
|
|
@ -1247,7 +1247,7 @@ void exec386_dynarec(int cycs)
|
|||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
// if (!fetchdat)
|
||||
// fatal("Dead with cache off\n");
|
||||
if (!abrt)
|
||||
if (!cpu_state.abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
opcode = fetchdat & 0xFF;
|
||||
|
|
@ -1271,7 +1271,7 @@ void exec386_dynarec(int cycs)
|
|||
ss=oldss;
|
||||
ssegs=0;
|
||||
}*/
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
CPU_BLOCK_END();
|
||||
if (trap)
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -1293,7 +1293,7 @@ void exec386_dynarec(int cycs)
|
|||
int valid_block = 0;
|
||||
trap = 0;
|
||||
|
||||
if (block && !abrt)
|
||||
if (block && !cpu_state.abrt)
|
||||
{
|
||||
page_t *page = &pages[phys_addr >> 12];
|
||||
|
||||
|
|
@ -1367,7 +1367,7 @@ inrecomp=0;
|
|||
insc += codeblock_ins[index];*/
|
||||
/* pclog("Exit block now %04X:%04X\n", CS, pc);*/
|
||||
}
|
||||
else if (valid_block && !abrt)
|
||||
else if (valid_block && !cpu_state.abrt)
|
||||
{
|
||||
uint32_t start_page = cpu_state.pc >> 12;
|
||||
uint32_t start_pc = cpu_state.pc;
|
||||
|
|
@ -1398,7 +1398,7 @@ inrecomp=0;
|
|||
// fatal("Dead ffffffff\n");
|
||||
// if (!fetchdat)
|
||||
// fatal("Dead\n");
|
||||
if (!abrt)
|
||||
if (!cpu_state.abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
opcode = fetchdat & 0xFF;
|
||||
|
|
@ -1430,7 +1430,7 @@ inrecomp=0;
|
|||
CPU_BLOCK_END();
|
||||
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
codegen_block_remove();
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -1440,7 +1440,7 @@ inrecomp=0;
|
|||
insc++;
|
||||
}
|
||||
|
||||
if (!abrt && !x86_was_reset)
|
||||
if (!cpu_state.abrt && !x86_was_reset)
|
||||
codegen_block_end_recompile(block);
|
||||
|
||||
if (x86_was_reset)
|
||||
|
|
@ -1449,7 +1449,7 @@ inrecomp=0;
|
|||
codegen_in_recompile = 0;
|
||||
// output &= ~2;
|
||||
}
|
||||
else if (!abrt)
|
||||
else if (!cpu_state.abrt)
|
||||
{
|
||||
/*Mark block but do not recompile*/
|
||||
uint32_t start_page = cpu_state.pc >> 12;
|
||||
|
|
@ -1477,7 +1477,7 @@ inrecomp=0;
|
|||
codegen_endpc = (cs + cpu_state.pc) + 8;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
|
||||
if (!abrt)
|
||||
if (!cpu_state.abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
opcode = fetchdat & 0xFF;
|
||||
|
|
@ -1507,7 +1507,7 @@ inrecomp=0;
|
|||
CPU_BLOCK_END();
|
||||
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
codegen_block_remove();
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -1517,7 +1517,7 @@ inrecomp=0;
|
|||
insc++;
|
||||
}
|
||||
|
||||
if (!abrt && !x86_was_reset)
|
||||
if (!cpu_state.abrt && !x86_was_reset)
|
||||
codegen_block_end();
|
||||
|
||||
if (x86_was_reset)
|
||||
|
|
@ -1534,22 +1534,22 @@ inrecomp=0;
|
|||
|
||||
// timer_end_period(cycles);
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
flags_rebuild();
|
||||
tempi = abrt;
|
||||
abrt = 0;
|
||||
tempi = cpu_state.abrt;
|
||||
cpu_state.abrt = 0;
|
||||
x86_doabrt(tempi);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
abrt = 0;
|
||||
cpu_state.abrt = 0;
|
||||
CS = oldcs;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
pclog("Double fault %i\n", ins);
|
||||
pmodeint(8, 0);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
abrt = 0;
|
||||
cpu_state.abrt = 0;
|
||||
softresetx86();
|
||||
pclog("Triple fault - reset\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,12 +16,12 @@ static inline void PUSH_W(uint16_t val)
|
|||
{
|
||||
if (stack32)
|
||||
{
|
||||
writememw(ss, ESP - 2, val); if (abrt) return;
|
||||
writememw(ss, ESP - 2, val); if (cpu_state.abrt) return;
|
||||
ESP -= 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
writememw(ss, (SP - 2) & 0xFFFF, val); if (abrt) return;
|
||||
writememw(ss, (SP - 2) & 0xFFFF, val); if (cpu_state.abrt) return;
|
||||
SP -= 2;
|
||||
}
|
||||
}
|
||||
|
|
@ -30,12 +30,12 @@ static inline void PUSH_L(uint32_t val)
|
|||
{
|
||||
if (stack32)
|
||||
{
|
||||
writememl(ss, ESP - 4, val); if (abrt) return;
|
||||
writememl(ss, ESP - 4, val); if (cpu_state.abrt) return;
|
||||
ESP -= 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
writememl(ss, (SP - 4) & 0xFFFF, val); if (abrt) return;
|
||||
writememl(ss, (SP - 4) & 0xFFFF, val); if (cpu_state.abrt) return;
|
||||
SP -= 4;
|
||||
}
|
||||
}
|
||||
|
|
@ -45,12 +45,12 @@ static inline uint16_t POP_W()
|
|||
uint16_t ret;
|
||||
if (stack32)
|
||||
{
|
||||
ret = readmemw(ss, ESP); if (abrt) return 0;
|
||||
ret = readmemw(ss, ESP); if (cpu_state.abrt) return 0;
|
||||
ESP += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = readmemw(ss, SP); if (abrt) return 0;
|
||||
ret = readmemw(ss, SP); if (cpu_state.abrt) return 0;
|
||||
SP += 2;
|
||||
}
|
||||
return ret;
|
||||
|
|
@ -61,12 +61,12 @@ static inline uint32_t POP_L()
|
|||
uint32_t ret;
|
||||
if (stack32)
|
||||
{
|
||||
ret = readmeml(ss, ESP); if (abrt) return 0;
|
||||
ret = readmeml(ss, ESP); if (cpu_state.abrt) return 0;
|
||||
ESP += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = readmeml(ss, SP); if (abrt) return 0;
|
||||
ret = readmeml(ss, SP); if (cpu_state.abrt) return 0;
|
||||
SP += 4;
|
||||
}
|
||||
return ret;
|
||||
|
|
@ -77,12 +77,12 @@ static inline uint16_t POP_W_seg(uint32_t seg)
|
|||
uint16_t ret;
|
||||
if (stack32)
|
||||
{
|
||||
ret = readmemw(seg, ESP); if (abrt) return 0;
|
||||
ret = readmemw(seg, ESP); if (cpu_state.abrt) return 0;
|
||||
ESP += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = readmemw(seg, SP); if (abrt) return 0;
|
||||
ret = readmemw(seg, SP); if (cpu_state.abrt) return 0;
|
||||
SP += 2;
|
||||
}
|
||||
return ret;
|
||||
|
|
@ -93,12 +93,12 @@ static inline uint32_t POP_L_seg(uint32_t seg)
|
|||
uint32_t ret;
|
||||
if (stack32)
|
||||
{
|
||||
ret = readmeml(seg, ESP); if (abrt) return 0;
|
||||
ret = readmeml(seg, ESP); if (cpu_state.abrt) return 0;
|
||||
ESP += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = readmeml(seg, SP); if (abrt) return 0;
|
||||
ret = readmeml(seg, SP); if (cpu_state.abrt) return 0;
|
||||
SP += 4;
|
||||
}
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -338,7 +338,6 @@ reg = If mod=11, (depending on data size, 16 bits/8 bits, 32 bits=extend 16 bit
|
|||
If BP or SP are in address calc, seg is SS, else DS
|
||||
*/
|
||||
|
||||
int cycles=0;
|
||||
uint32_t easeg;
|
||||
int rmdat;
|
||||
|
||||
|
|
@ -543,7 +542,7 @@ chdir(pcempath);
|
|||
f=fopen("rram4.dmp","wb");
|
||||
for (c=0;c<0x0050000;c++)
|
||||
{
|
||||
abrt = 0;
|
||||
cpu_state.abrt = 0;
|
||||
putc(readmemb386l(0,c+0x80000000),f);
|
||||
}
|
||||
fclose(f);
|
||||
|
|
|
|||
|
|
@ -239,7 +239,6 @@ void codegen_block_start_recompile(codeblock_t *block);
|
|||
void codegen_block_end_recompile(codeblock_t *block);
|
||||
void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc);
|
||||
void codegen_generate_seg_restore();
|
||||
void codegen_check_abrt();
|
||||
void codegen_set_op32();
|
||||
void codegen_flush();
|
||||
void codegen_check_flush(struct page_t *page, uint64_t mask, uint32_t phys_addr);
|
||||
|
|
@ -247,7 +246,7 @@ void codegen_check_flush(struct page_t *page, uint64_t mask, uint32_t phys_addr)
|
|||
extern int cpu_block_end;
|
||||
extern uint32_t codegen_endpc;
|
||||
|
||||
extern int cpu_recomp_blocks, cpu_recomp_ins, cpu_recomp_full_ins, cpu_new_blocks;
|
||||
extern int cpu_recomp_blocks, cpu_recomp_full_ins, cpu_new_blocks;
|
||||
extern int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latched, cpu_new_blocks_latched;
|
||||
extern int cpu_recomp_flushes, cpu_recomp_flushes_latched;
|
||||
extern int cpu_recomp_evicted, cpu_recomp_evicted_latched;
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ static uint32_t ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
|||
|
||||
FP_LOAD_IQ();
|
||||
|
||||
codegen_fpu_loaded_iq[(TOP - 1) & 7] = 1;
|
||||
codegen_fpu_loaded_iq[(cpu_state.TOP - 1) & 7] = 1;
|
||||
|
||||
return op_pc + 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ static int LOAD_REG_B(int reg)
|
|||
addbyte(0x44); /*MOVZX W[reg],host_reg*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[host_reg & 3].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[host_reg & 3].b));
|
||||
}
|
||||
|
||||
codegen_reg_loaded[reg & 3] = 1;
|
||||
|
|
@ -220,7 +220,7 @@ static int LOAD_REG_W(int reg)
|
|||
addbyte(0x44); /*MOVZX W[reg],host_reg*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 7].w));
|
||||
}
|
||||
|
||||
codegen_reg_loaded[reg & 7] = 1;
|
||||
|
|
@ -237,7 +237,7 @@ static int LOAD_REG_L(int reg)
|
|||
addbyte(0x44); /*MOVZX W[reg],host_reg*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 7].l));
|
||||
}
|
||||
|
||||
codegen_reg_loaded[reg & 7] = 1;
|
||||
|
|
@ -307,7 +307,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (dest_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 3].w));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -326,7 +326,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0xc0 | (dest_reg & 7));
|
||||
addbyte(0x88); /*MOVB regs[reg].b, AH*/
|
||||
addbyte(0x65);
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -336,7 +336,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0x44); /*MOVB regs[guest_reg].b, host_reg*/
|
||||
addbyte(0x88);
|
||||
addbyte(0x45 | ((host_reg & 3) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -352,7 +352,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0xc0 | (dest_reg & 7) | ((host_reg & 7) << 3));
|
||||
addbyte(0x88); /*MOVB regs[guest_reg].b, host_reg*/
|
||||
addbyte(0x45 | ((host_reg & 3) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 3].b));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -370,7 +370,7 @@ static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | ((host_reg & 7) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 7].w));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -381,7 +381,7 @@ static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0x66); /*MOVW regs[guest_reg].w, host_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 7].w));
|
||||
}
|
||||
}
|
||||
static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
|
||||
|
|
@ -394,7 +394,7 @@ static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0x44); /*MOVL regs[guest_reg].l, host_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].l - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 7].l));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -403,7 +403,7 @@ static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
|
|||
addbyte(0xc0 | guest_reg | (host_reg << 3));
|
||||
addbyte(0x89); /*MOVL regs[guest_reg].l, host_reg*/
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].l - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[guest_reg & 7].l));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -415,14 +415,14 @@ static void STORE_REG_B_RELEASE(int host_reg)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | ((host_reg & 7) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[host_reg & 7].w));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0x44); /*MOVB [reg],host_reg*/
|
||||
addbyte(0x88);
|
||||
addbyte(0x45 | ((host_reg & 7) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[host_reg & 7].b));
|
||||
}
|
||||
}
|
||||
static void STORE_REG_W_RELEASE(int host_reg)
|
||||
|
|
@ -431,14 +431,14 @@ static void STORE_REG_W_RELEASE(int host_reg)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | ((host_reg & 7) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[host_reg & 7].w));
|
||||
}
|
||||
static void STORE_REG_L_RELEASE(int host_reg)
|
||||
{
|
||||
addbyte(0x44); /*MOVL [reg],host_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | ((host_reg & 7) << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].l - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[host_reg & 7].l));
|
||||
}
|
||||
|
||||
static void STORE_IMM_REG_B(int reg, uint8_t val)
|
||||
|
|
@ -460,7 +460,7 @@ static void STORE_IMM_REG_B(int reg, uint8_t val)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 3].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 3].w));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -470,7 +470,7 @@ static void STORE_IMM_REG_B(int reg, uint8_t val)
|
|||
addbyte(0x44); /*MOVB reg, regs[reg].b*/
|
||||
addbyte(0x88);
|
||||
addbyte(0x45 | (reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 7].b - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 7].b));
|
||||
}
|
||||
}
|
||||
static void STORE_IMM_REG_W(int reg, uint16_t val)
|
||||
|
|
@ -483,7 +483,7 @@ static void STORE_IMM_REG_W(int reg, uint16_t val)
|
|||
addbyte(0x44);
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 7].w));
|
||||
}
|
||||
static void STORE_IMM_REG_L(int reg, uint32_t val)
|
||||
{
|
||||
|
|
@ -493,7 +493,7 @@ static void STORE_IMM_REG_L(int reg, uint32_t val)
|
|||
addbyte(0x44); /*MOVL reg, regs[reg].l*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (reg << 3));
|
||||
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[reg & 7].l));
|
||||
}
|
||||
|
||||
static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
|
||||
|
|
@ -964,15 +964,14 @@ static void MEM_LOAD_ADDR_EA_B(x86seg *seg)
|
|||
addbyte(0x04);
|
||||
addbyte(REG_EDI | (REG_ESI << 3));
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+12+8+6);
|
||||
addbyte(2+2+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
call_long(readmemb386l);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1031,15 +1030,14 @@ static void MEM_LOAD_ADDR_EA_W(x86seg *seg)
|
|||
addbyte(REG_EDI | (REG_ESI << 3));
|
||||
addbyte(-1);
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+12+8+6);
|
||||
addbyte(2+2+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
call_long(readmemwl);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1097,15 +1095,14 @@ static void MEM_LOAD_ADDR_EA_L(x86seg *seg)
|
|||
addbyte(REG_EDI | (REG_ESI << 3));
|
||||
addbyte(-3);
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+12+8+6);
|
||||
addbyte(2+2+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
call_long(readmemll);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1164,15 +1161,14 @@ static void MEM_LOAD_ADDR_EA_Q(x86seg *seg)
|
|||
addbyte(REG_EDI | (REG_ESI << 3));
|
||||
addbyte(-7);
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+12+8+6);
|
||||
addbyte(2+2+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
call_long(readmemql);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1274,16 +1270,15 @@ static void MEM_STORE_ADDR_EA_B(x86seg *seg, int host_reg)
|
|||
addbyte(REG_EDI | (REG_ESI << 3));
|
||||
}
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+3+12+8+6);
|
||||
addbyte(2+2+3+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
load_param_3_reg_32(host_reg);
|
||||
call_long(writememb386l);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1354,16 +1349,15 @@ static void MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
|
|||
addbyte(-1);
|
||||
}
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+3+12+8+6);
|
||||
addbyte(2+2+3+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
load_param_3_reg_32(host_reg);
|
||||
call_long(writememwl);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1432,16 +1426,15 @@ static void MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
|
|||
addbyte(-3);
|
||||
}
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+3+12+8+6);
|
||||
addbyte(2+2+3+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
load_param_3_reg_32(host_reg);
|
||||
call_long(writememll);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -1511,16 +1504,15 @@ static void MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
|
|||
addbyte(-7);
|
||||
}
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(2+2+3+12+8+6);
|
||||
addbyte(2+2+3+12+4+6);
|
||||
/*slowpath:*/
|
||||
load_param_1_reg_32(REG_ECX);
|
||||
load_param_2_reg_32(REG_EAX);
|
||||
load_param_3_reg_64(host_reg);
|
||||
call_long(writememql);
|
||||
addbyte(0x83); /*CMP abrt, 0*/
|
||||
addbyte(0x3c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt);
|
||||
addbyte(0x80); /*CMP abrt, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte(cpu_state_offset(abrt));
|
||||
addbyte(0);
|
||||
addbyte(0x0f); /*JNE end*/
|
||||
addbyte(0x85);
|
||||
|
|
@ -2789,17 +2781,16 @@ static void TEST_ZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
|
|||
addbyte(0xc0 | 0x38 | (host_reg & 7));
|
||||
addbyte(0);
|
||||
addbyte(0x75); /*JNZ +*/
|
||||
addbyte(7+5+(taken_cycles ? 8 : 0));
|
||||
addbyte(7+5+(taken_cycles ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(new_pc);
|
||||
if (taken_cycles)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(taken_cycles);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2813,17 +2804,16 @@ static void TEST_ZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
|
|||
addbyte(0xc0 | 0x38 | (host_reg & 7));
|
||||
addbyte(0);
|
||||
addbyte(0x75); /*JNZ +*/
|
||||
addbyte(7+5+(taken_cycles ? 8 : 0));
|
||||
addbyte(7+5+(taken_cycles ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(new_pc);
|
||||
if (taken_cycles)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(taken_cycles);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2839,17 +2829,16 @@ static void TEST_NONZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
|
|||
addbyte(0xc0 | 0x38 | (host_reg & 7));
|
||||
addbyte(0);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+5+(taken_cycles ? 8 : 0));
|
||||
addbyte(7+5+(taken_cycles ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(new_pc);
|
||||
if (taken_cycles)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(taken_cycles);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2863,17 +2852,16 @@ static void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
|
|||
addbyte(0xc0 | 0x38 | (host_reg & 7));
|
||||
addbyte(0);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+5+(taken_cycles ? 8 : 0));
|
||||
addbyte(7+5+(taken_cycles ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(new_pc);
|
||||
if (taken_cycles)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(taken_cycles);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2886,7 +2874,7 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
|
|||
{
|
||||
addbyte(0x83); /*CMP flags_res, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(flags_res));
|
||||
addbyte(0);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
}
|
||||
|
|
@ -2908,17 +2896,16 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
|
|||
addbyte(0x75); /*JNZ +*/
|
||||
else
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+5+(timing_bt ? 8 : 0));
|
||||
addbyte(7+5+(timing_bt ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(op_pc+pc_offset+offset);
|
||||
if (timing_bt)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(timing_bt);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2945,17 +2932,16 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
|
|||
addbyte(0x75); /*JNZ +*/
|
||||
else
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+5+(timing_bt ? 8 : 0));
|
||||
addbyte(7+5+(timing_bt ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(op_pc+pc_offset+offset);
|
||||
if (timing_bt)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(timing_bt);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -2968,7 +2954,7 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
|
|||
{
|
||||
addbyte(0x83); /*CMP flags_res, 0*/
|
||||
addbyte(0x7d);
|
||||
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(flags_res));
|
||||
addbyte(0);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
}
|
||||
|
|
@ -3002,17 +2988,16 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
|
|||
addbyte(0x75); /*JNZ +*/
|
||||
else
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+5+(timing_bt ? 8 : 0));
|
||||
addbyte(7+5+(timing_bt ? 4 : 0));
|
||||
addbyte(0xC7); /*MOVL [pc], new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(op_pc+pc_offset+offset);
|
||||
if (timing_bt)
|
||||
{
|
||||
addbyte(0x83); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addbyte(timing_bt);
|
||||
}
|
||||
addbyte(0xe9); /*JMP end*/
|
||||
|
|
@ -3348,7 +3333,7 @@ static void FP_ENTER()
|
|||
addbyte(7+5+12+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(oldpc));
|
||||
addlong(op_old_pc);
|
||||
load_param_1_32(&codeblock[block_current], 7);
|
||||
CALL_FUNC(x86_int);
|
||||
|
|
@ -3361,9 +3346,8 @@ static void FP_ENTER()
|
|||
static void FP_FXCH(int reg)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
|
@ -3395,7 +3379,7 @@ static void FP_FXCH(int reg)
|
|||
|
||||
addbyte(0x48); /*MOVL ESI, tag*/
|
||||
addbyte(0xbe);
|
||||
addquad((uintptr_t)tag);
|
||||
addquad((uintptr_t)cpu_state.tag);
|
||||
addbyte(0x8a); /*MOV CL, tag[EAX]*/
|
||||
addbyte(0x14);
|
||||
addbyte(0x1e);
|
||||
|
|
@ -3411,7 +3395,7 @@ static void FP_FXCH(int reg)
|
|||
|
||||
addbyte(0x48); /*MOV RSI, ST_i64*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST_i64);
|
||||
addquad((uint64_t)MM);
|
||||
addbyte(0x48); /*MOV RDX, [RSI + RBX*8]*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x14);
|
||||
|
|
@ -3436,9 +3420,8 @@ static void FP_FXCH(int reg)
|
|||
static void FP_FLD(int reg)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x89); /*MOV EBX, EAX*/
|
||||
addbyte(0xc3);
|
||||
if (reg)
|
||||
|
|
@ -3472,10 +3455,11 @@ static void FP_FLD(int reg)
|
|||
addbyte(0x8b);
|
||||
addbyte(0x14);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST_i64);
|
||||
addlong((uintptr_t)MM);
|
||||
addbyte(0x8a); /*MOV AL, [tag+EAX]*/
|
||||
addbyte(0x80);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
addbyte(0x48); /*MOV ST[EBX*8], RCX*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x0c);
|
||||
|
|
@ -3485,31 +3469,31 @@ static void FP_FLD(int reg)
|
|||
addbyte(0x89);
|
||||
addbyte(0x14);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST_i64);
|
||||
addlong((uintptr_t)MM);
|
||||
addbyte(0x88); /*MOV [tag+EBX], AL*/
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
|
||||
addbyte(0x89); /*MOV [TOP], EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
}
|
||||
|
||||
static void FP_FST(int reg)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x0c);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(0x8a); /*MOV BL, [tag+EAX]*/
|
||||
addbyte(0x98);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x5c);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
|
||||
if (reg)
|
||||
{
|
||||
|
|
@ -3527,19 +3511,20 @@ static void FP_FST(int reg)
|
|||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(0x88); /*MOV [tag+EAX], BL*/
|
||||
addbyte(0x98);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x5c);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
|
||||
static void FP_POP()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xc6); /*MOVB tag[EAX], 3*/
|
||||
addbyte(0x80);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
addbyte(3);
|
||||
addbyte(0x83); /*ADD AL, 1*/
|
||||
addbyte(0xc0);
|
||||
|
|
@ -3548,17 +3533,15 @@ static void FP_POP()
|
|||
addbyte(0xe0);
|
||||
addbyte(7);
|
||||
addbyte(0x89); /*MOV [TOP], EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
}
|
||||
|
||||
static void FP_LOAD_S()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x66); /*MOVD XMM0, EAX*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x6e);
|
||||
|
|
@ -3576,9 +3559,8 @@ static void FP_LOAD_S()
|
|||
addbyte(0x85); /*TEST EAX, EAX*/
|
||||
addbyte(0xc0);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
|
|
@ -3587,15 +3569,15 @@ static void FP_LOAD_S()
|
|||
addlong((uintptr_t)ST);
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
static void FP_LOAD_D()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x83); /*SUB EBX, 1*/
|
||||
addbyte(0xeb);
|
||||
addbyte(0x01);
|
||||
|
|
@ -3606,9 +3588,8 @@ static void FP_LOAD_D()
|
|||
addbyte(0x85);
|
||||
addbyte(0xc0);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOVQ [ST+EBX*8], RAX*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x04);
|
||||
|
|
@ -3616,16 +3597,16 @@ static void FP_LOAD_D()
|
|||
addlong((uintptr_t)ST);
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
|
||||
static void FP_LOAD_IW()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x0f); /*MOVSX EAX, AX*/
|
||||
addbyte(0xbf);
|
||||
addbyte(0xc0);
|
||||
|
|
@ -3642,9 +3623,8 @@ static void FP_LOAD_IW()
|
|||
addbyte(0x85); /*TEST EAX, EAX*/
|
||||
addbyte(0xc0);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
|
|
@ -3653,15 +3633,15 @@ static void FP_LOAD_IW()
|
|||
addlong((uintptr_t)ST);
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
static void FP_LOAD_IL()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x83); /*SUB EBX, 1*/
|
||||
addbyte(0xeb);
|
||||
addbyte(0x01);
|
||||
|
|
@ -3675,9 +3655,8 @@ static void FP_LOAD_IL()
|
|||
addbyte(0x85); /*TEST EAX, EAX*/
|
||||
addbyte(0xc0);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
|
|
@ -3686,15 +3665,15 @@ static void FP_LOAD_IL()
|
|||
addlong((uintptr_t)ST);
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
static void FP_LOAD_IQ()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x83); /*SUB EBX, 1*/
|
||||
addbyte(0xeb);
|
||||
addbyte(0x01);
|
||||
|
|
@ -3713,11 +3692,10 @@ static void FP_LOAD_IQ()
|
|||
addbyte(0x89);
|
||||
addbyte(0x04);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST_i64);
|
||||
addlong((uintptr_t)MM);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x0f); /*SETE AL*/
|
||||
addbyte(0x94);
|
||||
addbyte(0xc0);
|
||||
|
|
@ -3730,16 +3708,16 @@ static void FP_LOAD_IQ()
|
|||
addbyte(0x0c); /*OR AL, TAG_UINT64*/
|
||||
addbyte(TAG_UINT64);
|
||||
addbyte(0x88); /*MOV [tag+EBX], AL*/
|
||||
addbyte(0x83);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
}
|
||||
|
||||
static int FP_LOAD_REG(int reg)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
if (reg)
|
||||
{
|
||||
addbyte(0x83); /*ADD EBX, reg*/
|
||||
|
|
@ -3769,9 +3747,8 @@ static int FP_LOAD_REG(int reg)
|
|||
static void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EBX, TOP*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
if (reg)
|
||||
{
|
||||
addbyte(0x83); /*ADD EBX, reg*/
|
||||
|
|
@ -3818,9 +3795,8 @@ static int FP_LOAD_REG_INT_W(int reg)
|
|||
addbyte(0xc3);
|
||||
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
if (reg)
|
||||
{
|
||||
addbyte(0x83); /*ADD EAX, reg*/
|
||||
|
|
@ -3849,9 +3825,8 @@ static int FP_LOAD_REG_INT(int reg)
|
|||
addbyte(0xc3);
|
||||
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
if (reg)
|
||||
{
|
||||
addbyte(0x83); /*ADD EAX, reg*/
|
||||
|
|
@ -3880,9 +3855,8 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(0xc3);
|
||||
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
if (reg)
|
||||
{
|
||||
addbyte(0x83); /*ADD EAX, reg*/
|
||||
|
|
@ -3893,7 +3867,7 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(7);
|
||||
}
|
||||
|
||||
if (codegen_fpu_loaded_iq[TOP] && (tag[TOP] & TAG_UINT64))
|
||||
if (codegen_fpu_loaded_iq[cpu_state.TOP] && (cpu_state.tag[cpu_state.TOP] & TAG_UINT64))
|
||||
{
|
||||
/*If we know the register was loaded with FILDq in this block and
|
||||
has not been modified, then we can skip most of the conversion
|
||||
|
|
@ -3902,7 +3876,7 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(0x8b);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc5);
|
||||
addlong((uint32_t)ST_i64);
|
||||
addlong((uint32_t)MM);
|
||||
|
||||
addbyte(0x48); /*XCHG RBX, RAX*/
|
||||
addbyte(0x93);
|
||||
|
|
@ -3912,9 +3886,10 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
return;
|
||||
}
|
||||
|
||||
addbyte(0xf6); /*TEST TAG[EBX], TAG_UINT64*/
|
||||
addbyte(0x80);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0xf6); /*TEST TAG[EAX], TAG_UINT64*/
|
||||
addbyte(0x44);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
addbyte(TAG_UINT64);
|
||||
|
||||
addbyte(0x74); /*JZ +*/
|
||||
|
|
@ -3924,7 +3899,7 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(0x8b);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc5);
|
||||
addlong((uint32_t)ST_i64);
|
||||
addlong((uint32_t)MM);
|
||||
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(9+12);
|
||||
|
|
@ -3954,9 +3929,8 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
static void FP_OP_REG(int op, int dst, int src)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
|
@ -4051,9 +4025,8 @@ static void FP_OP_REG(int op, int dst, int src)
|
|||
static void FP_OP_MEM(int op)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
|
@ -4063,8 +4036,9 @@ static void FP_OP_MEM(int op)
|
|||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
|
||||
addbyte(0xa0 | REG_EAX);
|
||||
addlong((uintptr_t)tag);
|
||||
addbyte(0x64);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
addbyte(~TAG_UINT64);
|
||||
|
||||
switch (op)
|
||||
|
|
@ -4206,9 +4180,8 @@ static void FP_OP_IL(int op)
|
|||
static void FP_COMPARE_REG(int dst, int src)
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
|
@ -4276,9 +4249,8 @@ static void FP_COMPARE_REG(int dst, int src)
|
|||
static void FP_COMPARE_MEM()
|
||||
{
|
||||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
|
@ -4409,7 +4381,7 @@ static void MMX_ENTER()
|
|||
addbyte(7+5+12+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(oldpc));
|
||||
addlong(op_old_pc);
|
||||
load_param_1_32(&codeblock[block_current], 7);
|
||||
CALL_FUNC(x86_int);
|
||||
|
|
@ -4419,23 +4391,19 @@ static void MMX_ENTER()
|
|||
|
||||
addbyte(0x31); /*XOR EAX, EAX*/
|
||||
addbyte(0xc0);
|
||||
addbyte(0xc7); /*MOV ISMMX, 1*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&ismmx);
|
||||
addlong(1);
|
||||
addbyte(0xc6); /*MOV ISMMX, 1*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(ismmx));
|
||||
addbyte(1);
|
||||
addbyte(0x89); /*MOV TOP, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&TOP);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x89); /*MOV tag, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&tag[0]);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(0x89); /*MOV tag+4, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&tag[4]);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(tag[4]));
|
||||
|
||||
codegen_mmx_entered = 1;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -473,17 +473,15 @@ void codegen_block_end_recompile(codeblock_t *block)
|
|||
if (codegen_block_cycles)
|
||||
{
|
||||
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addlong((uint32_t)codegen_block_cycles);
|
||||
}
|
||||
if (codegen_block_ins)
|
||||
{
|
||||
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&cpu_recomp_ins);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(cpu_recomp_ins));
|
||||
addlong(codegen_block_ins);
|
||||
}
|
||||
#if 0
|
||||
|
|
@ -612,7 +610,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
{
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
addlong((fetchdat >> 8) & 0xffff);
|
||||
(*op_pc) += 2;
|
||||
}
|
||||
|
|
@ -722,7 +720,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
|
||||
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
|
|
@ -877,7 +875,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -888,7 +886,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
addlong(new_eaaddr);
|
||||
(*op_pc) += 4;
|
||||
return op_ea_seg;
|
||||
|
|
@ -919,14 +917,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0x44); /*MOV eaaddr, base_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (base_reg << 3));
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
}
|
||||
}
|
||||
return op_ea_seg;
|
||||
|
|
@ -1074,7 +1072,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
|
|||
}
|
||||
fetchdat = fastreadl(cs + op_pc);
|
||||
codegen_timing_prefix(opcode, fetchdat);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return;
|
||||
opcode = fetchdat & 0xff;
|
||||
if (!pc_off)
|
||||
|
|
@ -1095,18 +1093,16 @@ generate_call:
|
|||
if (codegen_block_cycles)
|
||||
{
|
||||
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addlong((uint32_t)codegen_block_cycles);
|
||||
codegen_block_cycles = 0;
|
||||
}
|
||||
if (codegen_block_ins)
|
||||
{
|
||||
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&cpu_recomp_ins);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(cpu_recomp_ins));
|
||||
addlong(codegen_block_ins);
|
||||
codegen_block_ins = 0;
|
||||
}
|
||||
|
|
@ -1147,7 +1143,7 @@ generate_call:
|
|||
last_ssegs = op_ssegs;
|
||||
addbyte(0xC6); /*MOVB $0,(ssegs)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ssegs - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(ssegs));
|
||||
addbyte(op_ssegs);
|
||||
}
|
||||
//#if 0
|
||||
|
|
@ -1166,7 +1162,7 @@ generate_call:
|
|||
|
||||
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.rm_data.rm_mod_reg_data - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(rm_data.rm_mod_reg_data));
|
||||
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
|
||||
|
||||
op_pc += pc_off;
|
||||
|
|
@ -1182,25 +1178,25 @@ generate_call:
|
|||
// last_ea_seg = op_ea_seg;
|
||||
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ea_seg - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(ea_seg));
|
||||
addlong((uint32_t)op_ea_seg);
|
||||
}
|
||||
|
||||
|
||||
addbyte(0xC7); /*MOVL [pc],new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(op_pc + pc_off);
|
||||
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(oldpc));
|
||||
addlong(old_pc);
|
||||
if (op_32 != last_op32)
|
||||
{
|
||||
last_op32 = op_32;
|
||||
addbyte(0xC7); /*MOVL $use32,(op32)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.op32 - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(op32));
|
||||
addlong(op_32);
|
||||
}
|
||||
|
||||
|
|
@ -1221,15 +1217,4 @@ generate_call:
|
|||
codegen_endpc = (cs + cpu_state.pc) + 8;
|
||||
}
|
||||
|
||||
void codegen_check_abrt()
|
||||
{
|
||||
codeblock_t *block = &codeblock[block_current];
|
||||
// pclog("Generate check abrt at %08X\n", &codeblock[block_current][block_pos]);
|
||||
addbyte(0xf7); addbyte(0x04); /*TESTL $-1, (abrt)*/
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&abrt); addlong(0xffffffff);
|
||||
addbyte(0x0F); addbyte(0x85); /*JNZ 0*/
|
||||
addlong((uint32_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(&block->data[block_pos + 4]));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -446,15 +446,15 @@ void codegen_block_end_recompile(codeblock_t *block)
|
|||
if (codegen_block_cycles)
|
||||
{
|
||||
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2d);
|
||||
addlong((uint32_t)&cycles);
|
||||
addlong((uint32_t)codegen_block_cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addlong(codegen_block_cycles);
|
||||
}
|
||||
if (codegen_block_ins)
|
||||
{
|
||||
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&cpu_recomp_ins);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(cpu_recomp_ins));
|
||||
addlong(codegen_block_ins);
|
||||
}
|
||||
#if 0
|
||||
|
|
@ -573,7 +573,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
{
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
addlong((fetchdat >> 8) & 0xffff);
|
||||
(*op_pc) += 2;
|
||||
}
|
||||
|
|
@ -645,7 +645,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
{
|
||||
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(regs[sib & 7].l));
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
|
|
@ -654,7 +654,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
addlong(new_eaaddr);
|
||||
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(regs[sib & 7].l));
|
||||
(*op_pc)++;
|
||||
break;
|
||||
case 2:
|
||||
|
|
@ -663,7 +663,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
addlong(new_eaaddr);
|
||||
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(regs[sib & 7].l));
|
||||
(*op_pc) += 4;
|
||||
break;
|
||||
}
|
||||
|
|
@ -681,20 +681,20 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
case 0:
|
||||
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l));
|
||||
break;
|
||||
case 1:
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
|
||||
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
|
||||
break;
|
||||
case 2:
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0xC1); addbyte(0xE3); addbyte(2); /*SHL $2,%ebx*/
|
||||
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
|
||||
break;
|
||||
case 3:
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
|
||||
addbyte(0xC1); addbyte(0xE3); addbyte(3); /*SHL $2,%ebx*/
|
||||
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
|
||||
break;
|
||||
|
|
@ -710,14 +710,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(eaaddr));
|
||||
addlong(new_eaaddr);
|
||||
(*op_pc) += 4;
|
||||
return op_ea_seg;
|
||||
}
|
||||
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[cpu_rm].l - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(regs[cpu_rm].l));
|
||||
// addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/
|
||||
// addlong((uint32_t)&cpu_state.regs[cpu_rm].l);
|
||||
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
|
|
@ -888,7 +888,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
|
|||
}
|
||||
fetchdat = fastreadl(cs + op_pc);
|
||||
codegen_timing_prefix(opcode, fetchdat);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return;
|
||||
opcode = fetchdat & 0xff;
|
||||
if (!pc_off)
|
||||
|
|
@ -910,16 +910,16 @@ generate_call:
|
|||
if (codegen_block_cycles)
|
||||
{
|
||||
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
|
||||
addbyte(0x2d);
|
||||
addlong((uint32_t)&cycles);
|
||||
addlong((uint32_t)codegen_block_cycles);
|
||||
addbyte(0x6d);
|
||||
addbyte(cpu_state_offset(_cycles));
|
||||
addlong(codegen_block_cycles);
|
||||
codegen_block_cycles = 0;
|
||||
}
|
||||
if (codegen_block_ins)
|
||||
{
|
||||
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&cpu_recomp_ins);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(cpu_recomp_ins));
|
||||
addlong(codegen_block_ins);
|
||||
codegen_block_ins = 0;
|
||||
}
|
||||
|
|
@ -961,7 +961,7 @@ generate_call:
|
|||
|
||||
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ssegs - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(ssegs));
|
||||
addbyte(op_pc + pc_off);
|
||||
}
|
||||
|
||||
|
|
@ -980,7 +980,7 @@ generate_call:
|
|||
|
||||
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.rm_data.rm_mod_reg_data - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(rm_data.rm_mod_reg_data));
|
||||
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
|
||||
|
||||
op_pc += pc_off;
|
||||
|
|
@ -996,18 +996,18 @@ generate_call:
|
|||
last_ea_seg = op_ea_seg;
|
||||
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ea_seg - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(ea_seg));
|
||||
addlong((uint32_t)op_ea_seg);
|
||||
}
|
||||
|
||||
addbyte(0xC7); /*MOVL pc,new_pc*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(pc));
|
||||
addlong(op_pc + pc_off);
|
||||
|
||||
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(oldpc));
|
||||
addlong(old_pc);
|
||||
|
||||
if (op_32 != last_op32)
|
||||
|
|
@ -1015,7 +1015,7 @@ generate_call:
|
|||
last_op32 = op_32;
|
||||
addbyte(0xC7); /*MOVL $use32,(op32)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.op32 - (uintptr_t)&cpu_state);
|
||||
addbyte(cpu_state_offset(op32));
|
||||
addlong(op_32);
|
||||
}
|
||||
|
||||
|
|
@ -1042,14 +1042,4 @@ generate_call:
|
|||
codegen_endpc = (cs + cpu_state.pc) + 8;
|
||||
}
|
||||
|
||||
void codegen_check_abrt()
|
||||
{
|
||||
codeblock_t *block = &codeblock[block_current];
|
||||
// pclog("Generate check abrt at %08X\n", &codeblock[block_current][block_pos]);
|
||||
addbyte(0x83); addbyte(0x3d); /*CMP abrt, 0*/
|
||||
addlong((uint32_t)&abrt); addbyte(0);
|
||||
addbyte(0x0F); addbyte(0x85); /*JNZ 0*/
|
||||
addlong((uint32_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(&block->data[block_pos + 4]));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -89,7 +89,6 @@ void fdc_reset()
|
|||
}
|
||||
// pclog("Reset FDC\n");
|
||||
}
|
||||
int ins;
|
||||
|
||||
void fdc_reset_fifo_buf()
|
||||
{
|
||||
|
|
|
|||
16
src/ibm.h
16
src/ibm.h
|
|
@ -112,6 +112,8 @@ typedef struct
|
|||
struct
|
||||
{
|
||||
x86reg regs[8];
|
||||
|
||||
uint8_t tag[8];
|
||||
|
||||
x86seg *ea_seg;
|
||||
uint32_t eaaddr;
|
||||
|
|
@ -122,7 +124,9 @@ struct
|
|||
|
||||
uint32_t pc;
|
||||
uint32_t oldpc;
|
||||
uint32_t op32;
|
||||
uint32_t op32;
|
||||
|
||||
int TOP;
|
||||
|
||||
union
|
||||
{
|
||||
|
|
@ -134,12 +138,21 @@ struct
|
|||
} rm_data;
|
||||
|
||||
int8_t ssegs;
|
||||
int8_t ismmx;
|
||||
int8_t abrt;
|
||||
|
||||
int _cycles;
|
||||
int cpu_recomp_ins;
|
||||
} cpu_state;
|
||||
|
||||
#define cycles cpu_state._cycles
|
||||
|
||||
#define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0];
|
||||
|
||||
COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128);
|
||||
|
||||
#define cpu_state_offset(MEMBER) ((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state)
|
||||
|
||||
/*x86reg regs[8];*/
|
||||
|
||||
uint16_t flags,eflags;
|
||||
|
|
@ -210,7 +223,6 @@ uint32_t dr[8];
|
|||
//#define IOPLp 1
|
||||
|
||||
//#define IOPLV86 ((!(msw&1)) || (CPL<=IOPL))
|
||||
extern int cycles;
|
||||
extern int cycles_lost;
|
||||
extern int is486;
|
||||
extern uint8_t opcode;
|
||||
|
|
|
|||
10
src/mem.c
10
src/mem.c
|
|
@ -617,7 +617,7 @@ int loadbios()
|
|||
|
||||
|
||||
|
||||
int abrt=0;
|
||||
//int abrt=0;
|
||||
|
||||
void resetreadlookup()
|
||||
{
|
||||
|
|
@ -783,7 +783,7 @@ uint32_t mmutranslatereal(uint32_t addr, int rw)
|
|||
uint32_t addr2;
|
||||
uint32_t temp,temp2,temp3;
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
// pclog("Translate recursive abort\n");
|
||||
return -1;
|
||||
|
|
@ -803,7 +803,7 @@ uint32_t mmutranslatereal(uint32_t addr, int rw)
|
|||
temp&=1;
|
||||
if (CPL==3) temp|=4;
|
||||
if (rw) temp|=2;
|
||||
abrt = ABRT_PF;
|
||||
cpu_state.abrt = ABRT_PF;
|
||||
abrt_error = temp;
|
||||
/* if (addr == 0x70046D)
|
||||
{
|
||||
|
|
@ -833,7 +833,7 @@ uint32_t mmutranslatereal(uint32_t addr, int rw)
|
|||
temp&=1;
|
||||
if (CPL==3) temp|=4;
|
||||
if (rw) temp|=2;
|
||||
abrt = ABRT_PF;
|
||||
cpu_state.abrt = ABRT_PF;
|
||||
abrt_error = temp;
|
||||
// pclog("%04X\n",abrt);
|
||||
return -1;
|
||||
|
|
@ -851,7 +851,7 @@ uint32_t mmutranslate_noabrt(uint32_t addr, int rw)
|
|||
uint32_t addr2;
|
||||
uint32_t temp,temp2,temp3;
|
||||
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
return -1;
|
||||
|
||||
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
|
||||
|
|
|
|||
4
src/pc.c
4
src/pc.c
|
|
@ -467,7 +467,7 @@ void runpc()
|
|||
scycles_lost = cycles_lost;
|
||||
|
||||
cpu_recomp_blocks_latched = cpu_recomp_blocks;
|
||||
cpu_recomp_ins_latched = cpu_recomp_ins;
|
||||
cpu_recomp_ins_latched = cpu_state.cpu_recomp_ins;
|
||||
cpu_recomp_full_ins_latched = cpu_recomp_full_ins;
|
||||
cpu_new_blocks_latched = cpu_new_blocks;
|
||||
cpu_recomp_flushes_latched = cpu_recomp_flushes;
|
||||
|
|
@ -478,7 +478,7 @@ void runpc()
|
|||
cpu_notreps_latched = cpu_notreps;
|
||||
|
||||
cpu_recomp_blocks = 0;
|
||||
cpu_recomp_ins = 0;
|
||||
cpu_state.cpu_recomp_ins = 0;
|
||||
cpu_recomp_full_ins = 0;
|
||||
cpu_new_blocks = 0;
|
||||
cpu_recomp_flushes = 0;
|
||||
|
|
|
|||
|
|
@ -315,7 +315,6 @@ static int pit_read_timer(int t)
|
|||
return pit.count[t];
|
||||
}
|
||||
|
||||
extern int ins;
|
||||
void pit_write(uint16_t addr, uint8_t val, void *priv)
|
||||
{
|
||||
int t;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ int oldcpl;
|
|||
extern int nmi_enable;
|
||||
|
||||
int tempc;
|
||||
int cycles,output;
|
||||
int output;
|
||||
int firstrepcycle;
|
||||
|
||||
uint32_t easeg,ealimit,ealimitw;
|
||||
|
|
@ -14,7 +14,7 @@ int skipnextprint;
|
|||
int inhlt;
|
||||
|
||||
uint8_t opcode;
|
||||
int ins,noint;
|
||||
int noint;
|
||||
|
||||
uint16_t lastcs,lastpc;
|
||||
int timetolive,keyboardtimer;
|
||||
|
|
@ -83,7 +83,6 @@ enum
|
|||
ABRT_PF = 0xE
|
||||
};
|
||||
|
||||
extern int abrt;
|
||||
extern uint32_t abrt_error;
|
||||
|
||||
void x86_doabrt(int x86_abrt);
|
||||
|
|
|
|||
|
|
@ -13,9 +13,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (abrt) return 1; \
|
||||
uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
seteab(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
|
|
@ -35,9 +35,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (abrt) return 1; \
|
||||
uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
seteab(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
|
|
@ -58,9 +58,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (abrt) return 1; \
|
||||
uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
seteaw(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
|
|
@ -80,9 +80,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (abrt) return 1; \
|
||||
uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
seteaw(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
|
|
@ -103,9 +103,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (abrt) return 1; \
|
||||
uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
seteal(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
} \
|
||||
|
|
@ -125,9 +125,9 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (abrt) return 1; \
|
||||
uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
seteal(operation); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
} \
|
||||
|
|
@ -140,7 +140,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (abrt) return 1; \
|
||||
src = geteab(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(cpu_reg, operation); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
|
|
@ -152,7 +152,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (abrt) return 1; \
|
||||
src = geteab(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(cpu_reg, operation); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
|
|
@ -165,7 +165,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (abrt) return 1; \
|
||||
src = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[cpu_reg].w = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
|
|
@ -177,7 +177,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (abrt) return 1; \
|
||||
src = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[cpu_reg].w = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
|
|
@ -190,7 +190,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (abrt) return 1; \
|
||||
src = geteal(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[cpu_reg].l = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
|
||||
|
|
@ -202,7 +202,7 @@
|
|||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (abrt) return 1; \
|
||||
src = geteal(); if (cpu_state.abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[cpu_reg].l = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
|
||||
|
|
@ -234,7 +234,7 @@
|
|||
static int op ## name ## _EAX_imm(uint32_t fetchdat) \
|
||||
{ \
|
||||
uint32_t dst = EAX; \
|
||||
uint32_t src = getlong(); if (abrt) return 1; \
|
||||
uint32_t src = getlong(); if (cpu_state.abrt) return 1; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
setflags ## 32 flagops; \
|
||||
EAX = operation; \
|
||||
|
|
@ -254,7 +254,7 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -264,7 +264,7 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -275,7 +275,7 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -285,7 +285,7 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -296,7 +296,7 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -306,7 +306,7 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
|
|
@ -317,7 +317,7 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
|
|
@ -326,7 +326,7 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
src = geteab(); if (cpu_state.abrt) return 1;
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
|
|
@ -336,7 +336,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
|
|
@ -345,7 +345,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
src = geteaw(); if (cpu_state.abrt) return 1;
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
|
|
@ -355,7 +355,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
|
|
@ -364,7 +364,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
src = geteal(); if (cpu_state.abrt) return 1;
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
|
|
@ -388,7 +388,7 @@ static int opCMP_AX_imm(uint32_t fetchdat)
|
|||
|
||||
static int opCMP_EAX_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = getlong(); if (abrt) return 1;
|
||||
uint32_t src = getlong(); if (cpu_state.abrt) return 1;
|
||||
setsub32(EAX, src);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
|
|
@ -398,7 +398,7 @@ static int opTEST_b_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -409,7 +409,7 @@ static int opTEST_b_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -421,7 +421,7 @@ static int opTEST_w_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -432,7 +432,7 @@ static int opTEST_w_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -444,7 +444,7 @@ static int opTEST_l_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -455,7 +455,7 @@ static int opTEST_l_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
|
|
@ -479,7 +479,7 @@ static int opTEST_AX(uint32_t fetchdat)
|
|||
}
|
||||
static int opTEST_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = getlong(); if (abrt) return 1;
|
||||
uint32_t temp = getlong(); if (cpu_state.abrt) return 1;
|
||||
setznp32(EAX & temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
|
|
@ -487,46 +487,46 @@ static int opTEST_EAX(uint32_t fetchdat)
|
|||
|
||||
|
||||
#define ARITH_MULTI(ea_width, flag_width) \
|
||||
dst = getea ## ea_width(); if (abrt) return 1; \
|
||||
dst = getea ## ea_width(); if (cpu_state.abrt) return 1; \
|
||||
switch (rmdat&0x38) \
|
||||
{ \
|
||||
case 0x00: /*ADD ea, #*/ \
|
||||
setea ## ea_width(dst + src); if (abrt) return 1; \
|
||||
setea ## ea_width(dst + src); if (cpu_state.abrt) return 1; \
|
||||
setadd ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x08: /*OR ea, #*/ \
|
||||
dst |= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x10: /*ADC ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst + src + tempc); if (abrt) return 1; \
|
||||
setea ## ea_width(dst + src + tempc); if (cpu_state.abrt) return 1; \
|
||||
setadc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x18: /*SBB ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst - (src + tempc)); if (abrt) return 1; \
|
||||
setea ## ea_width(dst - (src + tempc)); if (cpu_state.abrt) return 1; \
|
||||
setsbc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x20: /*AND ea, #*/ \
|
||||
dst &= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 1; \
|
||||
setea ## ea_width(dst - src); if (cpu_state.abrt) return 1; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
|
|
@ -543,7 +543,7 @@ static int op80_a16(uint32_t fetchdat)
|
|||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
|
|
@ -553,7 +553,7 @@ static int op80_a32(uint32_t fetchdat)
|
|||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
|
|
@ -563,7 +563,7 @@ static int op81_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
|
|
@ -573,7 +573,7 @@ static int op81_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
|
|
@ -583,7 +583,7 @@ static int op81_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
|
|
@ -593,7 +593,7 @@ static int op81_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
|
|
@ -604,7 +604,7 @@ static int op83_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
|
|
@ -615,7 +615,7 @@ static int op83_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
|
|
@ -627,7 +627,7 @@ static int op83_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
|
|
@ -638,7 +638,7 @@ static int op83_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 1;
|
||||
src = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
|
|
|
|||
|
|
@ -8,10 +8,10 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub8(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -26,10 +26,10 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub8(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -45,10 +45,10 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub16(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -63,10 +63,10 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub16(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -82,10 +82,10 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub32(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -100,10 +100,10 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
setsub32(temp2, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -120,7 +120,7 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
{
|
||||
seteal(EBX);
|
||||
|
|
@ -131,7 +131,7 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
|
|||
EAX = temp;
|
||||
EDX = temp_hi;
|
||||
}
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
flags_rebuild();
|
||||
if (temp == temp2 && temp_hi == temp2_hi)
|
||||
flags |= Z_FLAG;
|
||||
|
|
@ -151,7 +151,7 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
{
|
||||
seteal(EBX);
|
||||
|
|
@ -162,7 +162,7 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
|||
EAX = temp;
|
||||
EDX = temp_hi;
|
||||
}
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
flags_rebuild();
|
||||
if (temp == temp2 && temp_hi == temp2_hi)
|
||||
flags |= Z_FLAG;
|
||||
|
|
@ -182,8 +182,8 @@ static int opXADD_b_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
@ -199,8 +199,8 @@ static int opXADD_b_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp + getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
@ -217,8 +217,8 @@ static int opXADD_w_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
@ -234,8 +234,8 @@ static int opXADD_w_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
@ -252,8 +252,8 @@ static int opXADD_l_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
@ -269,8 +269,8 @@ static int opXADD_l_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ static int opBT_w_r_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
|
@ -19,7 +19,7 @@ static int opBT_w_r_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
|
@ -33,7 +33,7 @@ static int opBT_l_r_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
|
@ -47,7 +47,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
|
@ -64,10 +64,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
else flags &= ~C_FLAG; \
|
||||
|
|
@ -82,10 +82,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
else flags &= ~C_FLAG; \
|
||||
|
|
@ -100,10 +100,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
else flags &= ~C_FLAG; \
|
||||
|
|
@ -118,10 +118,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
else flags &= ~C_FLAG; \
|
||||
|
|
@ -142,7 +142,7 @@ static int opBA_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
|
||||
temp = geteaw();
|
||||
count = getbyte(); if (abrt) return 1;
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
flags_rebuild();
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -168,7 +168,7 @@ static int opBA_w_a16(uint32_t fetchdat)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
seteaw(temp); if (abrt) return 1;
|
||||
seteaw(temp); if (cpu_state.abrt) return 1;
|
||||
if (tempc) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
@ -182,7 +182,7 @@ static int opBA_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
|
||||
temp = geteaw();
|
||||
count = getbyte(); if (abrt) return 1;
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
flags_rebuild();
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -208,7 +208,7 @@ static int opBA_w_a32(uint32_t fetchdat)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
seteaw(temp); if (abrt) return 1;
|
||||
seteaw(temp); if (cpu_state.abrt) return 1;
|
||||
if (tempc) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
@ -223,7 +223,7 @@ static int opBA_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
|
||||
temp = geteal();
|
||||
count = getbyte(); if (abrt) return 1;
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
flags_rebuild();
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -249,7 +249,7 @@ static int opBA_l_a16(uint32_t fetchdat)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
seteal(temp); if (abrt) return 1;
|
||||
seteal(temp); if (cpu_state.abrt) return 1;
|
||||
if (tempc) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
@ -263,7 +263,7 @@ static int opBA_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
|
||||
temp = geteal();
|
||||
count = getbyte(); if (abrt) return 1;
|
||||
count = getbyte(); if (cpu_state.abrt) return 1;
|
||||
tempc = temp & (1 << count);
|
||||
flags_rebuild();
|
||||
switch (rmdat & 0x38)
|
||||
|
|
@ -289,7 +289,7 @@ static int opBA_l_a32(uint32_t fetchdat)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
seteal(temp); if (abrt) return 1;
|
||||
seteal(temp); if (cpu_state.abrt) return 1;
|
||||
if (tempc) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ static int opBSF_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
||||
|
|
@ -34,7 +34,7 @@ static int opBSF_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ static int opBSF_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ static int opBSF_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
||||
|
|
@ -71,7 +71,7 @@ static int opBSR_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
||||
|
|
@ -83,7 +83,7 @@ static int opBSR_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
||||
|
|
@ -95,7 +95,7 @@ static int opBSR_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
||||
|
|
@ -107,7 +107,7 @@ static int opBSR_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,19 +12,19 @@
|
|||
cycles -= timing_call_rm; \
|
||||
} \
|
||||
optype = 0; \
|
||||
if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
oldss = ss; \
|
||||
if (cgate32) \
|
||||
{ \
|
||||
uint32_t old_esp = ESP; \
|
||||
PUSH_L(old_cs); if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_L(old_pc); if (abrt) { ESP = old_esp; return 1; } \
|
||||
PUSH_L(old_cs); if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_L(old_pc); if (cpu_state.abrt) { ESP = old_esp; return 1; } \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t old_esp = ESP; \
|
||||
PUSH_W(old_cs); if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_W(old_pc); if (abrt) { ESP = old_esp; return 1; } \
|
||||
PUSH_W(old_cs); if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_W(old_pc); if (cpu_state.abrt) { ESP = old_esp; return 1; } \
|
||||
}
|
||||
|
||||
#define CALL_FAR_l(new_seg, new_pc) \
|
||||
|
|
@ -41,19 +41,19 @@
|
|||
cycles -= timing_call_rm; \
|
||||
} \
|
||||
optype = 0; \
|
||||
if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
oldss = ss; \
|
||||
if (cgate16) \
|
||||
{ \
|
||||
uint32_t old_esp = ESP; \
|
||||
PUSH_W(old_cs); if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_W(old_pc); if (abrt) { ESP = old_esp; return 1; } \
|
||||
PUSH_W(old_cs); if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_W(old_pc); if (cpu_state.abrt) { ESP = old_esp; return 1; } \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t old_esp = ESP; \
|
||||
PUSH_L(old_cs); if (abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_L(old_pc); if (abrt) { ESP = old_esp; return 1; } \
|
||||
PUSH_L(old_cs); if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
|
||||
PUSH_L(old_pc); if (cpu_state.abrt) { ESP = old_esp; return 1; } \
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -63,7 +63,7 @@ static int opCALL_far_w(uint32_t fetchdat)
|
|||
uint16_t new_cs, new_pc;
|
||||
|
||||
new_pc = getwordf();
|
||||
new_cs = getword(); if (abrt) return 1;
|
||||
new_cs = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_w(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -76,7 +76,7 @@ static int opCALL_far_l(uint32_t fetchdat)
|
|||
uint32_t new_cs, new_pc;
|
||||
|
||||
new_pc = getlong();
|
||||
new_cs = getword(); if (abrt) return 1;
|
||||
new_cs = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_l(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -97,19 +97,19 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + 1); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp - 1); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -118,13 +118,13 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_w(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
|
|
@ -133,13 +133,13 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x30: /*PUSH w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
|
@ -148,7 +148,7 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
|
||||
x86illegal();
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFF_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -162,19 +162,19 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + 1); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp - 1); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -183,13 +183,13 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_w(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
new_pc = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
|
|
@ -198,13 +198,13 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x30: /*PUSH w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
|
@ -213,7 +213,7 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
|
||||
x86illegal();
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFF_l_a16(uint32_t fetchdat)
|
||||
|
|
@ -228,19 +228,19 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + 1); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp - 1); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(cpu_state.pc);
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -249,13 +249,13 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_l(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
|
|
@ -264,13 +264,13 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x30: /*PUSH l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
|
@ -279,7 +279,7 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
|
||||
x86illegal();
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFF_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -293,20 +293,20 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*INC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + 1); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp - 1); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
PUSH_L(cpu_state.pc); if (abrt) return 1;
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(cpu_state.pc); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
|
|
@ -314,13 +314,13 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (cpu_state.abrt) return 1;
|
||||
|
||||
CALL_FAR_l(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x20: /*JMP*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
new_pc = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
|
|
@ -329,13 +329,13 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
break;
|
||||
case 0x30: /*PUSH l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
|
@ -344,5 +344,5 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
|
||||
x86illegal();
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static int opPUSHF(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
PUSH_W(flags);
|
||||
CLOCK_CYCLES(4);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPUSHFD(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -108,7 +108,7 @@ static int opPUSHFD(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
PUSH_L(flags | (tempw << 16));
|
||||
CLOCK_CYCLES(4);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opPOPF_286(uint32_t fetchdat)
|
||||
|
|
@ -121,7 +121,7 @@ static int opPOPF_286(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
|
||||
tempw = POP_W(); if (abrt) return 1;
|
||||
tempw = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (!(msw & 1)) flags = (flags & 0x7000) | (tempw & 0x0fd5) | 2;
|
||||
else if (!(CPL)) flags = (tempw & 0x7fd5) | 2;
|
||||
|
|
@ -145,7 +145,7 @@ static int opPOPF(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
|
||||
tempw = POP_W(); if (abrt) return 1;
|
||||
tempw = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (!(CPL) || !(msw & 1)) flags = (tempw & 0x7fd5) | 2;
|
||||
else if (IOPLp) flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
|
||||
|
|
@ -168,7 +168,7 @@ static int opPOPFD(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
|
||||
templ = POP_L(); if (abrt) return 1;
|
||||
templ = POP_L(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (!(CPL) || !(msw & 1)) flags = (templ & 0x7fd5) | 2;
|
||||
else if (IOPLp) flags = (flags & 0x3000) | (templ & 0x4fd5) | 2;
|
||||
|
|
|
|||
|
|
@ -49,16 +49,16 @@ static int opINCDEC_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp=geteab(); if (abrt) return 1;
|
||||
temp=geteab(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (rmdat&0x38)
|
||||
{
|
||||
seteab(temp - 1); if (abrt) return 1;
|
||||
seteab(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub8nc(temp, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
seteab(temp + 1); if (abrt) return 1;
|
||||
seteab(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd8nc(temp, 1);
|
||||
}
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
@ -69,16 +69,16 @@ static int opINCDEC_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp=geteab(); if (abrt) return 1;
|
||||
temp=geteab(); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (rmdat&0x38)
|
||||
{
|
||||
seteab(temp - 1); if (abrt) return 1;
|
||||
seteab(temp - 1); if (cpu_state.abrt) return 1;
|
||||
setsub8nc(temp, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
seteab(temp + 1); if (abrt) return 1;
|
||||
seteab(temp + 1); if (cpu_state.abrt) return 1;
|
||||
setadd8nc(temp, 1);
|
||||
}
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@
|
|||
\
|
||||
static int opJ ## condition ## _l(uint32_t fetchdat) \
|
||||
{ \
|
||||
uint32_t offset = getlong(); if (abrt) return 1; \
|
||||
uint32_t offset = getlong(); if (cpu_state.abrt) return 1; \
|
||||
CLOCK_CYCLES(timing_bnt); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
|
|
@ -204,7 +204,7 @@ static int opJMP_r16(uint32_t fetchdat)
|
|||
}
|
||||
static int opJMP_r32(uint32_t fetchdat)
|
||||
{
|
||||
int32_t offset = (int32_t)getlong(); if (abrt) return 1;
|
||||
int32_t offset = (int32_t)getlong(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc += offset;
|
||||
CPU_BLOCK_END();
|
||||
CLOCK_CYCLES((is486) ? 3 : 7);
|
||||
|
|
@ -214,7 +214,7 @@ static int opJMP_r32(uint32_t fetchdat)
|
|||
static int opJMP_far_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint16_t seg = getword(); if (abrt) return 1;
|
||||
uint16_t seg = getword(); if (cpu_state.abrt) return 1;
|
||||
uint32_t oxpc = cpu_state.pc;
|
||||
cpu_state.pc = addr;
|
||||
loadcsjmp(seg, oxpc);
|
||||
|
|
@ -224,7 +224,7 @@ static int opJMP_far_a16(uint32_t fetchdat)
|
|||
static int opJMP_far_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint16_t seg = getword(); if (abrt) return 1;
|
||||
uint16_t seg = getword(); if (cpu_state.abrt) return 1;
|
||||
uint32_t oxpc = cpu_state.pc;
|
||||
cpu_state.pc = addr;
|
||||
loadcsjmp(seg, oxpc);
|
||||
|
|
@ -243,7 +243,7 @@ static int opCALL_r16(uint32_t fetchdat)
|
|||
}
|
||||
static int opCALL_r32(uint32_t fetchdat)
|
||||
{
|
||||
int32_t addr = getlong(); if (abrt) return 1;
|
||||
int32_t addr = getlong(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(cpu_state.pc);
|
||||
cpu_state.pc += addr;
|
||||
CPU_BLOCK_END();
|
||||
|
|
@ -255,7 +255,7 @@ static int opRET_w(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t ret;
|
||||
|
||||
ret = POP_W(); if (abrt) return 1;
|
||||
ret = POP_W(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = ret;
|
||||
CPU_BLOCK_END();
|
||||
|
||||
|
|
@ -266,7 +266,7 @@ static int opRET_l(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t ret;
|
||||
|
||||
ret = POP_L(); if (abrt) return 1;
|
||||
ret = POP_L(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc = ret;
|
||||
CPU_BLOCK_END();
|
||||
|
||||
|
|
@ -279,7 +279,7 @@ static int opRET_w_imm(uint32_t fetchdat)
|
|||
uint16_t offset = getwordf();
|
||||
uint16_t ret;
|
||||
|
||||
ret = POP_W(); if (abrt) return 1;
|
||||
ret = POP_W(); if (cpu_state.abrt) return 1;
|
||||
if (stack32) ESP += offset;
|
||||
else SP += offset;
|
||||
cpu_state.pc = ret;
|
||||
|
|
@ -293,7 +293,7 @@ static int opRET_l_imm(uint32_t fetchdat)
|
|||
uint16_t offset = getwordf();
|
||||
uint32_t ret;
|
||||
|
||||
ret = POP_L(); if (abrt) return 1;
|
||||
ret = POP_L(); if (cpu_state.abrt) return 1;
|
||||
if (stack32) ESP += offset;
|
||||
else SP += offset;
|
||||
cpu_state.pc = ret;
|
||||
|
|
|
|||
|
|
@ -46,21 +46,21 @@ static int opF6_a16(uint32_t fetchdat)
|
|||
int8_t temps;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST b,#8*/
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
|
||||
setznp8(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
seteab(~dst); if (abrt) return 1;
|
||||
seteab(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
seteab(0 - dst); if (abrt) return 1;
|
||||
seteab(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
|
|
@ -136,21 +136,21 @@ static int opF6_a32(uint32_t fetchdat)
|
|||
int8_t temps;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
dst = geteab(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST b,#8*/
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
|
||||
setznp8(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
seteab(~dst); if (abrt) return 1;
|
||||
seteab(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
seteab(0 - dst); if (abrt) return 1;
|
||||
seteab(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
|
|
@ -229,21 +229,21 @@ static int opF7_w_a16(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST w*/
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
setznp16(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
seteaw(~dst); if (abrt) return 1;
|
||||
seteaw(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
seteaw(0 - dst); if (abrt) return 1;
|
||||
seteaw(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
|
|
@ -315,21 +315,21 @@ static int opF7_w_a32(uint32_t fetchdat)
|
|||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
dst = geteaw(); if (cpu_state.abrt) return 1;
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST w*/
|
||||
src = getword(); if (abrt) return 1;
|
||||
src = getword(); if (cpu_state.abrt) return 1;
|
||||
setznp16(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
seteaw(~dst); if (abrt) return 1;
|
||||
seteaw(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
seteaw(0 - dst); if (abrt) return 1;
|
||||
seteaw(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
|
|
@ -400,22 +400,22 @@ static int opF7_l_a16(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST l*/
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
setznp32(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
seteal(~dst); if (abrt) return 1;
|
||||
seteal(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
seteal(0 - dst); if (abrt) return 1;
|
||||
seteal(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
|
|
@ -462,22 +462,22 @@ static int opF7_l_a32(uint32_t fetchdat)
|
|||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
dst = geteal(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*TEST l*/
|
||||
src = getlong(); if (abrt) return 1;
|
||||
src = getlong(); if (cpu_state.abrt) return 1;
|
||||
setznp32(src & dst);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
seteal(~dst); if (abrt) return 1;
|
||||
seteal(~dst); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
seteal(0 - dst); if (abrt) return 1;
|
||||
seteal(0 - dst); if (cpu_state.abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
|
|
@ -544,7 +544,7 @@ static int opHLT(uint32_t fetchdat)
|
|||
static int opLOCK(uint32_t fetchdat)
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
cpu_state.pc++;
|
||||
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -560,7 +560,7 @@ static int opBOUND_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
|
|
@ -578,7 +578,7 @@ static int opBOUND_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
|
|
@ -597,7 +597,7 @@ static int opBOUND_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
|
|
@ -615,7 +615,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
src.q = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1; \
|
||||
src.q = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -295,7 +295,7 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
|
|
@ -322,7 +322,7 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
|
|
@ -350,7 +350,7 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
|
|
@ -377,7 +377,7 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
|
|
@ -36,7 +36,7 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -76,7 +76,7 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -96,7 +96,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -116,7 +116,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -136,7 +136,7 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -154,7 +154,7 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
|
|||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].q); if (abrt) return 1;
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].q); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 0;
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
@ -33,7 +33,7 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 0;
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
} \
|
||||
else \
|
||||
{ \
|
||||
shift = readmemb(easeg, cpu_state.eaaddr); if (abrt) return 0; \
|
||||
shift = readmemb(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -98,56 +98,56 @@ static int opMOV_SP_imm(uint32_t fetchdat)
|
|||
|
||||
static int opMOV_EAX_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
EAX = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_EBX_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
EBX = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_ECX_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
ECX = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_EDX_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
EDX = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_ESI_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
ESI = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_EDI_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
EDI = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_EBP_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
EBP = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opMOV_ESP_imm(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t templ = getlong(); if (abrt) return 1;
|
||||
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
|
||||
ESP = templ;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
|
|
@ -157,64 +157,64 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = readmemb(cs,cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
temp = readmemb(cs,cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_b_imm_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = getbyte(); if (abrt) return 1;
|
||||
temp = getbyte(); if (cpu_state.abrt) return 1;
|
||||
seteab(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opMOV_w_imm_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = getword(); if (abrt) return 1;
|
||||
temp = getword(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_w_imm_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = getword(); if (abrt) return 1;
|
||||
temp = getword(); if (cpu_state.abrt) return 1;
|
||||
seteaw(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_l_imm_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = getlong(); if (abrt) return 1;
|
||||
temp = getlong(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_l_imm_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = getlong(); if (abrt) return 1;
|
||||
temp = getlong(); if (cpu_state.abrt) return 1;
|
||||
seteal(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
||||
static int opMOV_AL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -222,7 +222,7 @@ static int opMOV_AL_a16(uint32_t fetchdat)
|
|||
static int opMOV_AL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -230,7 +230,7 @@ static int opMOV_AL_a32(uint32_t fetchdat)
|
|||
static int opMOV_AX_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -238,7 +238,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
|
|||
static int opMOV_AX_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -246,7 +246,7 @@ static int opMOV_AX_a32(uint32_t fetchdat)
|
|||
static int opMOV_EAX_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -254,7 +254,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
|
|||
static int opMOV_EAX_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
|
|
@ -265,42 +265,42 @@ static int opMOV_a16_AL(uint32_t fetchdat)
|
|||
uint16_t addr = getwordf();
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_a32_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_a16_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_a32_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (abrt) return 1;
|
||||
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_a16_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_a32_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (abrt) return 1;
|
||||
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -343,7 +343,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
|
|||
static int opXLAT_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = (BX + AL)&0xFFFF;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
return 0;
|
||||
|
|
@ -351,7 +351,7 @@ static int opXLAT_a16(uint32_t fetchdat)
|
|||
static int opXLAT_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = EBX + AL;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
return 0;
|
||||
|
|
@ -371,7 +371,7 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
|
|||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_b_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -387,7 +387,7 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
|
|||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_w_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -403,7 +403,7 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
|
|||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_w_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -419,7 +419,7 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
|
|||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_l_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -435,7 +435,7 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
|
|||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_l_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -451,7 +451,7 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
|
|||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opMOV_r_b_a16(uint32_t fetchdat)
|
||||
|
|
@ -466,7 +466,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
|
|
@ -484,7 +484,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
|
|
@ -502,7 +502,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
}
|
||||
|
|
@ -520,7 +520,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
}
|
||||
|
|
@ -538,7 +538,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
|
|
@ -556,7 +556,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp;
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
|
|
@ -575,7 +575,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -593,7 +593,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -611,7 +611,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -629,7 +629,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
temp = geteal(); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_w_seg_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -54,7 +54,7 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opMOV_l_seg_a16(uint32_t fetchdat)
|
||||
|
|
@ -90,7 +90,7 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_l_seg_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -125,7 +125,7 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opMOV_seg_w_a16(uint32_t fetchdat)
|
||||
|
|
@ -134,7 +134,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
new_seg=geteaw(); if (abrt) return 1;
|
||||
new_seg=geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
|
|
@ -146,14 +146,14 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x10: /*SS*/
|
||||
loadseg(new_seg, &_ss);
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return 1;
|
||||
case 0x20: /*FS*/
|
||||
|
|
@ -165,7 +165,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opMOV_seg_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -173,7 +173,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
new_seg=geteaw(); if (abrt) return 1;
|
||||
new_seg=geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
switch (rmdat & 0x38)
|
||||
{
|
||||
|
|
@ -185,14 +185,14 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
|||
break;
|
||||
case 0x10: /*SS*/
|
||||
loadseg(new_seg, &_ss);
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return 1;
|
||||
case 0x20: /*FS*/
|
||||
|
|
@ -204,7 +204,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
|||
}
|
||||
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -215,8 +215,8 @@ static int opLDS_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -229,8 +229,8 @@ static int opLDS_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -244,8 +244,8 @@ static int opLDS_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -259,8 +259,8 @@ static int opLDS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ds); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -274,8 +274,8 @@ static int opLSS_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -288,8 +288,8 @@ static int opLSS_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -303,8 +303,8 @@ static int opLSS_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -318,8 +318,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1;
|
||||
loadseg(seg, &_ss); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -334,8 +334,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
|
||||
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
|
|
@ -349,8 +349,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
|
||||
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
|
|
@ -365,8 +365,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
|
||||
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
|
|
@ -381,8 +381,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
|
||||
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ static int opMOVZX_w_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -14,7 +14,7 @@ static int opMOVZX_w_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -25,7 +25,7 @@ static int opMOVZX_l_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -36,7 +36,7 @@ static int opMOVZX_l_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -47,7 +47,7 @@ static int opMOVZX_w_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -58,7 +58,7 @@ static int opMOVZX_w_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -69,7 +69,7 @@ static int opMOVZX_l_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -80,7 +80,7 @@ static int opMOVZX_l_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -92,7 +92,7 @@ static int opMOVSX_w_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[cpu_reg].w |= 0xff00;
|
||||
|
|
@ -105,7 +105,7 @@ static int opMOVSX_w_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[cpu_reg].w |= 0xff00;
|
||||
|
|
@ -118,7 +118,7 @@ static int opMOVSX_l_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[cpu_reg].l |= 0xffffff00;
|
||||
|
|
@ -131,7 +131,7 @@ static int opMOVSX_l_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[cpu_reg].l |= 0xffffff00;
|
||||
|
|
@ -144,7 +144,7 @@ static int opMOVSX_l_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
cpu_state.regs[cpu_reg].l |= 0xffff0000;
|
||||
|
|
@ -157,7 +157,7 @@ static int opMOVSX_l_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
cpu_state.regs[cpu_reg].l |= 0xffff0000;
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
tempw = geteaw(); if (abrt) return 1;
|
||||
tempw2 = getword(); if (abrt) return 1;
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
templ = ((int)tempw) * ((int)tempw2);
|
||||
flags_rebuild();
|
||||
|
|
@ -24,8 +24,8 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
tempw = geteaw(); if (abrt) return 1;
|
||||
tempw2 = getword(); if (abrt) return 1;
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getword(); if (cpu_state.abrt) return 1;
|
||||
|
||||
templ = ((int)tempw) * ((int)tempw2);
|
||||
flags_rebuild();
|
||||
|
|
@ -44,8 +44,8 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ2 = getlong(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getlong(); if (cpu_state.abrt) return 1;
|
||||
|
||||
temp64 = ((int64_t)templ) * ((int64_t)templ2);
|
||||
flags_rebuild();
|
||||
|
|
@ -63,8 +63,8 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ2 = getlong(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getlong(); if (cpu_state.abrt) return 1;
|
||||
|
||||
temp64 = ((int64_t)templ) * ((int64_t)templ2);
|
||||
flags_rebuild();
|
||||
|
|
@ -83,8 +83,8 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
tempw = geteaw(); if (abrt) return 1;
|
||||
tempw2 = getbyte(); if (abrt) return 1;
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (tempw2 & 0x80) tempw2 |= 0xff00;
|
||||
|
||||
templ = ((int)tempw) * ((int)tempw2);
|
||||
|
|
@ -103,8 +103,8 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
tempw = geteaw(); if (abrt) return 1;
|
||||
tempw2 = getbyte(); if (abrt) return 1;
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
tempw2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (tempw2 & 0x80) tempw2 |= 0xff00;
|
||||
|
||||
templ = ((int)tempw) * ((int)tempw2);
|
||||
|
|
@ -123,8 +123,8 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ2 = getbyte(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (templ2 & 0x80) templ2 |= 0xffffff00;
|
||||
|
||||
temp64 = ((int64_t)templ)*((int64_t)templ2);
|
||||
|
|
@ -142,8 +142,8 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
|
|||
int32_t templ, templ2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ2 = getbyte(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
templ2 = getbyte(); if (cpu_state.abrt) return 1;
|
||||
if (templ2 & 0x80) templ2 |= 0xffffff00;
|
||||
|
||||
temp64 = ((int64_t)templ)*((int64_t)templ2);
|
||||
|
|
@ -164,7 +164,7 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
|
|
@ -179,7 +179,7 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
|
|
@ -195,7 +195,7 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
|
|
@ -210,7 +210,7 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ static int opARPL_a16(uint32_t fetchdat)
|
|||
NOTRM
|
||||
fetch_ea_16(fetchdat);
|
||||
pclog("ARPL_a16\n");
|
||||
temp_seg = geteaw(); if (abrt) return 1;
|
||||
temp_seg = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
flags_rebuild();
|
||||
if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
|
||||
{
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
|
||||
seteaw(temp_seg); if (abrt) return 1;
|
||||
seteaw(temp_seg); if (cpu_state.abrt) return 1;
|
||||
flags |= Z_FLAG;
|
||||
}
|
||||
else
|
||||
|
|
@ -27,13 +27,13 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
NOTRM
|
||||
fetch_ea_32(fetchdat);
|
||||
pclog("ARPL_a32\n");
|
||||
temp_seg = geteaw(); if (abrt) return 1;
|
||||
temp_seg = geteaw(); if (cpu_state.abrt) return 1;
|
||||
|
||||
flags_rebuild();
|
||||
if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
|
||||
{
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
|
||||
seteaw(temp_seg); if (abrt) return 1;
|
||||
seteaw(temp_seg); if (cpu_state.abrt) return 1;
|
||||
flags |= Z_FLAG;
|
||||
}
|
||||
else
|
||||
|
|
@ -52,7 +52,7 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
NOTRM \
|
||||
fetch_ea(fetchdat); \
|
||||
\
|
||||
sel = geteaw(); if (abrt) return 1; \
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
\
|
||||
flags_rebuild(); \
|
||||
if (!(sel & 0xfffc)) { flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
|
||||
|
|
@ -61,7 +61,7 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
cpl_override = 1; \
|
||||
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
|
||||
cpl_override = 0; if (abrt) return 1; \
|
||||
cpl_override = 0; if (cpu_state.abrt) return 1; \
|
||||
} \
|
||||
flags &= ~Z_FLAG; \
|
||||
if ((desc & 0x1f00) == 0x000) valid = 0; \
|
||||
|
|
@ -84,7 +84,7 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
cpl_override = 0; \
|
||||
} \
|
||||
CLOCK_CYCLES(11); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
opLAR(w_a16, fetch_ea_16, 0)
|
||||
|
|
@ -101,7 +101,7 @@ opLAR(l_a32, fetch_ea_32, 1)
|
|||
NOTRM \
|
||||
fetch_ea(fetchdat); \
|
||||
\
|
||||
sel = geteaw(); if (abrt) return 1; \
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
flags &= ~Z_FLAG; \
|
||||
if (!(sel & 0xfffc)) return 0; /*Null selector*/ \
|
||||
|
|
@ -110,7 +110,7 @@ opLAR(l_a32, fetch_ea_32, 1)
|
|||
{ \
|
||||
cpl_override = 1; \
|
||||
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
|
||||
cpl_override = 0; if (abrt) return 1; \
|
||||
cpl_override = 0; if (cpu_state.abrt) return 1; \
|
||||
} \
|
||||
if ((desc & 0x1400) == 0x400) valid = 0; /*Interrupt or trap or call gate*/ \
|
||||
if ((desc & 0x1f00) == 0x000) valid = 0; /*Invalid*/ \
|
||||
|
|
@ -139,7 +139,7 @@ opLAR(l_a32, fetch_ea_32, 1)
|
|||
cpl_override = 0; \
|
||||
} \
|
||||
CLOCK_CYCLES(10); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
opLSL(w_a16, fetch_ea_16, 0)
|
||||
|
|
@ -173,13 +173,13 @@ static int op0F00_common(uint32_t fetchdat)
|
|||
x86gpf(NULL,0);
|
||||
return 1;
|
||||
}
|
||||
sel = geteaw(); if (abrt) return 1;
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
addr = (sel & ~7) + gdt.base;
|
||||
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
|
||||
base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
|
||||
access = readmemb(0, addr + 5);
|
||||
granularity = readmemb(0, addr + 6) & 0x80;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
ldt.limit = limit;
|
||||
ldt.access = access;
|
||||
if (granularity)
|
||||
|
|
@ -198,13 +198,13 @@ static int op0F00_common(uint32_t fetchdat)
|
|||
x86gpf(NULL,0);
|
||||
break;
|
||||
}
|
||||
sel = geteaw(); if (abrt) return 1;
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
addr = (sel & ~7) + gdt.base;
|
||||
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
|
||||
base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
|
||||
access = readmemb(0, addr + 5);
|
||||
granularity = readmemb(0, addr + 6) & 0x80;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
tr.seg = sel;
|
||||
tr.limit = limit;
|
||||
tr.access = access;
|
||||
|
|
@ -217,14 +217,14 @@ static int op0F00_common(uint32_t fetchdat)
|
|||
CLOCK_CYCLES(20);
|
||||
break;
|
||||
case 0x20: /*VERR*/
|
||||
sel = geteaw(); if (abrt) return 1;
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
flags &= ~Z_FLAG;
|
||||
if (!(sel & 0xfffc)) return 0; /*Null selector*/
|
||||
cpl_override = 1;
|
||||
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
|
||||
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
|
||||
cpl_override = 0; if (abrt) return 1;
|
||||
cpl_override = 0; if (cpu_state.abrt) return 1;
|
||||
if (!(desc & 0x1000)) valid = 0;
|
||||
if ((desc & 0xC00) != 0xC00) /*Exclude conforming code segments*/
|
||||
{
|
||||
|
|
@ -236,14 +236,14 @@ static int op0F00_common(uint32_t fetchdat)
|
|||
CLOCK_CYCLES(20);
|
||||
break;
|
||||
case 0x28: /*VERW*/
|
||||
sel = geteaw(); if (abrt) return 1;
|
||||
sel = geteaw(); if (cpu_state.abrt) return 1;
|
||||
flags_rebuild();
|
||||
flags &= ~Z_FLAG;
|
||||
if (!(sel & 0xfffc)) return 0; /*Null selector*/
|
||||
cpl_override = 1;
|
||||
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
|
||||
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
|
||||
cpl_override = 0; if (abrt) return 1;
|
||||
cpl_override = 0; if (cpu_state.abrt) return 1;
|
||||
if (!(desc & 0x1000)) valid = 0;
|
||||
dpl = (desc >> 13) & 3; /*Check permissions*/
|
||||
if (dpl < CPL || dpl < (sel & 3)) valid = 0;
|
||||
|
|
@ -259,7 +259,7 @@ static int op0F00_common(uint32_t fetchdat)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int op0F00_a16(uint32_t fetchdat)
|
||||
|
|
@ -311,7 +311,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
|||
}
|
||||
// pclog("LGDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
// pclog(" %08X %04X\n", base, limit);
|
||||
gdt.limit = limit;
|
||||
gdt.base = base;
|
||||
|
|
@ -327,7 +327,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
|||
}
|
||||
// pclog("LIDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
|
||||
// pclog(" %08X %04X\n", base, limit);
|
||||
idt.limit = limit;
|
||||
idt.base = base;
|
||||
|
|
@ -347,7 +347,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
|||
x86gpf(NULL, 0);
|
||||
break;
|
||||
}
|
||||
tempw = geteaw(); if (abrt) return 1;
|
||||
tempw = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (msw & 1) tempw |= 1;
|
||||
msw = tempw;
|
||||
break;
|
||||
|
|
@ -372,7 +372,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
|||
x86illegal();
|
||||
break;
|
||||
}
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int op0F01_w_a16(uint32_t fetchdat)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
static int op ## name ## _w_a16(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetchdat = fastreadl(cs + cpu_state.pc); \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
cpu_state.ea_seg = &seg; \
|
||||
|
|
@ -15,7 +15,7 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
|
|||
static int op ## name ## _l_a16(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetchdat = fastreadl(cs + cpu_state.pc); \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
cpu_state.ea_seg = &seg; \
|
||||
|
|
@ -28,7 +28,7 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
|
|||
static int op ## name ## _w_a32(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetchdat = fastreadl(cs + cpu_state.pc); \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
cpu_state.ea_seg = &seg; \
|
||||
|
|
@ -41,7 +41,7 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
|
|||
static int op ## name ## _l_a32(uint32_t fetchdat) \
|
||||
{ \
|
||||
fetchdat = fastreadl(cs + cpu_state.pc); \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
cpu_state.ea_seg = &seg; \
|
||||
|
|
@ -61,7 +61,7 @@ op_seg(SS, _ss)
|
|||
static int op_66(uint32_t fetchdat) /*Data size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
|
||||
|
|
@ -71,7 +71,7 @@ static int op_66(uint32_t fetchdat) /*Data size select*/
|
|||
static int op_67(uint32_t fetchdat) /*Address size select*/
|
||||
{
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
cpu_state.pc = readmemw(ss, SP); \
|
||||
loadcs(readmemw(ss, SP + 2)); \
|
||||
} \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
if (stack32) ESP += 4 + stack_offset; \
|
||||
else SP += 4 + stack_offset; \
|
||||
cycles -= timing_retf_rm;
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
cpu_state.pc = readmeml(ss, SP); \
|
||||
loadcs(readmeml(ss, SP + 4) & 0xffff); \
|
||||
} \
|
||||
if (abrt) return 1; \
|
||||
if (cpu_state.abrt) return 1; \
|
||||
if (stack32) ESP += 8 + stack_offset; \
|
||||
else SP += 8 + stack_offset; \
|
||||
cycles -= timing_retf_rm;
|
||||
|
|
@ -107,7 +107,7 @@ static int opIRET_286(uint32_t fetchdat)
|
|||
flags_extract();
|
||||
nmi_enable = 1;
|
||||
CPU_BLOCK_END();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opIRET(uint32_t fetchdat)
|
||||
|
|
@ -147,7 +147,7 @@ static int opIRET(uint32_t fetchdat)
|
|||
flags_extract();
|
||||
nmi_enable = 1;
|
||||
CPU_BLOCK_END();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opIRETD(uint32_t fetchdat)
|
||||
|
|
@ -189,6 +189,6 @@ static int opIRETD(uint32_t fetchdat)
|
|||
flags_extract();
|
||||
nmi_enable = 1;
|
||||
CPU_BLOCK_END();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
fetch_ea_16(fetchdat); \
|
||||
seteab((cond_ ## condition) ? 1 : 0); \
|
||||
CLOCK_CYCLES(4); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
\
|
||||
static int opSET ## condition ## _a32(uint32_t fetchdat) \
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
fetch_ea_32(fetchdat); \
|
||||
seteab((cond_ ## condition) ? 1 : 0); \
|
||||
CLOCK_CYCLES(4); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
opSET(O)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
temp = (temp << 1) | temp2; \
|
||||
c--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
seteab(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
if (temp2) temp |= 0x80; \
|
||||
c--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
seteab(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
seteab(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
|
|
@ -58,25 +58,25 @@
|
|||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
seteab(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL b,CL*/ \
|
||||
seteab(temp << c); if (abrt) return 1; \
|
||||
seteab(temp << c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR b,CL*/ \
|
||||
seteab(temp >> c); if (abrt) return 1; \
|
||||
seteab(temp >> c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR b,CL*/ \
|
||||
temp = (int8_t)temp >> c; \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
seteab(temp); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
|
|
@ -97,7 +97,7 @@
|
|||
temp = (temp << 1) | temp2; \
|
||||
c--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
|
|
@ -111,7 +111,7 @@
|
|||
if (temp2) temp |= 0x8000; \
|
||||
c--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
|
|
@ -127,7 +127,7 @@
|
|||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
|
|
@ -143,25 +143,25 @@
|
|||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL w, c*/ \
|
||||
seteaw(temp << c); if (abrt) return 1; \
|
||||
seteaw(temp << c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR w, c*/ \
|
||||
seteaw(temp >> c); if (abrt) return 1; \
|
||||
seteaw(temp >> c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR w, c*/ \
|
||||
temp = (int16_t)temp >> c; \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
seteaw(temp); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
|
|
@ -182,7 +182,7 @@
|
|||
temp = (temp << 1) | temp2; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
|
|
@ -196,7 +196,7 @@
|
|||
if (temp2) temp |= 0x80000000; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
|
|
@ -212,7 +212,7 @@
|
|||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
|
|
@ -228,25 +228,25 @@
|
|||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||
seteal(temp << c); if (abrt) return 1; \
|
||||
seteal(temp << c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR l, c*/ \
|
||||
seteal(temp >> c); if (abrt) return 1; \
|
||||
seteal(temp >> c); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR l, c*/ \
|
||||
temp = (int32_t)temp >> c; \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
seteal(temp); if (cpu_state.abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
|
|
@ -261,7 +261,7 @@ static int opC0_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -273,7 +273,7 @@ static int opC0_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -285,7 +285,7 @@ static int opC1_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -297,7 +297,7 @@ static int opC1_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -309,7 +309,7 @@ static int opC1_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -321,7 +321,7 @@ static int opC1_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -333,7 +333,7 @@ static int opD0_a16(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -344,7 +344,7 @@ static int opD0_a32(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -355,7 +355,7 @@ static int opD1_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -366,7 +366,7 @@ static int opD1_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -377,7 +377,7 @@ static int opD1_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -388,7 +388,7 @@ static int opD1_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -401,7 +401,7 @@ static int opD2_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -413,7 +413,7 @@ static int opD2_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_b(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -425,7 +425,7 @@ static int opD3_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -437,7 +437,7 @@ static int opD3_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_w(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -449,7 +449,7 @@ static int opD3_l_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -461,7 +461,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
c = CL & 31;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
OP_SHIFT_l(c);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -470,12 +470,12 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
#define SHLD_w() \
|
||||
if (count) \
|
||||
{ \
|
||||
uint16_t tempw = geteaw(); if (abrt) return 1; \
|
||||
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
int tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
|
||||
uint32_t templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
|
||||
if (count <= 16) tempw = templ >> (16 - count); \
|
||||
else tempw = (templ << count) >> 16; \
|
||||
seteaw(tempw); if (abrt) return 1; \
|
||||
seteaw(tempw); if (cpu_state.abrt) return 1; \
|
||||
setznp16(tempw); \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -484,10 +484,10 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
#define SHLD_l() \
|
||||
if (count) \
|
||||
{ \
|
||||
uint32_t templ = geteal(); if (abrt) return 1; \
|
||||
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
|
||||
int tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
|
||||
templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
|
||||
seteal(templ); if (abrt) return 1; \
|
||||
seteal(templ); if (cpu_state.abrt) return 1; \
|
||||
setznp32(templ); \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -497,11 +497,11 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
#define SHRD_w() \
|
||||
if (count) \
|
||||
{ \
|
||||
uint16_t tempw = geteaw(); if (abrt) return 1; \
|
||||
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
|
||||
int tempc = (tempw >> (count - 1)) & 1; \
|
||||
uint32_t templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
|
||||
tempw = templ >> count; \
|
||||
seteaw(tempw); if (abrt) return 1; \
|
||||
seteaw(tempw); if (cpu_state.abrt) return 1; \
|
||||
setznp16(tempw); \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -510,10 +510,10 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
#define SHRD_l() \
|
||||
if (count) \
|
||||
{ \
|
||||
uint32_t templ = geteal(); if (abrt) return 1; \
|
||||
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
|
||||
int tempc = (templ >> (count - 1)) & 1; \
|
||||
templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
|
||||
seteal(templ); if (abrt) return 1; \
|
||||
seteal(templ); if (cpu_state.abrt) return 1; \
|
||||
setznp32(templ); \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
{ \
|
||||
PUSH_W(reg); \
|
||||
CLOCK_CYCLES((is486) ? 1 : 2); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
#define PUSH_L_OP(reg) \
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
{ \
|
||||
PUSH_L(reg); \
|
||||
CLOCK_CYCLES((is486) ? 1 : 2); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
#define POP_W_OP(reg) \
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
{ \
|
||||
reg = POP_W(); \
|
||||
CLOCK_CYCLES((is486) ? 1 : 4); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
#define POP_L_OP(reg) \
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
{ \
|
||||
reg = POP_L(); \
|
||||
CLOCK_CYCLES((is486) ? 1 : 4); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
PUSH_W_OP(AX)
|
||||
|
|
@ -79,7 +79,7 @@ static int opPUSHA_w(uint32_t fetchdat)
|
|||
writememw(ss, ESP - 12, BP);
|
||||
writememw(ss, ESP - 14, SI);
|
||||
writememw(ss, ESP - 16, DI);
|
||||
if (!abrt) ESP -= 16;
|
||||
if (!cpu_state.abrt) ESP -= 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -91,10 +91,10 @@ static int opPUSHA_w(uint32_t fetchdat)
|
|||
writememw(ss, ((SP - 12) & 0xFFFF), BP);
|
||||
writememw(ss, ((SP - 14) & 0xFFFF), SI);
|
||||
writememw(ss, ((SP - 16) & 0xFFFF), DI);
|
||||
if (!abrt) SP -= 16;
|
||||
if (!cpu_state.abrt) SP -= 16;
|
||||
}
|
||||
CLOCK_CYCLES((is486) ? 11 : 18);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPUSHA_l(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -108,7 +108,7 @@ static int opPUSHA_l(uint32_t fetchdat)
|
|||
writememl(ss, ESP - 24, EBP);
|
||||
writememl(ss, ESP - 28, ESI);
|
||||
writememl(ss, ESP - 32, EDI);
|
||||
if (!abrt) ESP -= 32;
|
||||
if (!cpu_state.abrt) ESP -= 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -120,34 +120,34 @@ static int opPUSHA_l(uint32_t fetchdat)
|
|||
writememl(ss, ((SP - 24) & 0xFFFF), EBP);
|
||||
writememl(ss, ((SP - 28) & 0xFFFF), ESI);
|
||||
writememl(ss, ((SP - 32) & 0xFFFF), EDI);
|
||||
if (!abrt) SP -= 32;
|
||||
if (!cpu_state.abrt) SP -= 32;
|
||||
}
|
||||
CLOCK_CYCLES((is486) ? 11 : 18);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opPOPA_w(uint32_t fetchdat)
|
||||
{
|
||||
if (stack32)
|
||||
{
|
||||
DI = readmemw(ss, ESP); if (abrt) return 1;
|
||||
SI = readmemw(ss, ESP + 2); if (abrt) return 1;
|
||||
BP = readmemw(ss, ESP + 4); if (abrt) return 1;
|
||||
BX = readmemw(ss, ESP + 8); if (abrt) return 1;
|
||||
DX = readmemw(ss, ESP + 10); if (abrt) return 1;
|
||||
CX = readmemw(ss, ESP + 12); if (abrt) return 1;
|
||||
AX = readmemw(ss, ESP + 14); if (abrt) return 1;
|
||||
DI = readmemw(ss, ESP); if (cpu_state.abrt) return 1;
|
||||
SI = readmemw(ss, ESP + 2); if (cpu_state.abrt) return 1;
|
||||
BP = readmemw(ss, ESP + 4); if (cpu_state.abrt) return 1;
|
||||
BX = readmemw(ss, ESP + 8); if (cpu_state.abrt) return 1;
|
||||
DX = readmemw(ss, ESP + 10); if (cpu_state.abrt) return 1;
|
||||
CX = readmemw(ss, ESP + 12); if (cpu_state.abrt) return 1;
|
||||
AX = readmemw(ss, ESP + 14); if (cpu_state.abrt) return 1;
|
||||
ESP += 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
DI = readmemw(ss, ((SP) & 0xFFFF)); if (abrt) return 1;
|
||||
SI = readmemw(ss, ((SP + 2) & 0xFFFF)); if (abrt) return 1;
|
||||
BP = readmemw(ss, ((SP + 4) & 0xFFFF)); if (abrt) return 1;
|
||||
BX = readmemw(ss, ((SP + 8) & 0xFFFF)); if (abrt) return 1;
|
||||
DX = readmemw(ss, ((SP + 10) & 0xFFFF)); if (abrt) return 1;
|
||||
CX = readmemw(ss, ((SP + 12) & 0xFFFF)); if (abrt) return 1;
|
||||
AX = readmemw(ss, ((SP + 14) & 0xFFFF)); if (abrt) return 1;
|
||||
DI = readmemw(ss, ((SP) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
SI = readmemw(ss, ((SP + 2) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
BP = readmemw(ss, ((SP + 4) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
BX = readmemw(ss, ((SP + 8) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
DX = readmemw(ss, ((SP + 10) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
CX = readmemw(ss, ((SP + 12) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
AX = readmemw(ss, ((SP + 14) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
SP += 16;
|
||||
}
|
||||
CLOCK_CYCLES((is486) ? 9 : 24);
|
||||
|
|
@ -157,24 +157,24 @@ static int opPOPA_l(uint32_t fetchdat)
|
|||
{
|
||||
if (stack32)
|
||||
{
|
||||
EDI = readmeml(ss, ESP); if (abrt) return 1;
|
||||
ESI = readmeml(ss, ESP + 4); if (abrt) return 1;
|
||||
EBP = readmeml(ss, ESP + 8); if (abrt) return 1;
|
||||
EBX = readmeml(ss, ESP + 16); if (abrt) return 1;
|
||||
EDX = readmeml(ss, ESP + 20); if (abrt) return 1;
|
||||
ECX = readmeml(ss, ESP + 24); if (abrt) return 1;
|
||||
EAX = readmeml(ss, ESP + 28); if (abrt) return 1;
|
||||
EDI = readmeml(ss, ESP); if (cpu_state.abrt) return 1;
|
||||
ESI = readmeml(ss, ESP + 4); if (cpu_state.abrt) return 1;
|
||||
EBP = readmeml(ss, ESP + 8); if (cpu_state.abrt) return 1;
|
||||
EBX = readmeml(ss, ESP + 16); if (cpu_state.abrt) return 1;
|
||||
EDX = readmeml(ss, ESP + 20); if (cpu_state.abrt) return 1;
|
||||
ECX = readmeml(ss, ESP + 24); if (cpu_state.abrt) return 1;
|
||||
EAX = readmeml(ss, ESP + 28); if (cpu_state.abrt) return 1;
|
||||
ESP += 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
EDI = readmeml(ss, ((SP) & 0xFFFF)); if (abrt) return 1;
|
||||
ESI = readmeml(ss, ((SP + 4) & 0xFFFF)); if (abrt) return 1;
|
||||
EBP = readmeml(ss, ((SP + 8) & 0xFFFF)); if (abrt) return 1;
|
||||
EBX = readmeml(ss, ((SP + 16) & 0xFFFF)); if (abrt) return 1;
|
||||
EDX = readmeml(ss, ((SP + 20) & 0xFFFF)); if (abrt) return 1;
|
||||
ECX = readmeml(ss, ((SP + 24) & 0xFFFF)); if (abrt) return 1;
|
||||
EAX = readmeml(ss, ((SP + 28) & 0xFFFF)); if (abrt) return 1;
|
||||
EDI = readmeml(ss, ((SP) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
ESI = readmeml(ss, ((SP + 4) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
EBP = readmeml(ss, ((SP + 8) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
EBX = readmeml(ss, ((SP + 16) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
EDX = readmeml(ss, ((SP + 20) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
ECX = readmeml(ss, ((SP + 24) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
EAX = readmeml(ss, ((SP + 28) & 0xFFFF)); if (cpu_state.abrt) return 1;
|
||||
SP += 32;
|
||||
}
|
||||
CLOCK_CYCLES((is486) ? 9 : 24);
|
||||
|
|
@ -186,14 +186,14 @@ static int opPUSH_imm_w(uint32_t fetchdat)
|
|||
uint16_t val = getwordf();
|
||||
PUSH_W(val);
|
||||
CLOCK_CYCLES(2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPUSH_imm_l(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t val = getlong(); if (abrt) return 1;
|
||||
uint32_t val = getlong(); if (cpu_state.abrt) return 1;
|
||||
PUSH_L(val);
|
||||
CLOCK_CYCLES(2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opPUSH_imm_bw(uint32_t fetchdat)
|
||||
|
|
@ -204,7 +204,7 @@ static int opPUSH_imm_bw(uint32_t fetchdat)
|
|||
PUSH_W(tempw);
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPUSH_imm_bl(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -214,18 +214,18 @@ static int opPUSH_imm_bl(uint32_t fetchdat)
|
|||
PUSH_L(templ);
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opPOPW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
temp = POP_W(); if (abrt) return 1;
|
||||
temp = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
seteaw(temp);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
if (stack32) ESP -= 2;
|
||||
else SP -= 2;
|
||||
|
|
@ -233,17 +233,17 @@ static int opPOPW_a16(uint32_t fetchdat)
|
|||
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPOPW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp;
|
||||
|
||||
temp = POP_W(); if (abrt) return 1;
|
||||
temp = POP_W(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
seteaw(temp);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
if (stack32) ESP -= 2;
|
||||
else SP -= 2;
|
||||
|
|
@ -251,18 +251,18 @@ static int opPOPW_a32(uint32_t fetchdat)
|
|||
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opPOPL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
temp = POP_L(); if (abrt) return 1;
|
||||
temp = POP_L(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
seteal(temp);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
if (stack32) ESP -= 4;
|
||||
else SP -= 4;
|
||||
|
|
@ -270,17 +270,17 @@ static int opPOPL_a16(uint32_t fetchdat)
|
|||
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opPOPL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
temp = POP_L(); if (abrt) return 1;
|
||||
temp = POP_L(); if (cpu_state.abrt) return 1;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
seteal(temp);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
if (stack32) ESP -= 4;
|
||||
else SP -= 4;
|
||||
|
|
@ -288,7 +288,7 @@ static int opPOPL_a32(uint32_t fetchdat)
|
|||
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -298,7 +298,7 @@ static int opENTER_w(uint32_t fetchdat)
|
|||
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
|
||||
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
|
||||
|
||||
PUSH_W(BP); if (abrt) return 1;
|
||||
PUSH_W(BP); if (cpu_state.abrt) return 1;
|
||||
frame_ptr = ESP;
|
||||
|
||||
if (count > 0)
|
||||
|
|
@ -309,13 +309,13 @@ static int opENTER_w(uint32_t fetchdat)
|
|||
|
||||
BP -= 2;
|
||||
tempw = readmemw(ss, BP);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
PUSH_W(tempw);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
CLOCK_CYCLES((is486) ? 3 : 4);
|
||||
}
|
||||
PUSH_W(frame_ptr);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
CLOCK_CYCLES((is486) ? 3 : 5);
|
||||
}
|
||||
BP = frame_ptr;
|
||||
|
|
@ -331,7 +331,7 @@ static int opENTER_l(uint32_t fetchdat)
|
|||
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
|
||||
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
|
||||
|
||||
PUSH_L(EBP); if (abrt) return 1;
|
||||
PUSH_L(EBP); if (cpu_state.abrt) return 1;
|
||||
frame_ptr = ESP;
|
||||
|
||||
if (count > 0)
|
||||
|
|
@ -342,13 +342,13 @@ static int opENTER_l(uint32_t fetchdat)
|
|||
|
||||
EBP -= 4;
|
||||
templ = readmeml(ss, EBP);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
PUSH_L(templ);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
CLOCK_CYCLES((is486) ? 3 : 4);
|
||||
}
|
||||
PUSH_L(frame_ptr);
|
||||
if (abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
|
||||
CLOCK_CYCLES((is486) ? 3 : 5);
|
||||
}
|
||||
EBP = frame_ptr;
|
||||
|
|
@ -367,7 +367,7 @@ static int opLEAVE_w(uint32_t fetchdat)
|
|||
|
||||
SP = BP;
|
||||
temp = POP_W();
|
||||
if (abrt) { ESP = tempESP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; return 1; }
|
||||
BP = temp;
|
||||
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -380,7 +380,7 @@ static int opLEAVE_l(uint32_t fetchdat)
|
|||
|
||||
ESP = EBP;
|
||||
temp = POP_L();
|
||||
if (abrt) { ESP = tempESP; return 1; }
|
||||
if (cpu_state.abrt) { ESP = tempESP; return 1; }
|
||||
EBP = temp;
|
||||
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -393,13 +393,13 @@ static int opLEAVE_l(uint32_t fetchdat)
|
|||
{ \
|
||||
PUSH_W(seg); \
|
||||
CLOCK_CYCLES(2); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opPUSH_ ## seg ## _l(uint32_t fetchdat) \
|
||||
{ \
|
||||
PUSH_L(seg); \
|
||||
CLOCK_CYCLES(2); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
#define POP_SEG_OPS(seg, realseg) \
|
||||
|
|
@ -407,19 +407,19 @@ static int opLEAVE_l(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t temp_seg; \
|
||||
uint32_t temp_esp = ESP; \
|
||||
temp_seg = POP_W(); if (abrt) return 1; \
|
||||
loadseg(temp_seg, realseg); if (abrt) ESP = temp_esp; \
|
||||
temp_seg = POP_W(); if (cpu_state.abrt) return 1; \
|
||||
loadseg(temp_seg, realseg); if (cpu_state.abrt) ESP = temp_esp; \
|
||||
CLOCK_CYCLES(is486 ? 3 : 7); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
} \
|
||||
static int opPOP_ ## seg ## _l(uint32_t fetchdat) \
|
||||
{ \
|
||||
uint32_t temp_seg; \
|
||||
uint32_t temp_esp = ESP; \
|
||||
temp_seg = POP_L(); if (abrt) return 1; \
|
||||
loadseg(temp_seg & 0xffff, realseg); if (abrt) ESP = temp_esp; \
|
||||
temp_seg = POP_L(); if (cpu_state.abrt) return 1; \
|
||||
loadseg(temp_seg & 0xffff, realseg); if (cpu_state.abrt) ESP = temp_esp; \
|
||||
CLOCK_CYCLES(is486 ? 3 : 7); \
|
||||
return abrt; \
|
||||
return cpu_state.abrt; \
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -440,8 +440,8 @@ static int opPOP_SS_w(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp_seg;
|
||||
uint32_t temp_esp = ESP;
|
||||
temp_seg = POP_W(); if (abrt) return 1;
|
||||
loadseg(temp_seg, &_ss); if (abrt) { ESP = temp_esp; return 1; }
|
||||
temp_seg = POP_W(); if (cpu_state.abrt) return 1;
|
||||
loadseg(temp_seg, &_ss); if (cpu_state.abrt) { ESP = temp_esp; return 1; }
|
||||
CLOCK_CYCLES(is486 ? 3 : 7);
|
||||
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
|
|
@ -450,7 +450,7 @@ static int opPOP_SS_w(uint32_t fetchdat)
|
|||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
|
||||
return 1;
|
||||
|
|
@ -459,8 +459,8 @@ static int opPOP_SS_l(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp_seg;
|
||||
uint32_t temp_esp = ESP;
|
||||
temp_seg = POP_L(); if (abrt) return 1;
|
||||
loadseg(temp_seg & 0xffff, &_ss); if (abrt) { ESP = temp_esp; return 1; }
|
||||
temp_seg = POP_L(); if (cpu_state.abrt) return 1;
|
||||
loadseg(temp_seg & 0xffff, &_ss); if (cpu_state.abrt) { ESP = temp_esp; return 1; }
|
||||
CLOCK_CYCLES(is486 ? 3 : 7);
|
||||
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
|
|
@ -469,7 +469,7 @@ static int opPOP_SS_l(uint32_t fetchdat)
|
|||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
static int opMOVSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememb(es, DI, temp); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -9,8 +9,8 @@ static int opMOVSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememb(es, EDI, temp); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -19,8 +19,8 @@ static int opMOVSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opMOVSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememw(es, DI, temp); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
else { DI += 2; SI += 2; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -28,8 +28,8 @@ static int opMOVSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememw(es, EDI, temp); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
else { EDI += 2; ESI += 2; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -38,8 +38,8 @@ static int opMOVSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opMOVSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememl(es, DI, temp); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
else { DI += 4; SI += 4; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -47,8 +47,8 @@ static int opMOVSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opMOVSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememl(es, EDI, temp); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
else { EDI += 4; ESI += 4; }
|
||||
CLOCK_CYCLES(7);
|
||||
|
|
@ -59,7 +59,7 @@ static int opMOVSL_a32(uint32_t fetchdat)
|
|||
static int opCMPSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, SI);
|
||||
uint8_t dst = readmemb(es, DI); if (abrt) return 1;
|
||||
uint8_t dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
|
|
@ -69,7 +69,7 @@ static int opCMPSB_a16(uint32_t fetchdat)
|
|||
static int opCMPSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
uint8_t dst = readmemb(es, EDI); if (abrt) return 1;
|
||||
uint8_t dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
|
|
@ -80,7 +80,7 @@ static int opCMPSB_a32(uint32_t fetchdat)
|
|||
static int opCMPSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, SI);
|
||||
uint16_t dst = readmemw(es, DI); if (abrt) return 1;
|
||||
uint16_t dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
else { DI += 2; SI += 2; }
|
||||
|
|
@ -90,7 +90,7 @@ static int opCMPSW_a16(uint32_t fetchdat)
|
|||
static int opCMPSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
uint16_t dst = readmemw(es, EDI); if (abrt) return 1;
|
||||
uint16_t dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
else { EDI += 2; ESI += 2; }
|
||||
|
|
@ -101,7 +101,7 @@ static int opCMPSW_a32(uint32_t fetchdat)
|
|||
static int opCMPSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, SI);
|
||||
uint32_t dst = readmeml(es, DI); if (abrt) return 1;
|
||||
uint32_t dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
else { DI += 4; SI += 4; }
|
||||
|
|
@ -111,7 +111,7 @@ static int opCMPSL_a16(uint32_t fetchdat)
|
|||
static int opCMPSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
uint32_t dst = readmeml(es, EDI); if (abrt) return 1;
|
||||
uint32_t dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
else { EDI += 4; ESI += 4; }
|
||||
|
|
@ -121,7 +121,7 @@ static int opCMPSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
writememb(es, DI, AL); if (abrt) return 1;
|
||||
writememb(es, DI, AL); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI--;
|
||||
else DI++;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -129,7 +129,7 @@ static int opSTOSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
writememb(es, EDI, AL); if (abrt) return 1;
|
||||
writememb(es, EDI, AL); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -138,7 +138,7 @@ static int opSTOSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
writememw(es, DI, AX); if (abrt) return 1;
|
||||
writememw(es, DI, AX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 2;
|
||||
else DI += 2;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -146,7 +146,7 @@ static int opSTOSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
writememw(es, EDI, AX); if (abrt) return 1;
|
||||
writememw(es, EDI, AX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 2;
|
||||
else EDI += 2;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -155,7 +155,7 @@ static int opSTOSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSTOSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
writememl(es, DI, EAX); if (abrt) return 1;
|
||||
writememl(es, DI, EAX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 4;
|
||||
else DI += 4;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -163,7 +163,7 @@ static int opSTOSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSTOSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
writememl(es, EDI, EAX); if (abrt) return 1;
|
||||
writememl(es, EDI, EAX); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 4;
|
||||
else EDI += 4;
|
||||
CLOCK_CYCLES(4);
|
||||
|
|
@ -173,7 +173,7 @@ static int opSTOSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
|
|
@ -182,7 +182,7 @@ static int opLODSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
|
|
@ -192,7 +192,7 @@ static int opLODSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
else SI += 2;
|
||||
|
|
@ -201,7 +201,7 @@ static int opLODSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
else ESI += 2;
|
||||
|
|
@ -211,7 +211,7 @@ static int opLODSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opLODSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) SI -= 4;
|
||||
else SI += 4;
|
||||
|
|
@ -220,7 +220,7 @@ static int opLODSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opLODSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
else ESI += 4;
|
||||
|
|
@ -231,7 +231,7 @@ static int opLODSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(es, DI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub8(AL, temp);
|
||||
if (flags & D_FLAG) DI--;
|
||||
else DI++;
|
||||
|
|
@ -240,7 +240,7 @@ static int opSCASB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(es, EDI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub8(AL, temp);
|
||||
if (flags & D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
|
|
@ -250,7 +250,7 @@ static int opSCASB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(es, DI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub16(AX, temp);
|
||||
if (flags & D_FLAG) DI -= 2;
|
||||
else DI += 2;
|
||||
|
|
@ -259,7 +259,7 @@ static int opSCASW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(es, EDI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub16(AX, temp);
|
||||
if (flags & D_FLAG) EDI -= 2;
|
||||
else EDI += 2;
|
||||
|
|
@ -269,7 +269,7 @@ static int opSCASW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opSCASL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(es, DI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
|
||||
setsub32(EAX, temp);
|
||||
if (flags & D_FLAG) DI -= 4;
|
||||
else DI += 4;
|
||||
|
|
@ -278,7 +278,7 @@ static int opSCASL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opSCASL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(es, EDI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
|
||||
setsub32(EAX, temp);
|
||||
if (flags & D_FLAG) EDI -= 4;
|
||||
else EDI += 4;
|
||||
|
|
@ -291,7 +291,7 @@ static int opINSB_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
check_io_perm(DX);
|
||||
temp = inb(DX);
|
||||
writememb(es, DI, temp); if (abrt) return 1;
|
||||
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI--;
|
||||
else DI++;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -302,7 +302,7 @@ static int opINSB_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
check_io_perm(DX);
|
||||
temp = inb(DX);
|
||||
writememb(es, EDI, temp); if (abrt) return 1;
|
||||
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -315,7 +315,7 @@ static int opINSW_a16(uint32_t fetchdat)
|
|||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
temp = inw(DX);
|
||||
writememw(es, DI, temp); if (abrt) return 1;
|
||||
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 2;
|
||||
else DI += 2;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -327,7 +327,7 @@ static int opINSW_a32(uint32_t fetchdat)
|
|||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
temp = inw(DX);
|
||||
writememw(es, EDI, temp); if (abrt) return 1;
|
||||
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 2;
|
||||
else EDI += 2;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -342,7 +342,7 @@ static int opINSL_a16(uint32_t fetchdat)
|
|||
check_io_perm(DX + 2);
|
||||
check_io_perm(DX + 3);
|
||||
temp = inl(DX);
|
||||
writememl(es, DI, temp); if (abrt) return 1;
|
||||
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) DI -= 4;
|
||||
else DI += 4;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -356,7 +356,7 @@ static int opINSL_a32(uint32_t fetchdat)
|
|||
check_io_perm(DX + 2);
|
||||
check_io_perm(DX + 3);
|
||||
temp = inl(DX);
|
||||
writememl(es, EDI, temp); if (abrt) return 1;
|
||||
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
|
||||
if (flags & D_FLAG) EDI -= 4;
|
||||
else EDI += 4;
|
||||
CLOCK_CYCLES(15);
|
||||
|
|
@ -365,7 +365,7 @@ static int opINSL_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
|
|
@ -375,7 +375,7 @@ static int opOUTSB_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
|
|
@ -386,7 +386,7 @@ static int opOUTSB_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
|
|
@ -397,7 +397,7 @@ static int opOUTSW_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
|
|
@ -409,7 +409,7 @@ static int opOUTSW_a32(uint32_t fetchdat)
|
|||
|
||||
static int opOUTSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
@ -422,7 +422,7 @@ static int opOUTSL_a16(uint32_t fetchdat)
|
|||
}
|
||||
static int opOUTSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@ static int opXCHG_b_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
@ -12,8 +12,8 @@ static int opXCHG_b_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (abrt) return 1;
|
||||
temp = geteab(); if (cpu_state.abrt) return 1;
|
||||
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
@ -23,8 +23,8 @@ static int opXCHG_w_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
@ -33,8 +33,8 @@ static int opXCHG_w_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
@ -44,8 +44,8 @@ static int opXCHG_l_a16(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
@ -54,8 +54,8 @@ static int opXCHG_l_a32(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
temp = geteal(); if (cpu_state.abrt) return 1;
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
|
|
|
|||
114
src/x86seg.c
114
src/x86seg.c
|
|
@ -116,7 +116,7 @@ void x86_doabrt(int x86_abrt)
|
|||
return;
|
||||
}
|
||||
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
|
||||
if (intgatesize == 16)
|
||||
{
|
||||
|
|
@ -150,25 +150,25 @@ void x86_doabrt(int x86_abrt)
|
|||
void x86gpf(char *s, uint16_t error)
|
||||
{
|
||||
// pclog("GPF %04X\n", error);
|
||||
abrt = ABRT_GPF;
|
||||
cpu_state.abrt = ABRT_GPF;
|
||||
abrt_error = error;
|
||||
}
|
||||
void x86ss(char *s, uint16_t error)
|
||||
{
|
||||
// pclog("SS %04X\n", error);
|
||||
abrt = ABRT_SS;
|
||||
cpu_state.abrt = ABRT_SS;
|
||||
abrt_error = error;
|
||||
}
|
||||
void x86ts(char *s, uint16_t error)
|
||||
{
|
||||
// pclog("TS %04X\n", error);
|
||||
abrt = ABRT_TS;
|
||||
cpu_state.abrt = ABRT_TS;
|
||||
abrt_error = error;
|
||||
}
|
||||
void x86np(char *s, uint16_t error)
|
||||
{
|
||||
// pclog("NP %04X : %s\n", error, s);
|
||||
abrt = ABRT_NP;
|
||||
cpu_state.abrt = ABRT_NP;
|
||||
abrt_error = error;
|
||||
}
|
||||
|
||||
|
|
@ -309,7 +309,7 @@ void loadseg(uint16_t seg, x86seg *s)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
dpl=(segdat[2]>>13)&3;
|
||||
if (s==&_ss)
|
||||
{
|
||||
|
|
@ -453,7 +453,7 @@ void loadcs(uint16_t seg)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
if (optype==JMP) pclog("Code seg - %04X - %04X %04X %04X %04X\n",seg,segdat[0],segdat[1],segdat[2],segdat[3]);
|
||||
// if (!(segdat[2]&0x8000)) x86abort("Code segment not present!\n");
|
||||
// if (output) pclog("Segdat2 %04X\n",segdat[2]);
|
||||
|
|
@ -573,7 +573,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
if (output) pclog("%04X %04X %04X %04X\n",segdat[0],segdat[1],segdat[2],segdat[3]);
|
||||
if (segdat[2]&0x1000) /*Normal code segment*/
|
||||
{
|
||||
|
|
@ -684,7 +684,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
|
||||
if (DPL > CPL)
|
||||
{
|
||||
|
|
@ -774,14 +774,14 @@ void PUSHW(uint16_t v)
|
|||
if (stack32)
|
||||
{
|
||||
writememw(ss,ESP-2,v);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
ESP-=2;
|
||||
}
|
||||
else
|
||||
{
|
||||
// pclog("Write %04X to %08X\n", v, ss+((SP-2)&0xFFFF));
|
||||
writememw(ss,((SP-2)&0xFFFF),v);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
SP-=2;
|
||||
}
|
||||
}
|
||||
|
|
@ -791,13 +791,13 @@ void PUSHL(uint32_t v)
|
|||
if (stack32)
|
||||
{
|
||||
writememl(ss,ESP-4,v);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
ESP-=4;
|
||||
}
|
||||
else
|
||||
{
|
||||
writememl(ss,((SP-4)&0xFFFF),v);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
SP-=4;
|
||||
}
|
||||
}
|
||||
|
|
@ -807,13 +807,13 @@ uint16_t POPW()
|
|||
if (stack32)
|
||||
{
|
||||
tempw=readmemw(ss,ESP);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
ESP+=2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tempw=readmemw(ss,SP);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
SP+=2;
|
||||
}
|
||||
return tempw;
|
||||
|
|
@ -824,13 +824,13 @@ uint32_t POPL()
|
|||
if (stack32)
|
||||
{
|
||||
templ=readmeml(ss,ESP);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
ESP+=4;
|
||||
}
|
||||
else
|
||||
{
|
||||
templ=readmeml(ss,SP);
|
||||
if (abrt) return 0;
|
||||
if (cpu_state.abrt) return 0;
|
||||
SP+=4;
|
||||
}
|
||||
return templ;
|
||||
|
|
@ -887,7 +887,7 @@ void loadcscall(uint16_t seg)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
type=segdat[2]&0xF00;
|
||||
if (type==0x400) newpc=segdat[0];
|
||||
else newpc=segdat[0]|(segdat[3]<<16);
|
||||
|
|
@ -1008,7 +1008,7 @@ void loadcscall(uint16_t seg)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
|
||||
if (output) pclog("Code seg2 call - %04X - %04X %04X %04X\n",seg2,segdat[0],segdat[1],segdat[2]);
|
||||
|
||||
|
|
@ -1048,7 +1048,7 @@ void loadcscall(uint16_t seg)
|
|||
newsp=readmemw(0,addr);
|
||||
}
|
||||
cpl_override=0;
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
if (output) pclog("New stack %04X:%08X\n",newss,newsp);
|
||||
if (!(newss&~3))
|
||||
{
|
||||
|
|
@ -1082,7 +1082,7 @@ void loadcscall(uint16_t seg)
|
|||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
if (output) pclog("Read stack seg done!\n");
|
||||
if (((newss & 3) != DPL) || (DPL2 != DPL))
|
||||
{
|
||||
|
|
@ -1139,7 +1139,7 @@ void loadcscall(uint16_t seg)
|
|||
{
|
||||
PUSHL(oldss);
|
||||
PUSHL(oldsp2);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
pclog("ABRT PUSHL\n");
|
||||
SS = oldss;
|
||||
|
|
@ -1153,7 +1153,7 @@ void loadcscall(uint16_t seg)
|
|||
{
|
||||
count--;
|
||||
PUSHL(readmeml(oldssbase,oldsp+(count*4)));
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
pclog("ABRT COPYL\n");
|
||||
SS = oldss;
|
||||
|
|
@ -1164,7 +1164,7 @@ void loadcscall(uint16_t seg)
|
|||
}
|
||||
// x86abort("Call gate with count %i\n",count);
|
||||
// PUSHL(oldcs);
|
||||
// PUSHL(oldpc); if (abrt) return;
|
||||
// PUSHL(oldpc); if (cpu_state.abrt) return;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1172,7 +1172,7 @@ void loadcscall(uint16_t seg)
|
|||
PUSHW(oldss);
|
||||
if (output) pclog("Write SS to %04X:%04X\n",SS,SP);
|
||||
PUSHW(oldsp2);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
pclog("ABRT PUSHW\n");
|
||||
SS = oldss;
|
||||
|
|
@ -1190,7 +1190,7 @@ void loadcscall(uint16_t seg)
|
|||
tempw=readmemw(oldssbase,(oldsp&0xFFFF)+(count*2));
|
||||
if (output) pclog("PUSH %04X\n",tempw);
|
||||
PUSHW(tempw);
|
||||
if (abrt)
|
||||
if (cpu_state.abrt)
|
||||
{
|
||||
pclog("ABRT COPYW\n");
|
||||
SS = oldss;
|
||||
|
|
@ -1202,7 +1202,7 @@ void loadcscall(uint16_t seg)
|
|||
// if (output) pclog("Stack %04X\n",SP);
|
||||
// if (count) x86abort("Call gate with count\n");
|
||||
// PUSHW(oldcs);
|
||||
// PUSHW(oldpc); if (abrt) return;
|
||||
// PUSHW(oldpc); if (cpu_state.abrt) return;
|
||||
}
|
||||
cycles -= timing_call_pm_gate_inner;
|
||||
break;
|
||||
|
|
@ -1217,12 +1217,12 @@ void loadcscall(uint16_t seg)
|
|||
/* if (type==0xC00)
|
||||
{
|
||||
PUSHL(oldcs);
|
||||
PUSHL(oldpc); if (abrt) return;
|
||||
PUSHL(oldpc); if (cpu_state.abrt) return;
|
||||
}
|
||||
else
|
||||
{
|
||||
PUSHW(oldcs);
|
||||
PUSHW(oldpc); if (abrt) return;
|
||||
PUSHW(oldpc); if (cpu_state.abrt) return;
|
||||
}*/
|
||||
CS=seg2;
|
||||
do_seg_load(&_cs, segdat);
|
||||
|
|
@ -1288,14 +1288,14 @@ void pmoderetf(int is32, uint16_t off)
|
|||
if (is32)
|
||||
{
|
||||
newpc=POPL();
|
||||
seg=POPL(); if (abrt) return;
|
||||
seg=POPL(); if (cpu_state.abrt) return;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (output) pclog("PC read from %04X:%04X\n",SS,SP);
|
||||
newpc=POPW();
|
||||
if (output) pclog("CS read from %04X:%04X\n",SS,SP);
|
||||
seg=POPW(); if (abrt) return;
|
||||
seg=POPW(); if (cpu_state.abrt) return;
|
||||
}
|
||||
if (output) pclog("Return to %04X:%08X\n",seg,newpc);
|
||||
if ((seg&3)<CPL)
|
||||
|
|
@ -1344,7 +1344,7 @@ void pmoderetf(int is32, uint16_t off)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) { ESP=oldsp; return; }
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP=oldsp; return; }
|
||||
oaddr = addr;
|
||||
|
||||
if (output) pclog("CPL %i RPL %i %i\n",CPL,seg&3,is32);
|
||||
|
|
@ -1447,7 +1447,7 @@ void pmoderetf(int is32, uint16_t off)
|
|||
if (is32)
|
||||
{
|
||||
newsp=POPL();
|
||||
newss=POPL(); if (abrt) return;
|
||||
newss=POPL(); if (cpu_state.abrt) return;
|
||||
// pclog("is32 new stack %04X:%04X\n",newss,newsp);
|
||||
}
|
||||
else
|
||||
|
|
@ -1455,7 +1455,7 @@ void pmoderetf(int is32, uint16_t off)
|
|||
if (output) pclog("SP read from %04X:%04X\n",SS,SP);
|
||||
newsp=POPW();
|
||||
if (output) pclog("SS read from %04X:%04X\n",SS,SP);
|
||||
newss=POPW(); if (abrt) return;
|
||||
newss=POPW(); if (cpu_state.abrt) return;
|
||||
// pclog("!is32 new stack %04X:%04X\n",newss,newsp);
|
||||
}
|
||||
if (output) pclog("Read new stack : %04X:%04X (%08X)\n", newss, newsp, ldt.base);
|
||||
|
|
@ -1493,7 +1493,7 @@ void pmoderetf(int is32, uint16_t off)
|
|||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) { ESP=oldsp; return; }
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP=oldsp; return; }
|
||||
if (output) pclog("Segment data %04X %04X %04X %04X\n", segdat2[0], segdat2[1], segdat2[2], segdat2[3]);
|
||||
// if (((newss & 3) != DPL) || (DPL2 != DPL))
|
||||
if ((newss & 3) != (seg & 3))
|
||||
|
|
@ -1622,7 +1622,7 @@ void pmodeint(int num, int soft)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(2,addr);
|
||||
segdat[2]=readmemw(4,addr);
|
||||
segdat[3]=readmemw(6,addr); cpl_override=0; if (abrt) { pclog("Abrt reading from %08X\n",addr); return; }
|
||||
segdat[3]=readmemw(6,addr); cpl_override=0; if (cpu_state.abrt) { pclog("Abrt reading from %08X\n",addr); return; }
|
||||
oaddr = addr;
|
||||
|
||||
if (output) pclog("Addr %08X seg %04X %04X %04X %04X\n",addr,segdat[0],segdat[1],segdat[2],segdat[3]);
|
||||
|
|
@ -1686,7 +1686,7 @@ void pmodeint(int num, int soft)
|
|||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
oaddr = addr;
|
||||
|
||||
if (DPL2 > CPL)
|
||||
|
|
@ -1762,7 +1762,7 @@ void pmodeint(int num, int soft)
|
|||
segdat3[0]=readmemw(0,addr);
|
||||
segdat3[1]=readmemw(0,addr+2);
|
||||
segdat3[2]=readmemw(0,addr+4);
|
||||
segdat3[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) return;
|
||||
segdat3[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
|
||||
if (((newss & 3) != DPL2) || (DPL3 != DPL2))
|
||||
{
|
||||
pclog("Int gate loading SS with wrong permissions\n");
|
||||
|
|
@ -1803,7 +1803,7 @@ void pmodeint(int num, int soft)
|
|||
PUSHL(GS);
|
||||
PUSHL(FS);
|
||||
PUSHL(DS);
|
||||
PUSHL(ES); if (abrt) return;
|
||||
PUSHL(ES); if (cpu_state.abrt) return;
|
||||
loadseg(0,&_ds);
|
||||
loadseg(0,&_es);
|
||||
loadseg(0,&_fs);
|
||||
|
|
@ -1815,7 +1815,7 @@ void pmodeint(int num, int soft)
|
|||
// if (soft) pclog("Pushl CS %08X\n", CS);
|
||||
PUSHL(CS);
|
||||
// if (soft) pclog("Pushl PC %08X\n", pc);
|
||||
PUSHL(cpu_state.pc); if (abrt) return;
|
||||
PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
|
||||
// if (output) pclog("32Stack %04X:%08X\n",SS,ESP);
|
||||
}
|
||||
else
|
||||
|
|
@ -1827,7 +1827,7 @@ void pmodeint(int num, int soft)
|
|||
// if (soft) pclog("Pushw CS %04X\n", CS);
|
||||
PUSHW(CS);
|
||||
// if (soft) pclog("Pushw pc %04X\n", pc);
|
||||
PUSHW(cpu_state.pc); if (abrt) return;
|
||||
PUSHW(cpu_state.pc); if (cpu_state.abrt) return;
|
||||
// if (output) pclog("16Stack %04X:%08X\n",SS,ESP);
|
||||
}
|
||||
cpl_override=0;
|
||||
|
|
@ -1862,7 +1862,7 @@ void pmodeint(int num, int soft)
|
|||
// if (soft) pclog("Pushlc CS %08X\n", CS);
|
||||
PUSHL(CS);
|
||||
// if (soft) pclog("Pushlc PC %08X\n", pc);
|
||||
PUSHL(cpu_state.pc); if (abrt) return;
|
||||
PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1870,7 +1870,7 @@ void pmodeint(int num, int soft)
|
|||
// if (soft) pclog("Pushwc CS %04X\n", CS);
|
||||
PUSHW(CS);
|
||||
// if (soft) pclog("Pushwc PC %04X\n", pc);
|
||||
PUSHW(cpu_state.pc); if (abrt) return;
|
||||
PUSHW(cpu_state.pc); if (cpu_state.abrt) return;
|
||||
}
|
||||
new_cpl = CS & 3;
|
||||
break;
|
||||
|
|
@ -1935,7 +1935,7 @@ void pmodeint(int num, int soft)
|
|||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6);
|
||||
cpl_override=0; if (abrt) return;
|
||||
cpl_override=0; if (cpu_state.abrt) return;
|
||||
if (!(segdat2[2]&0x8000))
|
||||
{
|
||||
pclog("Int task gate not present\n");
|
||||
|
|
@ -1980,13 +1980,13 @@ void pmodeiret(int is32)
|
|||
{
|
||||
newpc=POPL();
|
||||
seg=POPL();
|
||||
tempflags=POPL(); if (abrt) return;
|
||||
tempflags=POPL(); if (cpu_state.abrt) return;
|
||||
}
|
||||
else
|
||||
{
|
||||
newpc=POPW();
|
||||
seg=POPW();
|
||||
tempflags=POPW(); if (abrt) return;
|
||||
tempflags=POPW(); if (cpu_state.abrt) return;
|
||||
}
|
||||
cpu_state.pc=newpc;
|
||||
_cs.base=seg<<4;
|
||||
|
|
@ -2047,7 +2047,7 @@ void pmodeiret(int is32)
|
|||
// pclog("POP\n");
|
||||
newpc=POPL();
|
||||
seg=POPL();
|
||||
tempflags=POPL(); if (abrt) { ESP = oldsp; return; }
|
||||
tempflags=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
// if (output) pclog("IRETD pop %08X %08X %08X\n",newpc,seg,tempflags);
|
||||
if (is386 && ((tempflags>>16)&VM_FLAG))
|
||||
{
|
||||
|
|
@ -2058,7 +2058,7 @@ void pmodeiret(int is32)
|
|||
segs[0]=POPL();
|
||||
segs[1]=POPL();
|
||||
segs[2]=POPL();
|
||||
segs[3]=POPL(); if (abrt) { ESP = oldsp; return; }
|
||||
segs[3]=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
// pclog("Pop stack %04X:%04X\n",newss,newsp);
|
||||
eflags=tempflags>>16;
|
||||
loadseg(segs[0],&_es);
|
||||
|
|
@ -2101,7 +2101,7 @@ void pmodeiret(int is32)
|
|||
{
|
||||
newpc=POPW();
|
||||
seg=POPW();
|
||||
tempflags=POPW(); if (abrt) { ESP = oldsp; return; }
|
||||
tempflags=POPW(); if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
}
|
||||
// if (!is386) tempflags&=0xFFF;
|
||||
// pclog("Returned to %04X:%08X %04X %04X %i\n",seg,newpc,flags,tempflags, ins);
|
||||
|
|
@ -2150,7 +2150,7 @@ void pmodeiret(int is32)
|
|||
segdat[0]=readmemw(0,addr);
|
||||
segdat[1]=readmemw(0,addr+2);
|
||||
segdat[2]=readmemw(0,addr+4);
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) { ESP = oldsp; return; }
|
||||
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
// pclog("Seg type %04X %04X\n",segdat[2]&0x1F00,segdat[2]);
|
||||
|
||||
switch (segdat[2]&0x1F00)
|
||||
|
|
@ -2214,12 +2214,12 @@ void pmodeiret(int is32)
|
|||
if (is32)
|
||||
{
|
||||
newsp=POPL();
|
||||
newss=POPL(); if (abrt) { ESP = oldsp; return; }
|
||||
newss=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
}
|
||||
else
|
||||
{
|
||||
newsp=POPW();
|
||||
newss=POPW(); if (abrt) { ESP = oldsp; return; }
|
||||
newss=POPW(); if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
}
|
||||
|
||||
if (output) pclog("IRET load stack %04X:%04X\n",newss,newsp);
|
||||
|
|
@ -2258,7 +2258,7 @@ void pmodeiret(int is32)
|
|||
segdat2[0]=readmemw(0,addr);
|
||||
segdat2[1]=readmemw(0,addr+2);
|
||||
segdat2[2]=readmemw(0,addr+4);
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (abrt) { ESP = oldsp; return; }
|
||||
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP = oldsp; return; }
|
||||
// pclog("IRET SS sd2 %04X\n",segdat2[2]);
|
||||
// if (((newss & 3) != DPL) || (DPL2 != DPL))
|
||||
if ((newss & 3) != (seg & 3))
|
||||
|
|
@ -2378,12 +2378,12 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
|||
new_gs=readmemw(base,0x5C);
|
||||
new_ldt=readmemw(base,0x60);
|
||||
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
if (optype==JMP || optype==OPTYPE_INT)
|
||||
{
|
||||
if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
|
||||
else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
tempw&=~0x200;
|
||||
if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
|
||||
else writememw(gdt.base,(tr.seg&~7)+4,tempw);
|
||||
|
|
@ -2420,12 +2420,12 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
|
|||
writememl(base,0,tr.seg);
|
||||
new_flags|=NT_FLAG;
|
||||
}
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
if (optype==JMP || optype==OPTYPE_INT)
|
||||
{
|
||||
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
|
||||
else tempw=readmemw(gdt.base,(seg&~7)+4);
|
||||
if (abrt) return;
|
||||
if (cpu_state.abrt) return;
|
||||
tempw|=0x200;
|
||||
if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
|
||||
else writememw(gdt.base,(seg&~7)+4,tempw);
|
||||
|
|
|
|||
37
src/x87.c
37
src/x87.c
|
|
@ -20,13 +20,8 @@
|
|||
#include "386_common.h"
|
||||
|
||||
double ST[8];
|
||||
uint64_t ST_i64[8];
|
||||
MMX_REG MM[8];
|
||||
int ismmx;
|
||||
uint16_t npxs,npxc;
|
||||
uint8_t tag[8];
|
||||
|
||||
int TOP;
|
||||
|
||||
uint16_t x87_gettag()
|
||||
{
|
||||
|
|
@ -35,10 +30,10 @@ uint16_t x87_gettag()
|
|||
|
||||
for (c = 0; c < 8; c++)
|
||||
{
|
||||
if (tag[c] & TAG_UINT64)
|
||||
if (cpu_state.tag[c] & TAG_UINT64)
|
||||
ret |= 2 << (c*2);
|
||||
else
|
||||
ret |= (tag[c] << (c*2));
|
||||
ret |= (cpu_state.tag[c] << (c*2));
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -46,42 +41,42 @@ uint16_t x87_gettag()
|
|||
|
||||
void x87_settag(uint16_t new_tag)
|
||||
{
|
||||
tag[0] = new_tag & 3;
|
||||
tag[1] = (new_tag >> 2) & 3;
|
||||
tag[2] = (new_tag >> 4) & 3;
|
||||
tag[3] = (new_tag >> 6) & 3;
|
||||
tag[4] = (new_tag >> 8) & 3;
|
||||
tag[5] = (new_tag >> 10) & 3;
|
||||
tag[6] = (new_tag >> 12) & 3;
|
||||
tag[7] = (new_tag >> 14) & 3;
|
||||
cpu_state.tag[0] = new_tag & 3;
|
||||
cpu_state.tag[1] = (new_tag >> 2) & 3;
|
||||
cpu_state.tag[2] = (new_tag >> 4) & 3;
|
||||
cpu_state.tag[3] = (new_tag >> 6) & 3;
|
||||
cpu_state.tag[4] = (new_tag >> 8) & 3;
|
||||
cpu_state.tag[5] = (new_tag >> 10) & 3;
|
||||
cpu_state.tag[6] = (new_tag >> 12) & 3;
|
||||
cpu_state.tag[7] = (new_tag >> 14) & 3;
|
||||
}
|
||||
|
||||
void x87_dumpregs()
|
||||
{
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
pclog("MM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\n", MM[0].q, MM[1].q, MM[2].q, MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", MM[4].q, MM[5].q, MM[6].q, MM[7].q);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("ST(0)=%f\tST(1)=%f\tST(2)=%f\tST(3)=%f\t\n",ST[TOP],ST[(TOP+1)&7],ST[(TOP+2)&7],ST[(TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\t\n",ST[(TOP+4)&7],ST[(TOP+5)&7],ST[(TOP+6)&7],ST[(TOP+7)&7]);
|
||||
pclog("ST(0)=%f\tST(1)=%f\tST(2)=%f\tST(3)=%f\t\n",ST[cpu_state.TOP],ST[(cpu_state.TOP+1)&7],ST[(cpu_state.TOP+2)&7],ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\t\n",ST[(cpu_state.TOP+4)&7],ST[(cpu_state.TOP+5)&7],ST[(cpu_state.TOP+6)&7],ST[(cpu_state.TOP+7)&7]);
|
||||
}
|
||||
pclog("Status = %04X Control = %04X Tag = %04X\n",npxs,npxc,x87_gettag());
|
||||
}
|
||||
|
||||
void x87_print()
|
||||
{
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
pclog("\tMM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\t", MM[0].q, MM[1].q, MM[2].q, MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", MM[4].q, MM[5].q, MM[6].q, MM[7].q);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("\tST(0)=%.20f\tST(1)=%.20f\tST(2)=%f\tST(3)=%f\t",ST[TOP&7],ST[(TOP+1)&7],ST[(TOP+2)&7],ST[(TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\t TOP=%i CR=%04X SR=%04X TAG=%04X\n",ST[(TOP+4)&7],ST[(TOP+5)&7],ST[(TOP+6)&7],ST[(TOP+7)&7], TOP, npxc, npxs, x87_gettag());
|
||||
pclog("\tST(0)=%.20f\tST(1)=%.20f\tST(2)=%f\tST(3)=%f\t",ST[cpu_state.TOP&7],ST[(cpu_state.TOP+1)&7],ST[(cpu_state.TOP+2)&7],ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\tTOP=%i CR=%04X SR=%04X TAG=%04X\n",ST[(cpu_state.TOP+4)&7],ST[(cpu_state.TOP+5)&7],ST[(cpu_state.TOP+6)&7],ST[(cpu_state.TOP+7)&7], cpu_state.TOP, npxc, npxs, x87_gettag());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
uint32_t x87_pc_off,x87_op_off;
|
||||
uint16_t x87_pc_seg,x87_op_seg;
|
||||
extern int TOP;
|
||||
extern uint16_t npxs, npxc;
|
||||
extern uint8_t tag[8];
|
||||
extern int ismmx;
|
||||
extern double ST[8];
|
||||
extern uint64_t ST_i64[8];
|
||||
|
||||
typedef union MMX_REG
|
||||
{
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZERO};
|
||||
|
||||
#define ST(x) ST[((TOP+(x))&7)]
|
||||
#define ST(x) ST[((cpu_state.TOP+(x))&7)]
|
||||
|
||||
#define C0 (1<<8)
|
||||
#define C1 (1<<9)
|
||||
|
|
@ -34,15 +34,15 @@ static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZ
|
|||
|
||||
static inline void x87_set_mmx()
|
||||
{
|
||||
TOP = 0;
|
||||
*(uint64_t *)tag = 0;
|
||||
ismmx = 1;
|
||||
cpu_state.TOP = 0;
|
||||
*(uint64_t *)cpu_state.tag = 0;
|
||||
cpu_state.ismmx = 1;
|
||||
}
|
||||
|
||||
static inline void x87_emms()
|
||||
{
|
||||
*tag = 0x0303030303030303ll;
|
||||
ismmx = 0;
|
||||
*cpu_state.tag = 0x0303030303030303ll;
|
||||
cpu_state.ismmx = 0;
|
||||
}
|
||||
|
||||
static inline void x87_checkexceptions()
|
||||
|
|
@ -51,16 +51,16 @@ static inline void x87_checkexceptions()
|
|||
|
||||
static inline void x87_push(double i)
|
||||
{
|
||||
TOP=(TOP-1)&7;
|
||||
ST[TOP]=i;
|
||||
tag[TOP&7] = (i == 0.0) ? 1 : 0;
|
||||
cpu_state.TOP=(cpu_state.TOP-1)&7;
|
||||
ST[cpu_state.TOP]=i;
|
||||
cpu_state.tag[cpu_state.TOP&7] = (i == 0.0) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline double x87_pop()
|
||||
{
|
||||
double t=ST[TOP];
|
||||
tag[TOP&7] = 3;
|
||||
TOP=(TOP+1)&7;
|
||||
double t=ST[cpu_state.TOP];
|
||||
cpu_state.tag[cpu_state.TOP&7] = 3;
|
||||
cpu_state.TOP=(cpu_state.TOP+1)&7;
|
||||
return t;
|
||||
}
|
||||
|
||||
|
|
@ -163,12 +163,12 @@ static inline void x87_st80(double d)
|
|||
|
||||
static inline void x87_st_fsave(int reg)
|
||||
{
|
||||
reg = (TOP + reg) & 7;
|
||||
reg = (cpu_state.TOP + reg) & 7;
|
||||
|
||||
if (tag[reg] & TAG_UINT64)
|
||||
if (cpu_state.tag[reg] & TAG_UINT64)
|
||||
{
|
||||
writememl(easeg, cpu_state.eaaddr, ST_i64[reg] & 0xffffffff);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, ST_i64[reg] >> 32);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[reg].q & 0xffffffff);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, MM[reg].q >> 32);
|
||||
writememw(easeg, cpu_state.eaaddr + 8, 0x5555);
|
||||
}
|
||||
else
|
||||
|
|
@ -179,16 +179,16 @@ static inline void x87_ld_frstor(int reg)
|
|||
{
|
||||
uint16_t temp;
|
||||
|
||||
reg = (TOP + reg) & 7;
|
||||
reg = (cpu_state.TOP + reg) & 7;
|
||||
|
||||
temp = readmemw(easeg, cpu_state.eaaddr + 8);
|
||||
|
||||
if (temp == 0x5555 && tag[reg] == 2)
|
||||
if (temp == 0x5555 && cpu_state.tag[reg] == 2)
|
||||
{
|
||||
tag[reg] = TAG_UINT64;
|
||||
ST_i64[reg] = readmeml(easeg, cpu_state.eaaddr);
|
||||
ST_i64[reg] |= ((uint64_t)readmeml(easeg, cpu_state.eaaddr + 4) << 32);
|
||||
ST[reg] = (double)ST_i64[reg];
|
||||
cpu_state.tag[reg] = TAG_UINT64;
|
||||
MM[reg].q = readmeml(easeg, cpu_state.eaaddr);
|
||||
MM[reg].q |= ((uint64_t)readmeml(easeg, cpu_state.eaaddr + 4) << 32);
|
||||
ST[reg] = (double)MM[reg].q;
|
||||
}
|
||||
else
|
||||
ST[reg] = x87_ld80();
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
if ((npxc >> 10) & 3) \
|
||||
fesetround(rounding_modes[(npxc >> 10) & 3]); \
|
||||
ST(0) += use_var; \
|
||||
if ((npxc >> 10) & 3) \
|
||||
fesetround(FE_TONEAREST); \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(8); \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -19,7 +19,7 @@ static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
npxs &= ~(C0|C2|C3); \
|
||||
npxs |= x87_compare(ST(0), (double)use_var); \
|
||||
CLOCK_CYCLES(4); \
|
||||
|
|
@ -30,7 +30,7 @@ static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
npxs &= ~(C0|C2|C3); \
|
||||
npxs |= x87_compare(ST(0), (double)use_var); \
|
||||
x87_pop(); \
|
||||
|
|
@ -42,9 +42,9 @@ static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
x87_div(ST(0), ST(0), use_var); \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(73); \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -53,9 +53,9 @@ static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
x87_div(ST(0), use_var, ST(0)); \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(73); \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -64,9 +64,9 @@ static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) *= use_var; \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(11); \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -75,9 +75,9 @@ static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) -= use_var; \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(8); \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -86,9 +86,9 @@ static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat) \
|
|||
optype t; \
|
||||
FP_ENTER(); \
|
||||
fetch_ea_ ## a_size(fetchdat); \
|
||||
load_var = get(); if (abrt) return 1; \
|
||||
load_var = get(); if (cpu_state.abrt) return 1; \
|
||||
ST(0) = use_var - ST(0); \
|
||||
tag[TOP] &= ~TAG_UINT64; \
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64; \
|
||||
CLOCK_CYCLES(8); \
|
||||
return 0; \
|
||||
}
|
||||
|
|
@ -113,7 +113,7 @@ static int opFADD(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FADD\n");
|
||||
ST(0) = ST(0) + ST(fetchdat & 7);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -123,7 +123,7 @@ static int opFADDr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FADD\n");
|
||||
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -133,7 +133,7 @@ static int opFADDP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FADDP\n");
|
||||
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
|
|
@ -224,7 +224,7 @@ static int opFDIV(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIV\n");
|
||||
x87_div(ST(0), ST(0), ST(fetchdat & 7));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -234,7 +234,7 @@ static int opFDIVr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIV\n");
|
||||
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -244,7 +244,7 @@ static int opFDIVP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIVP\n");
|
||||
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
|
|
@ -256,7 +256,7 @@ static int opFDIVR(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIVR\n");
|
||||
x87_div(ST(0), ST(fetchdat&7), ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -266,7 +266,7 @@ static int opFDIVRr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIVR\n");
|
||||
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -276,7 +276,7 @@ static int opFDIVRP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDIVR\n");
|
||||
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(73);
|
||||
return 0;
|
||||
|
|
@ -288,7 +288,7 @@ static int opFMUL(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FMUL\n");
|
||||
ST(0) = ST(0) * ST(fetchdat & 7);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(16);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -298,7 +298,7 @@ static int opFMULr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FMUL\n");
|
||||
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(16);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -308,7 +308,7 @@ static int opFMULP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FMULP\n");
|
||||
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(16);
|
||||
return 0;
|
||||
|
|
@ -320,7 +320,7 @@ static int opFSUB(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUB\n");
|
||||
ST(0) = ST(0) - ST(fetchdat & 7);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -330,7 +330,7 @@ static int opFSUBr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUB\n");
|
||||
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -340,7 +340,7 @@ static int opFSUBP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUBP\n");
|
||||
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
|
|
@ -352,7 +352,7 @@ static int opFSUBR(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUBR\n");
|
||||
ST(0) = ST(fetchdat & 7) - ST(0);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -362,7 +362,7 @@ static int opFSUBRr(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUBR\n");
|
||||
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -372,7 +372,7 @@ static int opFSUBRP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSUBRP\n");
|
||||
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
|
||||
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ static int opFILDiw_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
x87_push((double)temp);
|
||||
CLOCK_CYCLES(13);
|
||||
|
|
@ -16,7 +16,7 @@ static int opFILDiw_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp = geteaw(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
x87_push((double)temp);
|
||||
CLOCK_CYCLES(13);
|
||||
|
|
@ -34,7 +34,7 @@ static int opFISTiw_a16(uint32_t fetchdat)
|
|||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
seteaw((int16_t)temp64);
|
||||
CLOCK_CYCLES(29);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFISTiw_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -47,7 +47,7 @@ static int opFISTiw_a32(uint32_t fetchdat)
|
|||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
seteaw((int16_t)temp64);
|
||||
CLOCK_CYCLES(29);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFISTPiw_a16(uint32_t fetchdat)
|
||||
|
|
@ -59,7 +59,7 @@ static int opFISTPiw_a16(uint32_t fetchdat)
|
|||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
seteaw((int16_t)temp64); if (abrt) return 1;
|
||||
seteaw((int16_t)temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(29);
|
||||
return 0;
|
||||
|
|
@ -73,7 +73,7 @@ static int opFISTPiw_a32(uint32_t fetchdat)
|
|||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
seteaw((int16_t)temp64); if (abrt) return 1;
|
||||
seteaw((int16_t)temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(29);
|
||||
return 0;
|
||||
|
|
@ -85,11 +85,11 @@ static int opFILDiq_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (abrt) return 1;
|
||||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
ST_i64[TOP] = temp64;
|
||||
tag[TOP] |= TAG_UINT64;
|
||||
MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
|
||||
|
||||
CLOCK_CYCLES(10);
|
||||
return 0;
|
||||
|
|
@ -100,11 +100,11 @@ static int opFILDiq_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (abrt) return 1;
|
||||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
ST_i64[TOP] = temp64;
|
||||
tag[TOP] |= TAG_UINT64;
|
||||
MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
|
||||
|
||||
CLOCK_CYCLES(10);
|
||||
return 0;
|
||||
|
|
@ -132,7 +132,7 @@ static int FBSTP_a16(uint32_t fetchdat)
|
|||
}
|
||||
tempc = (uint8_t)floor(fmod(tempd, 10.0));
|
||||
if (ST(0) < 0.0) tempc |= 0x80;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (abrt) return 1;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -158,7 +158,7 @@ static int FBSTP_a32(uint32_t fetchdat)
|
|||
}
|
||||
tempc = (uint8_t)floor(fmod(tempd, 10.0));
|
||||
if (ST(0) < 0.0) tempc |= 0x80;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (abrt) return 1;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -169,11 +169,11 @@ static int FISTPiq_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (tag[TOP] & TAG_UINT64)
|
||||
temp64 = ST_i64[TOP];
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = MM[cpu_state.TOP].q;
|
||||
else
|
||||
temp64 = x87_fround(ST(0));
|
||||
seteaq(temp64); if (abrt) return 1;
|
||||
seteaq(temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(29);
|
||||
return 0;
|
||||
|
|
@ -184,11 +184,11 @@ static int FISTPiq_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (tag[TOP] & TAG_UINT64)
|
||||
temp64 = ST_i64[TOP];
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = MM[cpu_state.TOP].q;
|
||||
else
|
||||
temp64 = x87_fround(ST(0));
|
||||
seteaq(temp64); if (abrt) return 1;
|
||||
seteaq(temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(29);
|
||||
return 0;
|
||||
|
|
@ -200,7 +200,7 @@ static int opFILDil_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
x87_push((double)templ);
|
||||
CLOCK_CYCLES(9);
|
||||
|
|
@ -212,7 +212,7 @@ static int opFILDil_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
templ = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
x87_push((double)templ);
|
||||
CLOCK_CYCLES(9);
|
||||
|
|
@ -230,7 +230,7 @@ static int opFISTil_a16(uint32_t fetchdat)
|
|||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
seteal((int32_t)temp64);
|
||||
CLOCK_CYCLES(28);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFISTil_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -243,7 +243,7 @@ static int opFISTil_a32(uint32_t fetchdat)
|
|||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
seteal((int32_t)temp64);
|
||||
CLOCK_CYCLES(28);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFISTPil_a16(uint32_t fetchdat)
|
||||
|
|
@ -255,7 +255,7 @@ static int opFISTPil_a16(uint32_t fetchdat)
|
|||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
seteal((int32_t)temp64); if (abrt) return 1;
|
||||
seteal((int32_t)temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(28);
|
||||
return 0;
|
||||
|
|
@ -269,7 +269,7 @@ static int opFISTPil_a32(uint32_t fetchdat)
|
|||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
seteal((int32_t)temp64); if (abrt) return 1;
|
||||
seteal((int32_t)temp64); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(28);
|
||||
return 0;
|
||||
|
|
@ -281,7 +281,7 @@ static int opFLDe_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (abrt) return 1;
|
||||
t=x87_ld80(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
x87_push(t);
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
@ -293,7 +293,7 @@ static int opFLDe_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (abrt) return 1;
|
||||
t=x87_ld80(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
x87_push(t);
|
||||
CLOCK_CYCLES(6);
|
||||
|
|
@ -305,7 +305,7 @@ static int opFSTPe_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (abrt) return 1;
|
||||
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
|
|
@ -315,7 +315,7 @@ static int opFSTPe_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (abrt) return 1;
|
||||
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
|
|
@ -327,7 +327,7 @@ static int opFLDd_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (abrt) return 1;
|
||||
t.i = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
x87_push(t.d);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -339,7 +339,7 @@ static int opFLDd_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (abrt) return 1;
|
||||
t.i = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
x87_push(t.d);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -355,7 +355,7 @@ static int opFSTd_a16(uint32_t fetchdat)
|
|||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
CLOCK_CYCLES(8);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTd_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -366,7 +366,7 @@ static int opFSTd_a32(uint32_t fetchdat)
|
|||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
CLOCK_CYCLES(8);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFSTPd_a16(uint32_t fetchdat)
|
||||
|
|
@ -377,7 +377,7 @@ static int opFSTPd_a16(uint32_t fetchdat)
|
|||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i); if (abrt) return 1;
|
||||
seteaq(t.i); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
|
|
@ -390,7 +390,7 @@ static int opFSTPd_a32(uint32_t fetchdat)
|
|||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i); if (abrt) return 1;
|
||||
seteaq(t.i); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(8);
|
||||
return 0;
|
||||
|
|
@ -402,7 +402,7 @@ static int opFLDs_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (abrt) return 1;
|
||||
ts.i = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
x87_push((double)ts.s);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -414,7 +414,7 @@ static int opFLDs_a32(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (abrt) return 1;
|
||||
ts.i = geteal(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
x87_push((double)ts.s);
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -430,7 +430,7 @@ static int opFSTs_a16(uint32_t fetchdat)
|
|||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
CLOCK_CYCLES(7);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTs_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -441,7 +441,7 @@ static int opFSTs_a32(uint32_t fetchdat)
|
|||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
CLOCK_CYCLES(7);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFSTPs_a16(uint32_t fetchdat)
|
||||
|
|
@ -451,7 +451,7 @@ static int opFSTPs_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (abrt) return 1;
|
||||
seteal(ts.i); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
@ -463,7 +463,7 @@ static int opFSTPs_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (abrt) return 1;
|
||||
seteal(ts.i); if (cpu_state.abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -33,8 +33,8 @@ static int opFINIT(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
npxc = 0x37F;
|
||||
npxs = 0;
|
||||
*(uint64_t *)tag = 0x0303030303030303ll;
|
||||
TOP = 0;
|
||||
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
|
||||
cpu_state.TOP = 0;
|
||||
CLOCK_CYCLES(17);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -45,7 +45,7 @@ static int opFFREE(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FFREE\n");
|
||||
tag[(TOP + fetchdat) & 7] = 3;
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = 3;
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -56,7 +56,7 @@ static int opFST(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FST\n");
|
||||
ST(fetchdat & 7) = ST(0);
|
||||
tag[(TOP + fetchdat) & 7] = tag[TOP & 7];
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -68,7 +68,7 @@ static int opFSTP(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSTP\n");
|
||||
ST(fetchdat & 7) = ST(0);
|
||||
tag[(TOP + fetchdat) & 7] = tag[TOP & 7];
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -87,7 +87,7 @@ static int FSTOR()
|
|||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+2);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
cpu_state.TOP = (npxs >> 11) & 7;
|
||||
cpu_state.eaaddr += 14;
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
|
|
@ -95,7 +95,7 @@ static int FSTOR()
|
|||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+4);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
cpu_state.TOP = (npxs >> 11) & 7;
|
||||
cpu_state.eaaddr += 28;
|
||||
break;
|
||||
}
|
||||
|
|
@ -108,38 +108,38 @@ static int FSTOR()
|
|||
x87_ldmmx(&MM[6]); x87_ld_frstor(6); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[7]); x87_ld_frstor(7);
|
||||
|
||||
ismmx = 0;
|
||||
cpu_state.ismmx = 0;
|
||||
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
|
||||
something like this is needed*/
|
||||
if (MM[0].w[4] == 0xffff && MM[1].w[4] == 0xffff && MM[2].w[4] == 0xffff && MM[3].w[4] == 0xffff &&
|
||||
MM[4].w[4] == 0xffff && MM[5].w[4] == 0xffff && MM[6].w[4] == 0xffff && MM[7].w[4] == 0xffff &&
|
||||
!TOP && !(*(uint64_t *)tag))
|
||||
ismmx = 1;
|
||||
!cpu_state.TOP && !(*(uint64_t *)cpu_state.tag))
|
||||
cpu_state.ismmx = 1;
|
||||
|
||||
CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
|
||||
if (fplog) pclog("FRSTOR %08X:%08X %i %i %04X\n", easeg, cpu_state.eaaddr, ismmx, TOP, x87_gettag());
|
||||
return abrt;
|
||||
if (fplog) pclog("FRSTOR %08X:%08X %i %i %04X\n", easeg, cpu_state.eaaddr, cpu_state.ismmx, cpu_state.TOP, x87_gettag());
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTOR_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FSTOR();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTOR_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FSTOR();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int FSAVE()
|
||||
{
|
||||
FP_ENTER();
|
||||
if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, cpu_state.eaaddr, ismmx);
|
||||
npxs = (npxs & ~(7 << 11)) | (TOP << 11);
|
||||
if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, cpu_state.eaaddr, cpu_state.ismmx);
|
||||
npxs = (npxs & ~(7 << 11)) | (cpu_state.TOP << 11);
|
||||
|
||||
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
|
||||
{
|
||||
|
|
@ -150,7 +150,7 @@ static int FSAVE()
|
|||
writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
cpu_state.eaaddr+=14;
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
|
|
@ -182,7 +182,7 @@ static int FSAVE()
|
|||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_op_seg);
|
||||
cpu_state.eaaddr+=14;
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
|
|
@ -213,7 +213,7 @@ static int FSAVE()
|
|||
writememw(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,(x87_op_off>>16)<<12);
|
||||
cpu_state.eaaddr+=28;
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
|
|
@ -245,7 +245,7 @@ static int FSAVE()
|
|||
writememl(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
|
||||
cpu_state.eaaddr+=28;
|
||||
if (ismmx)
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
|
|
@ -270,21 +270,21 @@ static int FSAVE()
|
|||
break;
|
||||
}
|
||||
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSAVE_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FSAVE();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSAVE_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FSAVE();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFSTSW_a16(uint32_t fetchdat)
|
||||
|
|
@ -292,18 +292,18 @@ static int opFSTSW_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((npxs & 0xC7FF) | (TOP << 11));
|
||||
seteaw((npxs & 0xC7FF) | (cpu_state.TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((npxs & 0xC7FF) | (TOP << 11));
|
||||
seteaw((npxs & 0xC7FF) | (cpu_state.TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -315,11 +315,11 @@ static int opFLD(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FLD %f\n", ST(fetchdat & 7));
|
||||
old_tag = tag[(TOP + fetchdat) & 7];
|
||||
old_i64 = ST_i64[(TOP + fetchdat) & 7];
|
||||
old_tag = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
|
||||
old_i64 = MM[(cpu_state.TOP + fetchdat) & 7].q;
|
||||
x87_push(ST(fetchdat&7));
|
||||
tag[TOP] = old_tag;
|
||||
ST_i64[TOP] = old_i64;
|
||||
cpu_state.tag[cpu_state.TOP] = old_tag;
|
||||
MM[cpu_state.TOP].q = old_i64;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -335,12 +335,12 @@ static int opFXCH(uint32_t fetchdat)
|
|||
td = ST(0);
|
||||
ST(0) = ST(fetchdat&7);
|
||||
ST(fetchdat&7) = td;
|
||||
old_tag = tag[TOP];
|
||||
tag[TOP] = tag[(TOP + fetchdat) & 7];
|
||||
tag[(TOP + fetchdat) & 7] = old_tag;
|
||||
old_i64 = ST_i64[TOP];
|
||||
ST_i64[TOP] = ST_i64[(TOP + fetchdat) & 7];
|
||||
ST_i64[(TOP + fetchdat) & 7] = old_i64;
|
||||
old_tag = cpu_state.tag[cpu_state.TOP];
|
||||
cpu_state.tag[cpu_state.TOP] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
|
||||
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = old_tag;
|
||||
old_i64 = MM[cpu_state.TOP].q;
|
||||
MM[cpu_state.TOP].q = MM[(cpu_state.TOP + fetchdat) & 7].q;
|
||||
MM[(cpu_state.TOP + fetchdat) & 7].q = old_i64;
|
||||
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
|
|
@ -352,7 +352,7 @@ static int opFCHS(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FCHS\n");
|
||||
ST(0) = -ST(0);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -363,7 +363,7 @@ static int opFABS(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FABS %f\n", ST(0));
|
||||
ST(0) = fabs(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -384,9 +384,9 @@ static int opFXAM(uint32_t fetchdat)
|
|||
{
|
||||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FXAM %i %f\n", tag[TOP&7], ST(0));
|
||||
if (fplog) pclog("FXAM %i %f\n", cpu_state.tag[cpu_state.TOP&7], ST(0));
|
||||
npxs &= ~(C0|C1|C2|C3);
|
||||
if (tag[TOP&7] == 3) npxs |= (C0|C3);
|
||||
if (cpu_state.tag[cpu_state.TOP&7] == 3) npxs |= (C0|C3);
|
||||
else if (ST(0) == 0.0) npxs |= C3;
|
||||
else npxs |= C2;
|
||||
if (ST(0) < 0.0) npxs |= C1;
|
||||
|
|
@ -460,7 +460,7 @@ static int opFLDZ(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FLDZ\n");
|
||||
x87_push(0.0);
|
||||
tag[TOP&7] = 1;
|
||||
cpu_state.tag[cpu_state.TOP&7] = 1;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -471,7 +471,7 @@ static int opF2XM1(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("F2XM1\n");
|
||||
ST(0) = pow(2.0, ST(0)) - 1.0;
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(200);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -482,7 +482,7 @@ static int opFYL2X(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FYL2X\n");
|
||||
ST(1) = ST(1) * (log(ST(0)) / log(2.0));
|
||||
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(250);
|
||||
return 0;
|
||||
|
|
@ -494,7 +494,7 @@ static int opFYL2XP1(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FYL2XP1\n");
|
||||
ST(1) = ST(1) * (log(ST(0)+1.0) / log(2.0));
|
||||
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(250);
|
||||
return 0;
|
||||
|
|
@ -506,7 +506,7 @@ static int opFPTAN(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FPTAN\n");
|
||||
ST(0) = tan(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
x87_push(1.0);
|
||||
npxs &= ~C2;
|
||||
CLOCK_CYCLES(235);
|
||||
|
|
@ -519,7 +519,7 @@ static int opFPATAN(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FPATAN\n");
|
||||
ST(1) = atan2(ST(1), ST(0));
|
||||
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
cpu_state.tag[(cpu_state.TOP + 1) & 7] &= ~TAG_UINT64;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(250);
|
||||
return 0;
|
||||
|
|
@ -530,7 +530,7 @@ static int opFDECSTP(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDECSTP\n");
|
||||
TOP = (TOP - 1) & 7;
|
||||
cpu_state.TOP = (cpu_state.TOP - 1) & 7;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -540,7 +540,7 @@ static int opFINCSTP(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FDECSTP\n");
|
||||
TOP = (TOP + 1) & 7;
|
||||
cpu_state.TOP = (cpu_state.TOP + 1) & 7;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -553,7 +553,7 @@ static int opFPREM(uint32_t fetchdat)
|
|||
if (fplog) pclog("FPREM %f %f ", ST(0), ST(1));
|
||||
temp64 = (int64_t)(ST(0) / ST(1));
|
||||
ST(0) = ST(0) - (ST(1) * (double)temp64);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
if (fplog) pclog("%f\n", ST(0));
|
||||
npxs &= ~(C0|C1|C2|C3);
|
||||
if (temp64 & 4) npxs|=C0;
|
||||
|
|
@ -570,7 +570,7 @@ static int opFPREM1(uint32_t fetchdat)
|
|||
if (fplog) pclog("FPREM1 %f %f ", ST(0), ST(1));
|
||||
temp64 = (int64_t)(ST(0) / ST(1));
|
||||
ST(0) = ST(0) - (ST(1) * (double)temp64);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
if (fplog) pclog("%f\n", ST(0));
|
||||
npxs &= ~(C0|C1|C2|C3);
|
||||
if (temp64 & 4) npxs|=C0;
|
||||
|
|
@ -586,7 +586,7 @@ static int opFSQRT(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSQRT\n");
|
||||
ST(0) = sqrt(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(83);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -599,7 +599,7 @@ static int opFSINCOS(uint32_t fetchdat)
|
|||
if (fplog) pclog("FSINCOS\n");
|
||||
td = ST(0);
|
||||
ST(0) = sin(td);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
x87_push(cos(td));
|
||||
npxs &= ~C2;
|
||||
CLOCK_CYCLES(330);
|
||||
|
|
@ -612,7 +612,7 @@ static int opFRNDINT(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FRNDINT %g ", ST(0));
|
||||
ST(0) = (double)x87_fround(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
if (fplog) pclog("%g\n", ST(0));
|
||||
CLOCK_CYCLES(21);
|
||||
return 0;
|
||||
|
|
@ -626,7 +626,7 @@ static int opFSCALE(uint32_t fetchdat)
|
|||
if (fplog) pclog("FSCALE\n");
|
||||
temp64 = (int64_t)ST(1);
|
||||
ST(0) = ST(0) * pow(2.0, (double)temp64);
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
CLOCK_CYCLES(30);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -637,7 +637,7 @@ static int opFSIN(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FSIN\n");
|
||||
ST(0) = sin(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
npxs &= ~C2;
|
||||
CLOCK_CYCLES(300);
|
||||
return 0;
|
||||
|
|
@ -649,7 +649,7 @@ static int opFCOS(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FCOS\n");
|
||||
ST(0) = cos(ST(0));
|
||||
tag[TOP] &= ~TAG_UINT64;
|
||||
cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
|
||||
npxs &= ~C2;
|
||||
CLOCK_CYCLES(300);
|
||||
return 0;
|
||||
|
|
@ -667,18 +667,18 @@ static int FLDENV()
|
|||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+2);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
cpu_state.TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+4);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
cpu_state.TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
}
|
||||
CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFLDENV_a16(uint32_t fetchdat)
|
||||
|
|
@ -686,14 +686,14 @@ static int opFLDENV_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FLDENV();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFLDENV_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FLDENV();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFLDCW_a16(uint32_t fetchdat)
|
||||
|
|
@ -703,7 +703,7 @@ static int opFLDCW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
npxc = tempw;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
|
|
@ -715,7 +715,7 @@ static int opFLDCW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
if (cpu_state.abrt) return 1;
|
||||
npxc = tempw;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
|
|
@ -762,7 +762,7 @@ static int FSTENV()
|
|||
break;
|
||||
}
|
||||
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFSTENV_a16(uint32_t fetchdat)
|
||||
|
|
@ -770,14 +770,14 @@ static int opFSTENV_a16(uint32_t fetchdat)
|
|||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
FSTENV();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTENV_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
FSTENV();
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
static int opFSTCW_a16(uint32_t fetchdat)
|
||||
|
|
@ -787,7 +787,7 @@ static int opFSTCW_a16(uint32_t fetchdat)
|
|||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
static int opFSTCW_a32(uint32_t fetchdat)
|
||||
{
|
||||
|
|
@ -796,7 +796,7 @@ static int opFSTCW_a32(uint32_t fetchdat)
|
|||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
#define opFCMOV(condition) \
|
||||
|
|
@ -807,8 +807,8 @@ static int opFSTCW_a32(uint32_t fetchdat)
|
|||
if (fplog) pclog("FCMOV %f\n", ST(fetchdat & 7)); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
tag[TOP] = tag[(TOP + fetchdat) & 7]; \
|
||||
ST_i64[TOP] = ST_i64[(TOP + fetchdat) & 7]; \
|
||||
cpu_state.tag[cpu_state.TOP] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7]; \
|
||||
MM[cpu_state.TOP].q = MM[(cpu_state.TOP + fetchdat) & 7].q; \
|
||||
ST(0) = ST(fetchdat & 7); \
|
||||
} \
|
||||
CLOCK_CYCLES(4); \
|
||||
|
|
|
|||
Loading…
Reference in a new issue