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Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.

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This commit is contained in:
SarahW 2016-11-25 21:32:02 +00:00
commit 1b73963997
33 changed files with 1139 additions and 261 deletions
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135
src/386_dynarec.c
View file

@ -274,6 +274,89 @@ void x86illegal()
x86_int(6);
}
/*Prefetch emulation is a fairly simplistic model:
- All instruction bytes must be fetched before it starts.
- Cycles used for non-instruction memory accesses are counted and subtracted
from the total cycles taken
- Any remaining cycles are used to refill the prefetch queue.
Note that this is only used for 286 / 386 systems. It is disabled when the
internal cache on 486+ CPUs is enabled.
*/
static int prefetch_bytes = 0;
static int prefetch_prefixes = 0;
static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int reads_l, int writes, int writes_l, int ea32)
{
int mem_cycles = reads*cpu_cycles_read + reads_l*cpu_cycles_read_l + writes*cpu_cycles_write + writes_l*cpu_cycles_write_l;
if (instr_cycles < mem_cycles)
instr_cycles = mem_cycles;
prefetch_bytes -= prefetch_prefixes;
prefetch_bytes -= bytes;
if (modrm != -1)
{
if (ea32)
{
if ((modrm & 7) == 4)
{
if ((modrm & 0x700) == 0x500)
prefetch_bytes -= 5;
else if ((modrm & 0xc0) == 0x40)
prefetch_bytes -= 2;
else if ((modrm & 0xc0) == 0x80)
prefetch_bytes -= 5;
}
else
{
if ((modrm & 0xc7) == 0x05)
prefetch_bytes -= 4;
else if ((modrm & 0xc0) == 0x40)
prefetch_bytes--;
else if ((modrm & 0xc0) == 0x80)
prefetch_bytes -= 4;
}
}
else
{
if ((modrm & 0xc7) == 0x06)
prefetch_bytes -= 2;
else if ((modrm & 0xc0) != 0xc0)
prefetch_bytes -= ((modrm & 0xc0) >> 6);
}
}
/* Fill up prefetch queue */
while (prefetch_bytes < 0)
{
prefetch_bytes += cpu_prefetch_width;
cycles -= cpu_prefetch_cycles;
}
/* Subtract cycles used for memory access by instruction */
instr_cycles -= mem_cycles;
while (instr_cycles >= cpu_prefetch_cycles)
{
prefetch_bytes += cpu_prefetch_width;
instr_cycles -= cpu_prefetch_cycles;
}
prefetch_prefixes = 0;
}
static void prefetch_flush()
{
prefetch_bytes = 0;
}
#define PREFETCH_RUN(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32) \
do { if (cpu_prefetch_cycles) prefetch_run(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32); } while (0)
#define PREFETCH_PREFIX() prefetch_prefixes++
#define PREFETCH_FLUSH() prefetch_flush()
int rep386(int fv)
{
@ -291,6 +374,7 @@ int rep386(int fv)
that high frequency timers still work okay. This amount is different
for interpreter and recompiler*/
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100);
int reads = 0, reads_l = 0, writes = 0, writes_l = 0, total_cycles = 0;
if (trap)
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
@ -319,28 +403,36 @@ int rep386(int fv)
break;
case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
cpu_state.ea_seg = &_es;
PREFETCH_PREFIX();
goto startrep;
break;
case 0x2E: case 0x12E: case 0x22E: case 0x32E: /*CS:*/
cpu_state.ea_seg = &_cs;
PREFETCH_PREFIX();
goto startrep;
case 0x36: case 0x136: case 0x236: case 0x336: /*SS:*/
cpu_state.ea_seg = &_ss;
PREFETCH_PREFIX();
goto startrep;
case 0x3E: case 0x13E: case 0x23E: case 0x33E: /*DS:*/
cpu_state.ea_seg = &_ds;
PREFETCH_PREFIX();
goto startrep;
case 0x64: case 0x164: case 0x264: case 0x364: /*FS:*/
cpu_state.ea_seg = &_fs;
PREFETCH_PREFIX();
goto startrep;
case 0x65: case 0x165: case 0x265: case 0x365: /*GS:*/
cpu_state.ea_seg = &_gs;
PREFETCH_PREFIX();
goto startrep;
case 0x66: case 0x166: case 0x266: case 0x366: /*Data size prefix*/
rep32 = (rep32 & 0x200) | ((use32 ^ 0x100) & 0x100);
PREFETCH_PREFIX();
goto startrep;
case 0x67: case 0x167: case 0x267: case 0x367: /*Address size prefix*/
rep32 = (rep32 & 0x100) | ((use32 ^ 0x200) & 0x200);
PREFETCH_PREFIX();
goto startrep;
case 0x6C: case 0x16C: /*REP INSB*/
// cpu_notreps++;
@ -354,6 +446,7 @@ int rep386(int fv)
else DI++;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -370,6 +463,7 @@ int rep386(int fv)
else EDI++;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -386,6 +480,7 @@ int rep386(int fv)
else DI+=2;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -401,6 +496,7 @@ int rep386(int fv)
else DI+=4;
c--;
cycles-=15;
reads_l++; writes_l++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -416,6 +512,7 @@ int rep386(int fv)
else EDI+=2;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -431,6 +528,7 @@ int rep386(int fv)
else EDI+=4;
c--;
cycles-=15;
reads_l++; writes_l++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -447,6 +545,7 @@ int rep386(int fv)
else SI++;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -463,6 +562,7 @@ int rep386(int fv)
else ESI++;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -479,6 +579,7 @@ int rep386(int fv)
else SI+=2;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -494,6 +595,7 @@ int rep386(int fv)
else SI += 4;
c--;
cycles -= 14;
reads_l++; writes_l++; total_cycles += 14;
}
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
@ -509,6 +611,7 @@ int rep386(int fv)
else ESI+=2;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -524,6 +627,7 @@ int rep386(int fv)
else ESI += 4;
c--;
cycles -= 14;
reads_l++; writes_l++; total_cycles += 14;
}
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
@ -544,6 +648,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -562,6 +667,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -580,6 +686,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -599,6 +706,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -618,6 +726,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -638,6 +747,7 @@ int rep386(int fv)
c--;
cycles-=(is486)?3:4;
ins++;
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
@ -657,6 +767,7 @@ int rep386(int fv)
else { DI++; SI++; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -675,6 +786,7 @@ int rep386(int fv)
else { EDI++; ESI++; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -696,6 +808,7 @@ int rep386(int fv)
else { DI+=2; SI+=2; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -714,6 +827,7 @@ int rep386(int fv)
else { DI+=4; SI+=4; }
c--;
cycles-=(is486)?7:9;
reads_l += 2; total_cycles += is486 ? 7 : 9;
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -732,6 +846,7 @@ int rep386(int fv)
else { EDI+=2; ESI+=2; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -750,6 +865,7 @@ int rep386(int fv)
else { EDI+=4; ESI+=4; }
c--;
cycles-=(is486)?7:9;
reads_l += 2; total_cycles += is486 ? 7 : 9;
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
@ -767,6 +883,7 @@ int rep386(int fv)
else DI++;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -785,6 +902,7 @@ int rep386(int fv)
else EDI++;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -803,6 +921,7 @@ int rep386(int fv)
else DI+=2;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -821,6 +940,7 @@ int rep386(int fv)
else EDI+=2;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -839,6 +959,7 @@ int rep386(int fv)
else DI+=4;
c--;
cycles-=(is486)?4:5;
writes_l++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -857,6 +978,7 @@ int rep386(int fv)
else EDI+=4;
c--;
cycles-=(is486)?4:5;
writes_l++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
@ -876,6 +998,7 @@ int rep386(int fv)
else SI++;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -891,6 +1014,7 @@ int rep386(int fv)
else ESI++;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -906,6 +1030,7 @@ int rep386(int fv)
else SI+=2;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -921,6 +1046,7 @@ int rep386(int fv)
else SI+=4;
c--;
cycles-=5;
reads_l++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -936,6 +1062,7 @@ int rep386(int fv)
else ESI+=2;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -951,6 +1078,7 @@ int rep386(int fv)
else ESI+=4;
c--;
cycles-=5;
reads_l++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
@ -970,6 +1098,7 @@ int rep386(int fv)
else DI++;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -994,6 +1123,7 @@ int rep386(int fv)
else EDI++;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -1016,6 +1146,7 @@ int rep386(int fv)
else DI+=2;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -1038,6 +1169,7 @@ int rep386(int fv)
else DI+=4;
c--;
cycles-=(is486)?5:8;
reads_l++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -1060,6 +1192,7 @@ int rep386(int fv)
else EDI+=2;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -1082,6 +1215,7 @@ int rep386(int fv)
else EDI+=4;
c--;
cycles-=(is486)?5:8;
reads_l++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
@ -1100,6 +1234,7 @@ int rep386(int fv)
if (rep32&0x200) ECX=c;
else CX=c;
CPU_BLOCK_END();
PREFETCH_RUN(total_cycles, 1, -1, reads, reads_l, writes, writes_l, 0);
return cpu_state.abrt;
//pclog("rep cpu_block_end=%d %p\n", cpu_block_end, (void *)&cpu_block_end);
// if (output) pclog("%03X %03X\n",rep32,use32);

3
src/386_dynarec_ops.c
View file

@ -49,6 +49,9 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
#define fetch_ea_32(rmdat) cpu_state.pc++; if (cpu_mod != 3) fetch_ea_32_long(rmdat);
#define PREFETCH_RUN(instr_cycles, bytes, modrm, reads, read_ls, writes, write_ls, ea32)
#define PREFETCH_PREFIX()
#define PREFETCH_FLUSH()
#define OP_TABLE(name) dynarec_ops_ ## name
#define CLOCK_CYCLES(c)

6
src/386_ops.h
View file

@ -153,13 +153,15 @@ static int op0F_w_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_opcodes_0f[opcode](fetchdat >> 8);
}
static int op0F_l_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_opcodes_0f[opcode | 0x100](fetchdat >> 8);
}
@ -167,6 +169,7 @@ static int op0F_w_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_opcodes_0f[opcode | 0x200](fetchdat >> 8);
}
@ -174,6 +177,7 @@ static int op0F_l_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_opcodes_0f[opcode | 0x300](fetchdat >> 8);
}

2
src/808x.c
View file

@ -635,6 +635,8 @@ void resetx86()
cr0 = 1 << 30;
else
cr0 = 0;
cpu_cache_int_enabled = 0;
cpu_update_waitstates();
cr4 = 0;
eflags=0;
cgate32=0;

391
src/cpu.c
View file

@ -71,6 +71,11 @@ int cpu_use_dynarec;
uint64_t cpu_CR4_mask;
int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
int cpu_prefetch_cycles, cpu_prefetch_width;
int cpu_waitstates;
int cpu_cache_int_enabled, cpu_cache_ext_enabled;
int is386;
uint64_t tsc = 0;
@ -118,209 +123,209 @@ static struct
CPU cpus_8088[] =
{
/*8088 standard*/
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0},
{"8088/7.16", CPU_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0},
{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0, 0, 0},
{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0, 0, 0},
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8088/7.16", CPU_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_pcjr[] =
{
/*8088 PCjr*/
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0},
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_8086[] =
{
/*8086 standard*/
{"8086/7.16", CPU_8086, 1, 14318184/2, 1, 0, 0, 0, 0, 0},
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"8086/9.54", CPU_8086, 1, 4772728*2, 1, 0, 0, 0, 0, 0},
{"8086/10", CPU_8086, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"8086/12", CPU_8086, 3, 12000000, 1, 0, 0, 0, 0, 0},
{"8086/16", CPU_8086, 4, 16000000, 1, 0, 0, 0, 0, 0},
{"8086/7.16", CPU_8086, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8086/9.54", CPU_8086, 1, 4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8086/10", CPU_8086, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8086/12", CPU_8086, 3, 12000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"8086/16", CPU_8086, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_pc1512[] =
{
/*8086 Amstrad*/
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_286[] =
{
/*286*/
{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0, 0},
{"286/8", CPU_286, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"286/12", CPU_286, 3, 12000000, 1, 0, 0, 0, 0, 0},
{"286/16", CPU_286, 4, 16000000, 1, 0, 0, 0, 0, 0},
{"286/20", CPU_286, 5, 20000000, 1, 0, 0, 0, 0, 0},
{"286/25", CPU_286, 6, 25000000, 1, 0, 0, 0, 0, 0},
{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0, 0, 2,2,2,2},
{"286/8", CPU_286, 1, 8000000, 1, 0, 0, 0, 0, 0, 2,2,2,2},
{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2},
{"286/12", CPU_286, 3, 12000000, 1, 0, 0, 0, 0, 0, 3,3,3,3},
{"286/16", CPU_286, 4, 16000000, 1, 0, 0, 0, 0, 0, 3,3,3,3},
{"286/20", CPU_286, 5, 20000000, 1, 0, 0, 0, 0, 0, 4,4,4,4},
{"286/25", CPU_286, 6, 25000000, 1, 0, 0, 0, 0, 0, 4,4,4,4},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_ibmat[] =
{
/*286*/
{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0, 0},
{"286/8", CPU_286, 0, 8000000, 1, 0, 0, 0, 0, 0},
{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0, 0, 3,3,3,3},
{"286/8", CPU_286, 0, 8000000, 1, 0, 0, 0, 0, 0, 3,3,3,3},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_ps1_m2011[] =
{
/*286*/
{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0, 0, 0, 2,2,2,2},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_i386[] =
{
/*i386*/
{"i386SX/16", CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0},
{"i386SX/20", CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0},
{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0},
{"i386SX/33", CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0},
{"i386DX/16", CPU_386DX, 0, 16000000, 1, 0, 0x0308, 0, 0, 0},
{"i386DX/20", CPU_386DX, 1, 20000000, 1, 0, 0x0308, 0, 0, 0},
{"i386DX/25", CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0},
{"i386DX/33", CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0},
{"i386SX/16", CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3},
{"i386SX/20", CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3},
{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3},
{"i386SX/33", CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3},
{"i386DX/16", CPU_386DX, 0, 16000000, 1, 0, 0x0308, 0, 0, 0, 3,3,3,3},
{"i386DX/20", CPU_386DX, 1, 20000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3},
{"i386DX/25", CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3},
{"i386DX/33", CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3},
{"", -1, 0, 0, 0}
};
CPU cpus_acer[] =
{
/*i386*/
{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0},
{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,4,4},
{"", -1, 0, 0, 0}
};
CPU cpus_Am386[] =
{
/*Am386*/
{"Am386SX/16", CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0},
{"Am386SX/20", CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0},
{"Am386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0},
{"Am386SX/33", CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0},
{"Am386SX/40", CPU_386SX, 4, 40000000, 1, 0, 0x2308, 0, 0, 0},
{"Am386DX/25", CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0},
{"Am386DX/33", CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0},
{"Am386DX/40", CPU_386DX, 4, 40000000, 1, 0, 0x0308, 0, 0, 0},
{"Am386SX/16", CPU_386SX, 0, 16000000, 1, 0, 0x2308, 0, 0, 0, 3,3,3,3},
{"Am386SX/20", CPU_386SX, 1, 20000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3},
{"Am386SX/25", CPU_386SX, 2, 25000000, 1, 0, 0x2308, 0, 0, 0, 4,4,3,3},
{"Am386SX/33", CPU_386SX, 3, 33333333, 1, 0, 0x2308, 0, 0, 0, 6,6,3,3},
{"Am386SX/40", CPU_386SX, 4, 40000000, 1, 0, 0x2308, 0, 0, 0, 7,7,3,3},
{"Am386DX/25", CPU_386DX, 2, 25000000, 1, 0, 0x0308, 0, 0, 0, 4,4,3,3},
{"Am386DX/33", CPU_386DX, 3, 33333333, 1, 0, 0x0308, 0, 0, 0, 6,6,3,3},
{"Am386DX/40", CPU_386DX, 4, 40000000, 1, 0, 0x0308, 0, 0, 0, 7,7,3,3},
{"", -1, 0, 0, 0}
};
CPU cpus_486SDLC[] =
{
/*Cx486SLC/DLC*/
{"Cx486SLC/20", CPU_486SLC, 1, 20000000, 1, 0, 0, 0, 0x0000, 0},
{"Cx486SLC/25", CPU_486SLC, 2, 25000000, 1, 0, 0, 0, 0x0000, 0},
{"Cx486SLC/33", CPU_486SLC, 3, 33333333, 1, 0, 0, 0, 0x0000, 0},
{"Cx486SRx2/32", CPU_486SLC, 3, 32000000, 2, 0, 0, 0, 0x0006, 0},
{"Cx486SRx2/40", CPU_486SLC, 4, 40000000, 2, 0, 0, 0, 0x0006, 0},
{"Cx486SRx2/50", CPU_486SLC, 5, 50000000, 2, 0, 0, 0, 0x0006, 0},
{"Cx486DLC/25", CPU_486DLC, 2, 25000000, 1, 0, 0, 0, 0x0001, 0},
{"Cx486DLC/33", CPU_486DLC, 3, 33333333, 1, 0, 0, 0, 0x0001, 0},
{"Cx486DLC/40", CPU_486DLC, 4, 40000000, 1, 0, 0, 0, 0x0001, 0},
{"Cx486DRx2/32", CPU_486DLC, 3, 32000000, 2, 0, 0, 0, 0x0007, 0},
{"Cx486DRx2/40", CPU_486DLC, 4, 40000000, 2, 0, 0, 0, 0x0007, 0},
{"Cx486DRx2/50", CPU_486DLC, 5, 50000000, 2, 0, 0, 0, 0x0007, 0},
{"Cx486DRx2/66", CPU_486DLC, 6, 66666666, 2, 0, 0, 0, 0x0007, 0},
{"Cx486SLC/20", CPU_486SLC, 1, 20000000, 1, 0, 0, 0, 0x0000, 0, 4,4,3,3},
{"Cx486SLC/25", CPU_486SLC, 2, 25000000, 1, 0, 0, 0, 0x0000, 0, 4,4,3,3},
{"Cx486SLC/33", CPU_486SLC, 3, 33333333, 1, 0, 0, 0, 0x0000, 0, 6,6,3,3},
{"Cx486SRx2/32", CPU_486SLC, 3, 32000000, 2, 0, 0, 0, 0x0006, 0, 6,6,6,6},
{"Cx486SRx2/40", CPU_486SLC, 4, 40000000, 2, 0, 0, 0, 0x0006, 0, 8,8,6,6},
{"Cx486SRx2/50", CPU_486SLC, 5, 50000000, 2, 0, 0, 0, 0x0006, 0, 8,8,6,6},
{"Cx486DLC/25", CPU_486DLC, 2, 25000000, 1, 0, 0, 0, 0x0001, 0, 4,4,3,3},
{"Cx486DLC/33", CPU_486DLC, 3, 33333333, 1, 0, 0, 0, 0x0001, 0, 6,6,3,3},
{"Cx486DLC/40", CPU_486DLC, 4, 40000000, 1, 0, 0, 0, 0x0001, 0, 7,7,3,3},
{"Cx486DRx2/32", CPU_486DLC, 3, 32000000, 2, 0, 0, 0, 0x0007, 0, 6,6,6,6},
{"Cx486DRx2/40", CPU_486DLC, 4, 40000000, 2, 0, 0, 0, 0x0007, 0, 8,8,6,6},
{"Cx486DRx2/50", CPU_486DLC, 5, 50000000, 2, 0, 0, 0, 0x0007, 0, 8,8,6,6},
{"Cx486DRx2/66", CPU_486DLC, 6, 66666666, 2, 0, 0, 0, 0x0007, 0, 12,12,6,6},
{"", -1, 0, 0, 0}
};
CPU cpus_i486[] =
{
/*i486*/
{"i486SX/16", CPU_i486SX, 0, 16000000, 1, 16000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486SX/20", CPU_i486SX, 1, 20000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486SX/25", CPU_i486SX, 2, 25000000, 1, 25000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486SX/33", CPU_i486SX, 3, 33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486SX2/50", CPU_i486SX, 5, 50000000, 2, 25000000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX/25", CPU_i486DX, 2, 25000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX/33", CPU_i486DX, 3, 33333333, 1, 33333333, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX/50", CPU_i486DX, 5, 50000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX2/40", CPU_i486DX, 4, 40000000, 2, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX2/50", CPU_i486DX, 5, 50000000, 2, 25000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
{"i486DX2/66", CPU_i486DX, 6, 66666666, 2, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
{"iDX4/75", CPU_i486DX, 7, 75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_i486DX,10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"Pentium OverDrive/63", CPU_PENTIUM, 6, 62500000, 3, 25000000, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive/83", CPU_PENTIUM, 8, 83333333, 3, 33333333, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"i486SX/16", CPU_i486SX, 0, 16000000, 1, 16000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3,3,3,3},
{"i486SX/20", CPU_i486SX, 1, 20000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3},
{"i486SX/25", CPU_i486SX, 2, 25000000, 1, 25000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3},
{"i486SX/33", CPU_i486SX, 3, 33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"i486SX2/50", CPU_i486SX, 5, 50000000, 2, 25000000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"i486DX/25", CPU_i486DX, 2, 25000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3},
{"i486DX/33", CPU_i486DX, 3, 33333333, 1, 33333333, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"i486DX/50", CPU_i486DX, 5, 50000000, 1, 25000000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4},
{"i486DX2/40", CPU_i486DX, 4, 40000000, 2, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"i486DX2/50", CPU_i486DX, 5, 50000000, 2, 25000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"i486DX2/66", CPU_i486DX, 6, 66666666, 2, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"iDX4/75", CPU_i486DX, 7, 75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_i486DX,10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"Pentium OverDrive/63", CPU_PENTIUM, 6, 62500000, 3, 25000000, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7},
{"Pentium OverDrive/83", CPU_PENTIUM, 8, 83333333, 3, 33333333, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8},
{"", -1, 0, 0, 0}
};
CPU cpus_Am486[] =
{
/*Am486/5x86*/
{"Am486SX/33", CPU_Am486SX, 3, 33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"Am486SX/40", CPU_Am486SX, 4, 40000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
{"Am486SX2/50", CPU_Am486SX, 5, 50000000, 2, 25000000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"Am486SX2/66", CPU_Am486SX, 6, 66666666, 2, 33333333, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
{"Am486DX/33", CPU_Am486DX, 3, 33333333, 1, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX/40", CPU_Am486DX, 4, 40000000, 1, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX2/50", CPU_Am486DX, 5, 50000000, 2, 25000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX2/66", CPU_Am486DX, 6, 66666666, 2, 33333333, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX2/80", CPU_Am486DX, 8, 80000000, 2, 20000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX4/75", CPU_Am486DX, 7, 75000000, 3, 25000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX4/90", CPU_Am486DX, 9, 90000000, 3, 30000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX4/100", CPU_Am486DX, 10, 100000000, 3, 33333333, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
{"Am486DX4/120", CPU_Am486DX, 11, 120000000, 3, 20000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
{"Am5x86/P75", CPU_Am486DX, 12, 133333333, 4, 33333333, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC},
{"Am5x86/P75+", CPU_Am486DX, 13, 160000000, 4, 20000000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC},
{"Am486SX/33", CPU_Am486SX, 3, 33333333, 1, 33333333, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"Am486SX/40", CPU_Am486SX, 4, 40000000, 1, 20000000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3},
{"Am486SX2/50", CPU_Am486SX, 5, 50000000, 2, 25000000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"Am486SX2/66", CPU_Am486SX, 6, 66666666, 2, 33333333, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
{"Am486DX/33", CPU_Am486DX, 3, 33333333, 1, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"Am486DX/40", CPU_Am486DX, 4, 40000000, 1, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3},
{"Am486DX2/50", CPU_Am486DX, 5, 50000000, 2, 25000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"Am486DX2/66", CPU_Am486DX, 6, 66666666, 2, 33333333, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"Am486DX2/80", CPU_Am486DX, 8, 80000000, 2, 20000000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14,6,6},
{"Am486DX4/75", CPU_Am486DX, 7, 75000000, 3, 25000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9},
{"Am486DX4/90", CPU_Am486DX, 9, 90000000, 3, 30000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9},
{"Am486DX4/100", CPU_Am486DX, 10, 100000000, 3, 33333333, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15,9,9},
{"Am486DX4/120", CPU_Am486DX, 11, 120000000, 3, 20000000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21,9,9},
{"Am5x86/P75", CPU_Am486DX, 12, 133333333, 4, 33333333, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12},
{"Am5x86/P75+", CPU_Am486DX, 13, 160000000, 4, 20000000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12},
{"", -1, 0, 0, 0}
};
CPU cpus_Cx486[] =
{
/*Cx486/5x86*/
{"Cx486S/25", CPU_Cx486S, 2, 25000000, 1, 25000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
{"Cx486S/33", CPU_Cx486S, 3, 33333333, 1, 33333333, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
{"Cx486S/40", CPU_Cx486S, 4, 40000000, 1, 20000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
{"Cx486DX/33", CPU_Cx486DX, 3, 33333333, 1, 33333333, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC},
{"Cx486DX/40", CPU_Cx486DX, 4, 40000000, 1, 20000000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC},
{"Cx486DX2/50", CPU_Cx486DX, 5, 50000000, 2, 25000000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC},
{"Cx486DX2/66", CPU_Cx486DX, 6, 66666666, 2, 33333333, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC},
{"Cx486DX2/80", CPU_Cx486DX, 8, 80000000, 2, 20000000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC},
{"Cx486DX4/75", CPU_Cx486DX, 7, 75000000, 3, 25000000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC},
{"Cx486DX4/100", CPU_Cx486DX, 10, 100000000, 3, 33333333, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC},
{"Cx5x86/100", CPU_Cx5x86, 10, 100000000, 3, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
{"Cx5x86/120", CPU_Cx5x86, 11, 120000000, 3, 20000000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
{"Cx5x86/133", CPU_Cx5x86, 12, 133333333, 4, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
{"Cx486S/25", CPU_Cx486S, 2, 25000000, 1, 25000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4,4,3,3},
{"Cx486S/33", CPU_Cx486S, 3, 33333333, 1, 33333333, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"Cx486S/40", CPU_Cx486S, 4, 40000000, 1, 20000000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7,7,3,3},
{"Cx486DX/33", CPU_Cx486DX, 3, 33333333, 1, 33333333, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6,6,3,3},
{"Cx486DX/40", CPU_Cx486DX, 4, 40000000, 1, 20000000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7,7,3,3},
{"Cx486DX2/50", CPU_Cx486DX, 5, 50000000, 2, 25000000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"Cx486DX2/66", CPU_Cx486DX, 6, 66666666, 2, 33333333, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"Cx486DX2/80", CPU_Cx486DX, 8, 80000000, 2, 20000000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14,16,16},
{"Cx486DX4/75", CPU_Cx486DX, 7, 75000000, 3, 25000000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12,9,9},
{"Cx486DX4/100", CPU_Cx486DX, 10, 100000000, 3, 33333333, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15,9,9},
{"Cx5x86/100", CPU_Cx5x86, 10, 100000000, 3, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15,9,9},
{"Cx5x86/120", CPU_Cx5x86, 11, 120000000, 3, 20000000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21,9,9},
{"Cx5x86/133", CPU_Cx5x86, 12, 133333333, 4, 33333333, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12},
{"", -1, 0, 0, 0}
};
CPU cpus_6x86[] =
{
/*Cyrix 6x86*/
{"6x86-P90", CPU_Cx6x86, 17, 80000000, 3, 40000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-PR120+", CPU_Cx6x86, 17, 100000000, 3, 25000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-PR133+", CPU_Cx6x86, 17, 110000000, 3, 27500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-PR150+", CPU_Cx6x86, 17, 120000000, 3, 30000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-PR166+", CPU_Cx6x86, 17, 133333333, 3, 33333333, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-PR200+", CPU_Cx6x86, 17, 150000000, 3, 37500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86-P90", CPU_Cx6x86, 17, 80000000, 3, 40000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8,8,6,6},
{"6x86-PR120+", CPU_Cx6x86, 17, 100000000, 3, 25000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6},
{"6x86-PR133+", CPU_Cx6x86, 17, 110000000, 3, 27500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6},
{"6x86-PR150+", CPU_Cx6x86, 17, 120000000, 3, 30000000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"6x86-PR166+", CPU_Cx6x86, 17, 133333333, 3, 33333333, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"6x86-PR200+", CPU_Cx6x86, 17, 150000000, 3, 37500000, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
/*Cyrix 6x86L*/
{"6x86L-PR133+", CPU_Cx6x86L, 19, 110000000, 3, 27500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86L-PR150+", CPU_Cx6x86L, 19, 120000000, 3, 30000000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86L-PR166+", CPU_Cx6x86L, 19, 133333333, 3, 33333333, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86L-PR200+", CPU_Cx6x86L, 19, 150000000, 3, 37500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86L-PR133+", CPU_Cx6x86L, 19, 110000000, 3, 27500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6},
{"6x86L-PR150+", CPU_Cx6x86L, 19, 120000000, 3, 30000000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"6x86L-PR166+", CPU_Cx6x86L, 19, 133333333, 3, 33333333, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"6x86L-PR200+", CPU_Cx6x86L, 19, 150000000, 3, 37500000, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
/*Cyrix 6x86MX*/
{"6x86MX-PR166", CPU_Cx6x86MX, 18, 133333333, 3, 33333333, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR200", CPU_Cx6x86MX, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR233", CPU_Cx6x86MX, 18, 188888888, 3, 37500000, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR266", CPU_Cx6x86MX, 18, 207500000, 3, 41666667, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR300", CPU_Cx6x86MX, 18, 233333333, 3, 33333333, 0x600, 0x600, 0x0454, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR333", CPU_Cx6x86MX, 18, 250000000, 3, 41666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR366", CPU_Cx6x86MX, 18, 250000000, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR400", CPU_Cx6x86MX, 18, 285000000, 3, 31666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"6x86MX-PR166", CPU_Cx6x86MX, 18, 133333333, 3, 33333333, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"6x86MX-PR200", CPU_Cx6x86MX, 18, 166666666, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"6x86MX-PR233", CPU_Cx6x86MX, 18, 188888888, 3, 37500000, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"6x86MX-PR266", CPU_Cx6x86MX, 18, 207500000, 3, 41666667, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17,7,7},
{"6x86MX-PR300", CPU_Cx6x86MX, 18, 233333333, 3, 33333333, 0x600, 0x600, 0x0454, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,7,7},
{"6x86MX-PR333", CPU_Cx6x86MX, 18, 250000000, 3, 41666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 20,20,9,9},
{"6x86MX-PR366", CPU_Cx6x86MX, 18, 250000000, 3, 33333333, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12},
{"6x86MX-PR400", CPU_Cx6x86MX, 18, 285000000, 3, 31666667, 0x600, 0x600, 0x0453, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"", -1, 0, 0, 0}
};
@ -329,80 +334,80 @@ CPU cpus_Cx486[] =
CPU cpus_WinChip[] =
{
/*IDT WinChip*/
{"WinChip 75", CPU_WINCHIP, 7, 75000000, 2, 25000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 90", CPU_WINCHIP, 9, 90000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 100", CPU_WINCHIP, 10, 100000000, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 120", CPU_WINCHIP, 11, 120000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 133", CPU_WINCHIP, 12, 133333333, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 150", CPU_WINCHIP, 13, 150000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 166", CPU_WINCHIP, 15, 166666666, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 180", CPU_WINCHIP, 16, 180000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
{"WinChip 75", CPU_WINCHIP, 7, 75000000, 2, 25000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8,8,4,4},
{"WinChip 90", CPU_WINCHIP, 9, 90000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4},
{"WinChip 100", CPU_WINCHIP, 10, 100000000, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9,9,4,4},
{"WinChip 120", CPU_WINCHIP, 11, 120000000, 2, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"WinChip 133", CPU_WINCHIP, 12, 133333333, 2, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"WinChip 150", CPU_WINCHIP, 13, 150000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7},
{"WinChip 166", CPU_WINCHIP, 15, 166666666, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7},
{"WinChip 180", CPU_WINCHIP, 16, 180000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9},
{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9},
{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9},
{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12},
{"", -1, 0, 0, 0}
};
CPU cpus_Pentium5V[] =
{
/*Intel Pentium (5V, socket 4)*/
{"Pentium 60", CPU_PENTIUM, 6, 60000000, 1, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 66", CPU_PENTIUM, 6, 66666666, 1, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 120",CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 133",CPU_PENTIUM, 16, 133333333, 2, 33333333, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 60", CPU_PENTIUM, 6, 60000000, 1, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3},
{"Pentium 66", CPU_PENTIUM, 6, 66666666, 1, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6,6,3,3},
{"Pentium OverDrive 120",CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Pentium OverDrive 133",CPU_PENTIUM, 16, 133333333, 2, 33333333, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"", -1, 0, 0, 0}
};
CPU cpus_PentiumS5[] =
{
/*Intel Pentium (Socket 5)*/
{"Pentium 75", CPU_PENTIUM, 9, 75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 90", CPU_PENTIUM, 12, 90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 100/50", CPU_PENTIUM, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 100/66", CPU_PENTIUM, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 120", CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 75", CPU_PENTIUM, 9, 75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4},
{"Pentium 90", CPU_PENTIUM, 12, 90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4},
{"Pentium 100/50", CPU_PENTIUM, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6},
{"Pentium 100/66", CPU_PENTIUM, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4},
{"Pentium 120", CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7},
{"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"", -1, 0, 0, 0}
};
CPU cpus_Pentium[] =
{
/*Intel Pentium*/
{"Pentium 75", CPU_PENTIUM, 9, 75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 90", CPU_PENTIUM, 12, 90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 100/50", CPU_PENTIUM, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 100/66", CPU_PENTIUM, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 120", CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 133", CPU_PENTIUM, 16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 150", CPU_PENTIUM, 17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 166", CPU_PENTIUM, 19, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 200", CPU_PENTIUM, 21, 200000000, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium MMX 166", CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium MMX 200", CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium MMX 233", CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 14, 120000000, 2, 30000000, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 16, 133333333, 2, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 17, 150000000, 3, 30000000, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 26, 266666666, 4, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 28, 300000000, 5, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
{"Pentium 75", CPU_PENTIUM, 9, 75000000, 2, 25000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7,7,4,4},
{"Pentium 90", CPU_PENTIUM, 12, 90000000, 2, 30000000, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4},
{"Pentium 100/50", CPU_PENTIUM, 13, 100000000, 2, 25000000, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6},
{"Pentium 100/66", CPU_PENTIUM, 13, 100000000, 2, 33333333, 0x525, 0x525, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9,9,4,4},
{"Pentium 120", CPU_PENTIUM, 14, 120000000, 2, 30000000, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Pentium 133", CPU_PENTIUM, 16, 133333333, 2, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Pentium 150", CPU_PENTIUM, 17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium 166", CPU_PENTIUM, 19, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium 200", CPU_PENTIUM, 21, 200000000, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"Pentium MMX 166", CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium MMX 200", CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"Pentium MMX 233", CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10},
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 14, 120000000, 2, 30000000, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 16, 133333333, 2, 33333333, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6},
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 17, 150000000, 3, 30000000, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 19, 166666666, 3, 33333333, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 21, 200000000, 3, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 24, 233333333, 4, 33333333, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10},
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 26, 266666666, 4, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12},
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 28, 300000000, 5, 33333333, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13},
{"Pentium OverDrive 125",CPU_PENTIUM,15, 125000000, 3, 25000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7},
{"Pentium OverDrive 150",CPU_PENTIUM,17, 150000000, 3, 30000000, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive 166",CPU_PENTIUM,17, 166666666, 3, 33333333, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX,15,125000000, 3, 25000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX,17,150000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX,19,166000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX,20,180000000, 3, 30000000, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX,21,200000000, 3, 33333333, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9},
{"", -1, 0, 0, 0}
};
@ -431,7 +436,7 @@ void cpu_set()
is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC);
hasfpu = (cpu_s->cpu_type >= CPU_i486DX);
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
cpu_16bitbus = (cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC);
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC);
if (cpu_s->multi)
cpu_busspeed = cpu_s->rspeed / cpu_s->multi;
cpu_multi = cpu_s->multi;
@ -440,6 +445,8 @@ void cpu_set()
cpu_hasMSR = 0;
cpu_hasCR4 = 0;
ccr0 = ccr1 = ccr2 = ccr3 = ccr4 = ccr5 = ccr6 = 0;
cpu_update_waitstates();
isa_cycles = (int)(((int64_t)cpu_s->rspeed << ISA_CYCLES_SHIFT) / 8000000ll);
@ -1502,3 +1509,43 @@ void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn
x86_dynarec_opcodes = dynarec_opcodes;
x86_dynarec_opcodes_0f = dynarec_opcodes_0f;
}
void cpu_update_waitstates()
{
cpu_s = &models[model].cpu[cpu_manufacturer].cpus[cpu];
cpu_prefetch_width = cpu_16bitbus ? 2 : 4;
if (cpu_cache_int_enabled)
{
/* Disable prefetch emulation */
cpu_prefetch_cycles = 0;
}
else if (cpu_waitstates)
{
/* Waitstates override */
cpu_prefetch_cycles = cpu_waitstates+1;
cpu_cycles_read = cpu_waitstates+1;
cpu_cycles_read_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates+1);
cpu_cycles_write = cpu_waitstates+1;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates+1);
}
else if (cpu_cache_ext_enabled)
{
/* Use cache timings */
cpu_prefetch_cycles = cpu_s->cache_read_cycles;
cpu_cycles_read = cpu_s->cache_read_cycles;
cpu_cycles_read_l = (cpu_16bitbus ? 2 : 1) * cpu_s->cache_read_cycles;
cpu_cycles_write = cpu_s->cache_write_cycles;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->cache_write_cycles;
}
else
{
/* Use memory timings */
cpu_prefetch_cycles = cpu_s->mem_read_cycles;
cpu_cycles_read = cpu_s->mem_read_cycles;
cpu_cycles_read_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_read_cycles;
cpu_cycles_write = cpu_s->mem_write_cycles;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles;
}
}

9
src/cpu.h
View file

@ -64,6 +64,8 @@ typedef struct
uint32_t cpuid_model;
uint16_t cyrix_id;
int cpu_flags;
int mem_read_cycles, mem_write_cycles;
int cache_read_cycles, cache_write_cycles;
} CPU;
extern CPU cpus_8088[];
@ -107,6 +109,11 @@ extern uint64_t cpu_CR4_mask;
#define CPU_SUPPORTS_DYNAREC 1
#define CPU_REQUIRES_DYNAREC 2
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width;
extern int cpu_waitstates;
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
extern uint64_t tsc;
void cyrix_write(uint16_t addr, uint8_t val, void *priv);
@ -125,4 +132,6 @@ extern int xt_cpu_multi;
extern int isa_cycles;
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
void cpu_update_waitstates();
#endif

6
src/pc.c
View file

@ -387,6 +387,8 @@ void resetpchard()
keyboard_at_reset();
cpu_cache_int_enabled = cpu_cache_ext_enabled = 0;
// output=3;
#if __unix
@ -591,7 +593,8 @@ void loadconfig(char *fn)
cpu_manufacturer = config_get_int(NULL, "cpu_manufacturer", 0);
cpu = config_get_int(NULL, "cpu", 0);
cpu_use_dynarec = config_get_int(NULL, "cpu_use_dynarec", 0);
cpu_waitstates = config_get_int(NULL, "cpu_waitstates", 0);
gfxcard = config_get_int(NULL, "gfxcard", 0);
video_speed = config_get_int(NULL, "video_speed", 3);
sound_card_current = config_get_int(NULL, "sndcard", SB2);
@ -704,6 +707,7 @@ void saveconfig()
config_set_int(NULL, "cpu_manufacturer", cpu_manufacturer);
config_set_int(NULL, "cpu", cpu);
config_set_int(NULL, "cpu_use_dynarec", cpu_use_dynarec);
config_set_int(NULL, "cpu_waitstates", cpu_waitstates);
config_set_int(NULL, "gfxcard", gfxcard);
config_set_int(NULL, "video_speed", video_speed);

64
src/pc.rc
View file

@ -57,51 +57,53 @@ BEGIN
END
END
ConfigureDlg DIALOGEX 0, 0, 232+40, 308+40+40
ConfigureDlg DIALOGEX 0, 0, 232+40, 408
STYLE DS_SETFONT | DS_MODALFRAME | DS_FIXEDSYS | WS_POPUP | WS_CAPTION | WS_SYSMENU
CAPTION "Configure PCem"
FONT 8, "MS Sans Serif"
BEGIN
DEFPUSHBUTTON "OK",IDOK,64,324+40,50,14, WS_TABSTOP
PUSHBUTTON "Cancel",IDCANCEL,128,324+40,50,14, WS_TABSTOP
DEFPUSHBUTTON "OK",IDOK,64,384,50,14, WS_TABSTOP
PUSHBUTTON "Cancel",IDCANCEL,128,384,50,14, WS_TABSTOP
COMBOBOX IDC_COMBO1,62,16,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOVID,62,36,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure", IDC_CONFIGUREVID, 224, 36, 40, 14, WS_TABSTOP
COMBOBOX IDC_COMBOCPUM,62,56,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBO3,62,76,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
CONTROL "Dynamic Recompiler",IDC_CHECKDYNAREC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,96,118,10
COMBOBOX IDC_COMBOCHC,62,116,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSPD,62,136,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSND,62,156,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure", IDC_CONFIGURESND, 224, 156, 40, 14, WS_TABSTOP
EDITTEXT IDC_MEMTEXT, 62, 172, 36, 14, ES_AUTOHSCROLL | ES_NUMBER
CONTROL "", IDC_MEMSPIN, UPDOWN_CLASS, UDS_ALIGNRIGHT | UDS_ARROWKEYS | UDS_NOTHOUSANDS | UDS_SETBUDDYINT, 98, 172, 12, 14
LTEXT "MB", IDC_TEXT_MB, 98, 172, 40, 10
CONTROL "CMS / Game Blaster",IDC_CHECK3,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,272,118,10
CONTROL "Gravis Ultrasound",IDC_CHECKGUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,288,118,10
CONTROL "Innovation SSI-2001",IDC_CHECKSSI,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,304,118,10
CONTROL "Composite CGA",IDC_CHECK4,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,320,118,10
CONTROL "Synchronise time to host clock",IDC_CHECKSYNC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,336,118,10
CONTROL "Voodoo Graphics",IDC_CHECKVOODOO,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,352,118,10
PUSHBUTTON "Configure", IDC_CONFIGUREVOODOO, 224, 352, 40, 14, WS_TABSTOP
COMBOBOX IDC_COMBOWS, 62,116,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOCHC,62,136,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSPD,62,156,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBOSND,62,176,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure", IDC_CONFIGURESND, 224, 176, 40, 14, WS_TABSTOP
EDITTEXT IDC_MEMTEXT, 62, 192, 36, 14, ES_AUTOHSCROLL | ES_NUMBER
CONTROL "", IDC_MEMSPIN, UPDOWN_CLASS, UDS_ALIGNRIGHT | UDS_ARROWKEYS | UDS_NOTHOUSANDS | UDS_SETBUDDYINT, 98, 192, 12, 14
LTEXT "MB", IDC_TEXT_MB, 98, 192, 40, 10
CONTROL "CMS / Game Blaster",IDC_CHECK3,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,292,118,10
CONTROL "Gravis Ultrasound",IDC_CHECKGUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,308,118,10
CONTROL "Innovation SSI-2001",IDC_CHECKSSI,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,324,118,10
CONTROL "Composite CGA",IDC_CHECK4,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,340,118,10
CONTROL "Synchronise time to host clock",IDC_CHECKSYNC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,356,118,10
CONTROL "Voodoo Graphics",IDC_CHECKVOODOO,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,372,118,10
PUSHBUTTON "Configure", IDC_CONFIGUREVOODOO, 224, 372, 40, 14, WS_TABSTOP
LTEXT "Machine :",IDC_STATIC,15,16,40,10
LTEXT "Video :",IDC_STATIC,15,36,34,10
LTEXT "CPU type :",IDC_STATIC,15,56,34,10
LTEXT "CPU :",IDC_STATIC,15,76,34,10
LTEXT "Cache :",IDC_STATIC,15,116,40,10
LTEXT "Video speed :",IDC_STATIC,15,136,40,10
LTEXT "Soundcard :",IDC_STATIC,15,156,40,10
LTEXT "Memory :",IDC_STATIC,15,176,40,10
LTEXT "Drive A: :",IDC_STATIC,15,196,40,10
LTEXT "Drive B: :",IDC_STATIC,15,216,40,10
COMBOBOX IDC_COMBODRA,62,196,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBODRB,62,216,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
LTEXT "Joystick :",IDC_STATIC,15,236,40,10
COMBOBOX IDC_COMBOJOY,62,236,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
DEFPUSHBUTTON "Joystick 1...",IDC_JOY1,16,252,50,14, WS_TABSTOP
PUSHBUTTON "Joystick 2...",IDC_JOY2,80,252,50,14, WS_TABSTOP
DEFPUSHBUTTON "Joystick 3...",IDC_JOY3,144,252,50,14, WS_TABSTOP
PUSHBUTTON "Joystick 4...",IDC_JOY4,208,252,50,14, WS_TABSTOP
LTEXT "Waitstates :",IDC_STATIC,15,116,40,10
LTEXT "Cache :",IDC_STATIC,15,136,40,10
LTEXT "Video speed :",IDC_STATIC,15,156,40,10
LTEXT "Soundcard :",IDC_STATIC,15,176,40,10
LTEXT "Memory :",IDC_STATIC,15,196,40,10
LTEXT "Drive A: :",IDC_STATIC,15,216,40,10
LTEXT "Drive B: :",IDC_STATIC,15,236,40,10
COMBOBOX IDC_COMBODRA,62,216,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_COMBODRB,62,236,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
LTEXT "Joystick :",IDC_STATIC,15,256,40,10
COMBOBOX IDC_COMBOJOY,62,256,157,120,CBS_DROPDOWN | WS_VSCROLL | WS_TABSTOP
DEFPUSHBUTTON "Joystick 1...",IDC_JOY1,16,272,50,14, WS_TABSTOP
PUSHBUTTON "Joystick 2...",IDC_JOY2,80,272,50,14, WS_TABSTOP
DEFPUSHBUTTON "Joystick 3...",IDC_JOY3,144,272,50,14, WS_TABSTOP
PUSHBUTTON "Joystick 4...",IDC_JOY4,208,272,50,14, WS_TABSTOP
END
HdConfDlg DIALOGEX 0, 0, 210, 312+4*16

1
src/resources.h
View file

@ -39,6 +39,7 @@
#define IDC_COMBODRA 1062
#define IDC_COMBODRB 1063
#define IDC_COMBOJOY 1064
#define IDC_COMBOWS 1065
#define IDC_CHECK1 1010
#define IDC_CHECK2 1011
#define IDC_CHECK3 1012

16
src/win-config.c
View file

@ -242,6 +242,18 @@ static BOOL CALLBACK config_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPAR
EnableWindow(h, (joystick_get_max_joysticks(joystick_type) >= 3) ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_JOY4);
EnableWindow(h, (joystick_get_max_joysticks(joystick_type) >= 4) ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_COMBOWS);
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"System default");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"0 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"1 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"2 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"3 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"4 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"5 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"6 W/S");
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"7 W/S");
SendMessage(h, CB_SETCURSEL, cpu_waitstates, 0);
return TRUE;
case WM_COMMAND:
@ -352,6 +364,10 @@ static BOOL CALLBACK config_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPAR
cache=SendMessage(h, CB_GETCURSEL, 0, 0);
mem_updatecache();
h = GetDlgItem(hdlg, IDC_COMBOWS);
cpu_waitstates = SendMessage(h, CB_GETCURSEL, 0, 0);
cpu_update_waitstates();
saveconfig();
speedchanged();

89
src/x86_ops_arith.h
View file

@ -10,6 +10,7 @@
setflags ## 8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@ -18,6 +19,7 @@
seteab(operation); if (cpu_state.abrt) return 1; \
setflags ## 8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 0); \
} \
return 0; \
} \
@ -32,6 +34,7 @@
setflags ## 8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@ -40,6 +43,7 @@
seteab(operation); if (cpu_state.abrt) return 1; \
setflags ## 8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 1); \
} \
return 0; \
} \
@ -55,6 +59,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@ -63,6 +68,7 @@
seteaw(operation); if (cpu_state.abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 0); \
} \
return 0; \
} \
@ -77,6 +83,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@ -85,6 +92,7 @@
seteaw(operation); if (cpu_state.abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 1); \
} \
return 0; \
} \
@ -100,6 +108,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@ -107,7 +116,8 @@
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 0); \
} \
return 0; \
} \
@ -122,6 +132,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@ -129,7 +140,8 @@
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 1); \
} \
return 0; \
} \
@ -144,6 +156,7 @@
setflags ## 8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
return 0; \
} \
static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
@ -156,6 +169,7 @@
setflags ## 8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
return 0; \
} \
\
@ -169,6 +183,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
return 0; \
} \
static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
@ -181,6 +196,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
return 0; \
} \
\
@ -194,6 +210,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0); \
return 0; \
} \
static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
@ -206,6 +223,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1); \
return 0; \
} \
\
@ -217,6 +235,7 @@
setflags ## 8 flagops; \
AL = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@ -228,6 +247,7 @@
setflags ## 16 flagops; \
AX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@ -239,6 +259,7 @@
setflags ## 32 flagops; \
EAX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0); \
return 0; \
}
@ -258,6 +279,7 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_b_rmw_a32(uint32_t fetchdat)
@ -268,6 +290,7 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -279,6 +302,7 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_w_rmw_a32(uint32_t fetchdat)
@ -289,6 +313,7 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -300,6 +325,7 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opCMP_l_rmw_a32(uint32_t fetchdat)
@ -310,6 +336,7 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@ -320,6 +347,7 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
src = geteab(); if (cpu_state.abrt) return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_b_rm_a32(uint32_t fetchdat)
@ -329,6 +357,7 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
src = geteab(); if (cpu_state.abrt) return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -339,6 +368,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
src = geteaw(); if (cpu_state.abrt) return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_w_rm_a32(uint32_t fetchdat)
@ -348,6 +378,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
src = geteaw(); if (cpu_state.abrt) return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -358,6 +389,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
src = geteal(); if (cpu_state.abrt) return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opCMP_l_rm_a32(uint32_t fetchdat)
@ -367,6 +399,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
src = geteal(); if (cpu_state.abrt) return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@ -375,6 +408,7 @@ static int opCMP_AL_imm(uint32_t fetchdat)
uint8_t src = getbytef();
setsub8(AL, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
@ -383,6 +417,7 @@ static int opCMP_AX_imm(uint32_t fetchdat)
uint16_t src = getwordf();
setsub16(AX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
@ -391,6 +426,7 @@ static int opCMP_EAX_imm(uint32_t fetchdat)
uint32_t src = getlong(); if (cpu_state.abrt) return 1;
setsub32(EAX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
@ -403,6 +439,7 @@ static int opTEST_b_a16(uint32_t fetchdat)
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opTEST_b_a32(uint32_t fetchdat)
@ -414,6 +451,7 @@ static int opTEST_b_a32(uint32_t fetchdat)
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -426,6 +464,7 @@ static int opTEST_w_a16(uint32_t fetchdat)
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opTEST_w_a32(uint32_t fetchdat)
@ -437,6 +476,7 @@ static int opTEST_w_a32(uint32_t fetchdat)
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@ -449,6 +489,7 @@ static int opTEST_l_a16(uint32_t fetchdat)
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opTEST_l_a32(uint32_t fetchdat)
@ -460,6 +501,7 @@ static int opTEST_l_a32(uint32_t fetchdat)
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@ -468,6 +510,7 @@ static int opTEST_AL(uint32_t fetchdat)
uint8_t temp = getbytef();
setznp8(AL & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opTEST_AX(uint32_t fetchdat)
@ -475,6 +518,7 @@ static int opTEST_AX(uint32_t fetchdat)
uint16_t temp = getwordf();
setznp16(AX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opTEST_EAX(uint32_t fetchdat)
@ -482,6 +526,7 @@ static int opTEST_EAX(uint32_t fetchdat)
uint32_t temp = getlong(); if (cpu_state.abrt) return 1;
setznp32(EAX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
@ -545,6 +590,10 @@ static int op80_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@ -555,6 +604,10 @@ static int op80_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -565,6 +618,10 @@ static int op81_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@ -575,6 +632,10 @@ static int op81_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -585,6 +646,10 @@ static int op81_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
@ -595,6 +660,10 @@ static int op81_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}
@ -607,6 +676,10 @@ static int op83_w_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@ -618,6 +691,10 @@ static int op83_w_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -630,6 +707,10 @@ static int op83_l_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
@ -641,6 +722,10 @@ static int op83_l_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}

6
src/x86_ops_bcd.h
View file

@ -11,6 +11,7 @@ static int opAAA(uint32_t fetchdat)
flags &= ~(A_FLAG | C_FLAG);
AL &= 0xF;
CLOCK_CYCLES(is486 ? 3 : 4);
PREFETCH_RUN(is486 ? 3 : 4, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -22,6 +23,7 @@ static int opAAD(uint32_t fetchdat)
AH = 0;
setznp16(AX);
CLOCK_CYCLES((is486) ? 14 : 19);
PREFETCH_RUN(is486 ? 14 : 19, 2, -1, 0,0,0,0, 0);
return 0;
}
@ -33,6 +35,7 @@ static int opAAM(uint32_t fetchdat)
AL %= base;
setznp16(AX);
CLOCK_CYCLES((is486) ? 15 : 17);
PREFETCH_RUN(is486 ? 15 : 17, 2, -1, 0,0,0,0, 0);
return 0;
}
@ -49,6 +52,7 @@ static int opAAS(uint32_t fetchdat)
flags &= ~(A_FLAG | C_FLAG);
AL &= 0xF;
CLOCK_CYCLES(is486 ? 3 : 4);
PREFETCH_RUN(is486 ? 3 : 4, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -75,6 +79,7 @@ static int opDAA(uint32_t fetchdat)
flags_rebuild();
flags |= tempw;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -102,6 +107,7 @@ static int opDAS(uint32_t fetchdat)
flags_rebuild();
flags |= tempw;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,0, 0);
return 0;
}

16
src/x86_ops_bit.h
View file

@ -11,6 +11,7 @@ static int opBT_w_r_a16(uint32_t fetchdat)
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 1,0,0,0, 0);
return 0;
}
static int opBT_w_r_a32(uint32_t fetchdat)
@ -25,6 +26,7 @@ static int opBT_w_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 1,0,0,0, 1);
return 0;
}
static int opBT_l_r_a16(uint32_t fetchdat)
@ -39,6 +41,7 @@ static int opBT_l_r_a16(uint32_t fetchdat)
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 0,1,0,0, 0);
return 0;
}
static int opBT_l_r_a32(uint32_t fetchdat)
@ -53,6 +56,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 0,1,0,0, 1);
return 0;
}
@ -73,6 +77,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1,0,1,0, 0); \
return 0; \
} \
static int opBT ## name ## _w_r_a32(uint32_t fetchdat) \
@ -91,6 +96,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1,0,1,0, 1); \
return 0; \
} \
static int opBT ## name ## _l_r_a16(uint32_t fetchdat) \
@ -109,6 +115,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0,1,0,1, 0); \
return 0; \
} \
static int opBT ## name ## _l_r_a32(uint32_t fetchdat) \
@ -127,6 +134,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
else flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0,1,0,1, 1); \
return 0; \
}
@ -151,6 +159,7 @@ static int opBA_w_a16(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
case 0x28: /*BTS w,imm*/
temp |= (1 << count);
@ -172,6 +181,7 @@ static int opBA_w_a16(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opBA_w_a32(uint32_t fetchdat)
@ -191,6 +201,7 @@ static int opBA_w_a32(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
case 0x28: /*BTS w,imm*/
temp |= (1 << count);
@ -212,6 +223,7 @@ static int opBA_w_a32(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@ -232,6 +244,7 @@ static int opBA_l_a16(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
case 0x28: /*BTS w,imm*/
temp |= (1 << count);
@ -253,6 +266,7 @@ static int opBA_l_a16(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
static int opBA_l_a32(uint32_t fetchdat)
@ -272,6 +286,7 @@ static int opBA_l_a32(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
case 0x28: /*BTS w,imm*/
temp |= (1 << count);
@ -293,5 +308,6 @@ static int opBA_l_a32(uint32_t fetchdat)
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}

27
src/x86_ops_bitscan.h
View file

@ -7,6 +7,7 @@
for (c = start; c != end; c += dir) \
{ \
CLOCK_CYCLES(time); \
instr_cycles += time; \
if (temp & (1 << c)) \
{ \
dest = c; \
@ -20,6 +21,7 @@
static int opBSF_w_a16(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@ -27,11 +29,14 @@ static int opBSF_w_a16(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opBSF_w_a32(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@ -39,11 +44,14 @@ static int opBSF_w_a32(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opBSF_l_a16(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@ -51,24 +59,30 @@ static int opBSF_l_a16(uint32_t fetchdat)
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
}
static int opBSF_l_a32(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
}
static int opBSR_w_a16(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@ -76,11 +90,14 @@ static int opBSR_w_a16(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opBSR_w_a32(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@ -88,11 +105,14 @@ static int opBSR_w_a32(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opBSR_l_a16(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@ -100,11 +120,14 @@ static int opBSR_l_a16(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
}
static int opBSR_l_a32(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@ -112,6 +135,8 @@ static int opBSR_l_a32(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
}

65
src/x86_ops_call.h
View file

@ -61,26 +61,32 @@ static int opCALL_far_w(uint32_t fetchdat)
{
uint32_t old_cs, old_pc;
uint16_t new_cs, new_pc;
int cycles_old = cycles;
new_pc = getwordf();
new_cs = getword(); if (cpu_state.abrt) return 1;
CALL_FAR_w(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 5, -1, 0,0,cgate16 ? 2:0,cgate16 ? 0:2, 0);
PREFETCH_FLUSH();
return 0;
}
static int opCALL_far_l(uint32_t fetchdat)
{
uint32_t old_cs, old_pc;
uint32_t new_cs, new_pc;
int cycles_old = cycles;
new_pc = getlong();
new_cs = getword(); if (cpu_state.abrt) return 1;
CALL_FAR_l(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 7, -1, 0,0,cgate16 ? 2:0,cgate16 ? 0:2, 0);
PREFETCH_FLUSH();
return 0;
}
@ -89,6 +95,7 @@ static int opFF_w_a16(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
uint16_t temp;
@ -101,12 +108,14 @@ static int opFF_w_a16(uint32_t fetchdat)
seteaw(temp + 1); if (cpu_state.abrt) return 1;
setadd16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x08: /*DEC w*/
temp = geteaw(); if (cpu_state.abrt) return 1;
seteaw(temp - 1); if (cpu_state.abrt) return 1;
setsub16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x10: /*CALL*/
new_pc = geteaw(); if (cpu_state.abrt) return 1;
@ -115,6 +124,8 @@ static int opFF_w_a16(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 0);
PREFETCH_FLUSH();
break;
case 0x18: /*CALL far*/
new_pc = readmemw(easeg, cpu_state.eaaddr);
@ -122,6 +133,8 @@ static int opFF_w_a16(uint32_t fetchdat)
CALL_FAR_w(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 2,0,cgate16 ? 2:0,cgate16 ? 0:2, 0);
PREFETCH_FLUSH();
break;
case 0x20: /*JMP*/
new_pc = geteaw(); if (cpu_state.abrt) return 1;
@ -129,6 +142,8 @@ static int opFF_w_a16(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
PREFETCH_FLUSH();
break;
case 0x28: /*JMP far*/
oxpc = cpu_state.pc;
@ -137,11 +152,14 @@ static int opFF_w_a16(uint32_t fetchdat)
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 2,0,0,0, 0);
PREFETCH_FLUSH();
break;
case 0x30: /*PUSH w*/
temp = geteaw(); if (cpu_state.abrt) return 1;
PUSH_W(temp);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 0);
break;
default:
@ -154,6 +172,7 @@ static int opFF_w_a32(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
uint16_t temp;
@ -166,12 +185,14 @@ static int opFF_w_a32(uint32_t fetchdat)
seteaw(temp + 1); if (cpu_state.abrt) return 1;
setadd16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x08: /*DEC w*/
temp = geteaw(); if (cpu_state.abrt) return 1;
seteaw(temp - 1); if (cpu_state.abrt) return 1;
setsub16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x10: /*CALL*/
new_pc = geteaw(); if (cpu_state.abrt) return 1;
@ -180,6 +201,8 @@ static int opFF_w_a32(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 1);
PREFETCH_FLUSH();
break;
case 0x18: /*CALL far*/
new_pc = readmemw(easeg, cpu_state.eaaddr);
@ -187,6 +210,8 @@ static int opFF_w_a32(uint32_t fetchdat)
CALL_FAR_w(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 2,0,cgate16 ? 2:0,cgate16 ? 0:2, 1);
PREFETCH_FLUSH();
break;
case 0x20: /*JMP*/
new_pc = geteaw(); if (cpu_state.abrt) return 1;
@ -194,6 +219,8 @@ static int opFF_w_a32(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,0,0,0, 1);
PREFETCH_FLUSH();
break;
case 0x28: /*JMP far*/
oxpc = cpu_state.pc;
@ -202,11 +229,14 @@ static int opFF_w_a32(uint32_t fetchdat)
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 2,0,0,0, 1);
PREFETCH_FLUSH();
break;
case 0x30: /*PUSH w*/
temp = geteaw(); if (cpu_state.abrt) return 1;
PUSH_W(temp);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 1);
break;
default:
@ -220,7 +250,8 @@ static int opFF_l_a16(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
uint32_t temp;
fetch_ea_16(fetchdat);
@ -232,12 +263,14 @@ static int opFF_l_a16(uint32_t fetchdat)
seteal(temp + 1); if (cpu_state.abrt) return 1;
setadd32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
break;
case 0x08: /*DEC l*/
temp = geteal(); if (cpu_state.abrt) return 1;
seteal(temp - 1); if (cpu_state.abrt) return 1;
setsub32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
break;
case 0x10: /*CALL*/
new_pc = geteal(); if (cpu_state.abrt) return 1;
@ -246,6 +279,8 @@ static int opFF_l_a16(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 0);
PREFETCH_FLUSH();
break;
case 0x18: /*CALL far*/
new_pc = readmeml(easeg, cpu_state.eaaddr);
@ -253,6 +288,8 @@ static int opFF_l_a16(uint32_t fetchdat)
CALL_FAR_l(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,cgate16 ? 2:0,cgate16 ? 0:2, 0);
PREFETCH_FLUSH();
break;
case 0x20: /*JMP*/
new_pc = geteal(); if (cpu_state.abrt) return 1;
@ -260,6 +297,8 @@ static int opFF_l_a16(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 0,1,0,0, 0);
PREFETCH_FLUSH();
break;
case 0x28: /*JMP far*/
oxpc = cpu_state.pc;
@ -268,11 +307,14 @@ static int opFF_l_a16(uint32_t fetchdat)
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,0,0, 0);
PREFETCH_FLUSH();
break;
case 0x30: /*PUSH l*/
temp = geteal(); if (cpu_state.abrt) return 1;
PUSH_L(temp);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 0);
break;
default:
@ -285,7 +327,8 @@ static int opFF_l_a32(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
uint32_t temp;
fetch_ea_32(fetchdat);
@ -297,12 +340,14 @@ static int opFF_l_a32(uint32_t fetchdat)
seteal(temp + 1); if (cpu_state.abrt) return 1;
setadd32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
break;
case 0x08: /*DEC l*/
temp = geteal(); if (cpu_state.abrt) return 1;
seteal(temp - 1); if (cpu_state.abrt) return 1;
setsub32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
break;
case 0x10: /*CALL*/
new_pc = geteal(); if (cpu_state.abrt) return 1;
@ -311,6 +356,8 @@ static int opFF_l_a32(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 1);
PREFETCH_FLUSH();
break;
case 0x18: /*CALL far*/
new_pc = readmeml(easeg, cpu_state.eaaddr);
@ -318,6 +365,8 @@ static int opFF_l_a32(uint32_t fetchdat)
CALL_FAR_l(new_cs, new_pc);
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,cgate16 ? 2:0,cgate16 ? 0:2, 1);
PREFETCH_FLUSH();
break;
case 0x20: /*JMP*/
new_pc = geteal(); if (cpu_state.abrt) return 1;
@ -325,6 +374,8 @@ static int opFF_l_a32(uint32_t fetchdat)
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,0,0, 1);
PREFETCH_FLUSH();
break;
case 0x28: /*JMP far*/
oxpc = cpu_state.pc;
@ -333,11 +384,13 @@ static int opFF_l_a32(uint32_t fetchdat)
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (cpu_state.abrt) return 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,0,0, 1);
PREFETCH_FLUSH();
break;
case 0x30: /*PUSH l*/
temp = geteal(); if (cpu_state.abrt) return 1;
PUSH_L(temp);
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 1);
break;
default:

22
src/x86_ops_flag.h
View file

@ -3,6 +3,7 @@ static int opCMC(uint32_t fetchdat)
flags_rebuild();
flags ^= C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -12,12 +13,14 @@ static int opCLC(uint32_t fetchdat)
flags_rebuild();
flags &= ~C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCLD(uint32_t fetchdat)
{
flags &= ~D_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCLI(uint32_t fetchdat)
@ -33,6 +36,7 @@ static int opCLI(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -41,12 +45,14 @@ static int opSTC(uint32_t fetchdat)
flags_rebuild();
flags |= C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opSTD(uint32_t fetchdat)
{
flags |= D_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opSTI(uint32_t fetchdat)
@ -62,6 +68,7 @@ static int opSTI(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -70,7 +77,8 @@ static int opSAHF(uint32_t fetchdat)
flags_rebuild();
flags = (flags & 0xff00) | (AH & 0xd5) | 2;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
codegen_flags_changed = 0;
return 0;
@ -80,6 +88,7 @@ static int opLAHF(uint32_t fetchdat)
flags_rebuild();
AH = flags & 0xff;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -93,6 +102,7 @@ static int opPUSHF(uint32_t fetchdat)
flags_rebuild();
PUSH_W(flags);
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return cpu_state.abrt;
}
static int opPUSHFD(uint32_t fetchdat)
@ -108,6 +118,7 @@ static int opPUSHFD(uint32_t fetchdat)
flags_rebuild();
PUSH_L(flags | (tempw << 16));
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
return cpu_state.abrt;
}
@ -130,7 +141,8 @@ static int opPOPF_286(uint32_t fetchdat)
flags_extract();
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
codegen_flags_changed = 0;
return 0;
@ -153,7 +165,8 @@ static int opPOPF(uint32_t fetchdat)
flags_extract();
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
codegen_flags_changed = 0;
return 0;
@ -183,7 +196,8 @@ static int opPOPFD(uint32_t fetchdat)
flags_extract();
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
codegen_flags_changed = 0;
return 0;

3
src/x86_ops_inc_dec.h
View file

@ -4,6 +4,7 @@
setflags(reg, 1); \
reg += inc; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 1, -1, 0,0,0,0, 0); \
return 0; \
}
@ -62,6 +63,7 @@ static int opINCDEC_b_a16(uint32_t fetchdat)
setadd8nc(temp, 1);
}
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opINCDEC_b_a32(uint32_t fetchdat)
@ -82,5 +84,6 @@ static int opINCDEC_b_a32(uint32_t fetchdat)
setadd8nc(temp, 1);
}
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}

8
src/x86_ops_int.h
View file

@ -1,5 +1,6 @@
static int opINT3(uint32_t fetchdat)
{
int cycles_old = cycles;
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@ -7,11 +8,13 @@ static int opINT3(uint32_t fetchdat)
}
x86_int_sw(3);
CLOCK_CYCLES((is486) ? 44 : 59);
PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,0,0,0, 0);
return 1;
}
static int opINT(uint32_t fetchdat)
{
int cycles_old = cycles;
uint8_t temp;
/*if (msw&1) pclog("INT %i %i %i\n",cr0&1,eflags&VM_FLAG,IOPL);*/
@ -55,11 +58,14 @@ static int opINT(uint32_t fetchdat)
}*/
x86_int_sw(temp);
PREFETCH_RUN(cycles_old-cycles, 2, -1, 0,0,0,0, 0);
return 1;
}
static int opINTO(uint32_t fetchdat)
{
int cycles_old = cycles;
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@ -69,9 +75,11 @@ static int opINTO(uint32_t fetchdat)
{
cpu_state.oldpc = cpu_state.pc;
x86_int_sw(4);
PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,0,0,0, 0);
return 1;
}
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}

13
src/x86_ops_io.h
View file

@ -4,6 +4,7 @@ static int opIN_AL_imm(uint32_t fetchdat)
check_io_perm(port);
AL = inb(port);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 2, -1, 1,0,0,0, 0);
return 0;
}
static int opIN_AX_imm(uint32_t fetchdat)
@ -13,6 +14,7 @@ static int opIN_AX_imm(uint32_t fetchdat)
check_io_perm(port + 1);
AX = inw(port);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 2, -1, 1,0,0,0, 0);
return 0;
}
static int opIN_EAX_imm(uint32_t fetchdat)
@ -24,6 +26,7 @@ static int opIN_EAX_imm(uint32_t fetchdat)
check_io_perm(port + 3);
EAX = inl(port);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 2, -1, 0,1,0,0, 0);
return 0;
}
@ -33,6 +36,7 @@ static int opOUT_AL_imm(uint32_t fetchdat)
check_io_perm(port);
outb(port, AL);
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, -1, 0,0,1,0, 0);
if (port == 0x64)
return x86_was_reset;
return 0;
@ -44,6 +48,7 @@ static int opOUT_AX_imm(uint32_t fetchdat)
check_io_perm(port + 1);
outw(port, AX);
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, -1, 0,0,1,0, 0);
return 0;
}
static int opOUT_EAX_imm(uint32_t fetchdat)
@ -55,6 +60,7 @@ static int opOUT_EAX_imm(uint32_t fetchdat)
check_io_perm(port + 3);
outl(port, EAX);
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, -1, 0,0,0,1, 0);
return 0;
}
@ -63,6 +69,7 @@ static int opIN_AL_DX(uint32_t fetchdat)
check_io_perm(DX);
AL = inb(DX);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opIN_AX_DX(uint32_t fetchdat)
@ -71,6 +78,7 @@ static int opIN_AX_DX(uint32_t fetchdat)
check_io_perm(DX + 1);
AX = inw(DX);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opIN_EAX_DX(uint32_t fetchdat)
@ -81,6 +89,7 @@ static int opIN_EAX_DX(uint32_t fetchdat)
check_io_perm(DX + 3);
EAX = inl(DX);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 1, -1, 0,1,0,0, 0);
return 0;
}
@ -89,6 +98,7 @@ static int opOUT_AL_DX(uint32_t fetchdat)
check_io_perm(DX);
outb(DX, AL);
CLOCK_CYCLES(11);
PREFETCH_RUN(11, 1, -1, 0,0,1,0, 0);
return x86_was_reset;
}
static int opOUT_AX_DX(uint32_t fetchdat)
@ -98,6 +108,7 @@ static int opOUT_AX_DX(uint32_t fetchdat)
check_io_perm(DX + 1);
outw(DX, AX);
CLOCK_CYCLES(11);
PREFETCH_RUN(11, 1, -1, 0,0,1,0, 0);
return 0;
}
static int opOUT_EAX_DX(uint32_t fetchdat)
@ -107,6 +118,6 @@ static int opOUT_EAX_DX(uint32_t fetchdat)
check_io_perm(DX + 2);
check_io_perm(DX + 3);
outl(DX, EAX);
CLOCK_CYCLES(11);
PREFETCH_RUN(11, 1, -1, 0,0,0,1, 0);
return 0;
}

49
src/x86_ops_jump.h
View file

@ -25,8 +25,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 2, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 2, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@ -39,8 +42,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 3, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 3, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@ -53,8 +59,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 5, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 5, -1, 0,0,0,0, 0); \
return 0; \
} \
@ -82,10 +91,12 @@ static int opLOOPNE_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX && !ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -95,10 +106,12 @@ static int opLOOPNE_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX && !ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -109,10 +122,12 @@ static int opLOOPE_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX && ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -122,10 +137,12 @@ static int opLOOPE_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX && ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -136,10 +153,12 @@ static int opLOOP_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX)
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -149,10 +168,12 @@ static int opLOOP_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX)
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@ -167,8 +188,11 @@ static int opJCXZ(uint32_t fetchdat)
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
PREFETCH_RUN(9, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 1;
}
PREFETCH_RUN(5, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opJECXZ(uint32_t fetchdat)
@ -180,8 +204,11 @@ static int opJECXZ(uint32_t fetchdat)
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
PREFETCH_RUN(9, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 1;
}
PREFETCH_RUN(5, 2, -1, 0,0,0,0, 0);
return 0;
}
@ -192,6 +219,8 @@ static int opJMP_r8(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_r16(uint32_t fetchdat)
@ -200,6 +229,8 @@ static int opJMP_r16(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 3, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_r32(uint32_t fetchdat)
@ -208,6 +239,8 @@ static int opJMP_r32(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 5, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@ -219,6 +252,8 @@ static int opJMP_far_a16(uint32_t fetchdat)
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
PREFETCH_RUN(11, 5, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_far_a32(uint32_t fetchdat)
@ -229,6 +264,8 @@ static int opJMP_far_a32(uint32_t fetchdat)
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
PREFETCH_RUN(11, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@ -239,6 +276,8 @@ static int opCALL_r16(uint32_t fetchdat)
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 3, -1, 0,0,1,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opCALL_r32(uint32_t fetchdat)
@ -248,6 +287,8 @@ static int opCALL_r32(uint32_t fetchdat)
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 5, -1, 0,0,0,1, 0);
PREFETCH_FLUSH();
return 0;
}
@ -260,6 +301,8 @@ static int opRET_w(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 1, -1, 1,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRET_l(uint32_t fetchdat)
@ -271,6 +314,8 @@ static int opRET_l(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 1, -1, 0,1,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@ -286,6 +331,8 @@ static int opRET_w_imm(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 5, -1, 1,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRET_l_imm(uint32_t fetchdat)
@ -300,6 +347,8 @@ static int opRET_l_imm(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 5, -1, 0,1,0,0, 0);
PREFETCH_FLUSH();
return 0;
}

57
src/x86_ops_misc.h
View file

@ -2,30 +2,35 @@ static int opCBW(uint32_t fetchdat)
{
AH = (AL & 0x80) ? 0xff : 0;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCWDE(uint32_t fetchdat)
{
EAX = (AX & 0x8000) ? (0xffff0000 | AX) : AX;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCWD(uint32_t fetchdat)
{
DX = (AX & 0x8000) ? 0xFFFF : 0;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCDQ(uint32_t fetchdat)
{
EDX = (EAX & 0x80000000) ? 0xffffffff : 0;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opNOP(uint32_t fetchdat)
{
CLOCK_CYCLES((is486) ? 1 : 3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -33,6 +38,7 @@ static int opSETALC(uint32_t fetchdat)
{
AL = (CF_SET()) ? 0xff : 0;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -54,15 +60,18 @@ static int opF6_a16(uint32_t fetchdat)
setznp8(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x10: /*NOT b*/
seteab(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x18: /*NEG b*/
seteab(0 - dst); if (cpu_state.abrt) return 1;
setsub8(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x20: /*MUL AL,b*/
AX = AL * dst;
@ -70,6 +79,7 @@ static int opF6_a16(uint32_t fetchdat)
if (AH) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(13);
PREFETCH_RUN(13, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x28: /*IMUL AL,b*/
tempws = (int)((int8_t)AL) * (int)((int8_t)dst);
@ -78,6 +88,7 @@ static int opF6_a16(uint32_t fetchdat)
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x30: /*DIV AL,b*/
src16 = AX;
@ -98,6 +109,7 @@ static int opF6_a16(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(is486 ? 16 : 14);
PREFETCH_RUN(is486 ? 16 : 14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x38: /*IDIV AL,b*/
tempws = (int)(int16_t)AX;
@ -120,6 +132,7 @@ static int opF6_a16(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(19);
PREFETCH_RUN(19, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
default:
@ -144,15 +157,18 @@ static int opF6_a32(uint32_t fetchdat)
setznp8(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x10: /*NOT b*/
seteab(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x18: /*NEG b*/
seteab(0 - dst); if (cpu_state.abrt) return 1;
setsub8(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x20: /*MUL AL,b*/
AX = AL * dst;
@ -160,6 +176,7 @@ static int opF6_a32(uint32_t fetchdat)
if (AH) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(13);
PREFETCH_RUN(13, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x28: /*IMUL AL,b*/
tempws = (int)((int8_t)AL) * (int)((int8_t)dst);
@ -168,6 +185,7 @@ static int opF6_a32(uint32_t fetchdat)
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x30: /*DIV AL,b*/
src16 = AX;
@ -188,6 +206,7 @@ static int opF6_a32(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(is486 ? 16 : 14);
PREFETCH_RUN(is486 ? 16 : 14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x38: /*IDIV AL,b*/
tempws = (int)(int16_t)AX;
@ -210,6 +229,7 @@ static int opF6_a32(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(19);
PREFETCH_RUN(19, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
default:
@ -237,15 +257,18 @@ static int opF7_w_a16(uint32_t fetchdat)
setznp16(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x10: /*NOT w*/
seteaw(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x18: /*NEG w*/
seteaw(0 - dst); if (cpu_state.abrt) return 1;
setsub16(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
break;
case 0x20: /*MUL AX,w*/
templ = AX * dst;
@ -255,6 +278,7 @@ static int opF7_w_a16(uint32_t fetchdat)
if (DX) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x28: /*IMUL AX,w*/
templ = (int)((int16_t)AX) * (int)((int16_t)dst);
@ -264,6 +288,7 @@ static int opF7_w_a16(uint32_t fetchdat)
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(22);
PREFETCH_RUN(22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x30: /*DIV AX,w*/
templ = (DX << 16) | AX;
@ -281,6 +306,7 @@ static int opF7_w_a16(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(is486 ? 24 : 22);
PREFETCH_RUN(is486 ? 24 : 22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x38: /*IDIV AX,w*/
tempws = (int)((DX << 16)|AX);
@ -299,6 +325,7 @@ static int opF7_w_a16(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(27);
PREFETCH_RUN(27, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
default:
@ -323,15 +350,18 @@ static int opF7_w_a32(uint32_t fetchdat)
setznp16(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x10: /*NOT w*/
seteaw(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x18: /*NEG w*/
seteaw(0 - dst); if (cpu_state.abrt) return 1;
setsub16(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
break;
case 0x20: /*MUL AX,w*/
templ = AX * dst;
@ -341,6 +371,7 @@ static int opF7_w_a32(uint32_t fetchdat)
if (DX) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x28: /*IMUL AX,w*/
templ = (int)((int16_t)AX) * (int)((int16_t)dst);
@ -350,6 +381,7 @@ static int opF7_w_a32(uint32_t fetchdat)
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(22);
PREFETCH_RUN(22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x30: /*DIV AX,w*/
templ = (DX << 16) | AX;
@ -367,6 +399,7 @@ static int opF7_w_a32(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(is486 ? 24 : 22);
PREFETCH_RUN(is486 ? 24 : 22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x38: /*IDIV AX,w*/
tempws = (int)((DX << 16)|AX);
@ -385,6 +418,7 @@ static int opF7_w_a32(uint32_t fetchdat)
return 1;
}
CLOCK_CYCLES(27);
PREFETCH_RUN(27, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
default:
@ -409,15 +443,18 @@ static int opF7_l_a16(uint32_t fetchdat)
setznp32(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x10: /*NOT l*/
seteal(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
break;
case 0x18: /*NEG l*/
seteal(0 - dst); if (cpu_state.abrt) return 1;
setsub32(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
break;
case 0x20: /*MUL EAX,l*/
temp64 = (uint64_t)EAX * (uint64_t)dst;
@ -427,6 +464,7 @@ static int opF7_l_a16(uint32_t fetchdat)
if (EDX) flags |= (C_FLAG|V_FLAG);
else flags &= ~(C_FLAG|V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x28: /*IMUL EAX,l*/
temp64 = (int64_t)(int32_t)EAX * (int64_t)(int32_t)dst;
@ -436,18 +474,21 @@ static int opF7_l_a16(uint32_t fetchdat)
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(38);
PREFETCH_RUN(38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x30: /*DIV EAX,l*/
if (divl(dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES((is486) ? 40 : 38);
PREFETCH_RUN(is486 ? 40:38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x38: /*IDIV EAX,l*/
if (idivl((int32_t)dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES(43);
PREFETCH_RUN(43, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
default:
@ -471,15 +512,18 @@ static int opF7_l_a32(uint32_t fetchdat)
setznp32(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x10: /*NOT l*/
seteal(~dst); if (cpu_state.abrt) return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
break;
case 0x18: /*NEG l*/
seteal(0 - dst); if (cpu_state.abrt) return 1;
setsub32(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
break;
case 0x20: /*MUL EAX,l*/
temp64 = (uint64_t)EAX * (uint64_t)dst;
@ -489,6 +533,7 @@ static int opF7_l_a32(uint32_t fetchdat)
if (EDX) flags |= (C_FLAG|V_FLAG);
else flags &= ~(C_FLAG|V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x28: /*IMUL EAX,l*/
temp64 = (int64_t)(int32_t)EAX * (int64_t)(int32_t)dst;
@ -498,18 +543,21 @@ static int opF7_l_a32(uint32_t fetchdat)
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(38);
PREFETCH_RUN(38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x30: /*DIV EAX,l*/
if (divl(dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES((is486) ? 40 : 38);
PREFETCH_RUN(is486 ? 40 : 38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x38: /*IDIV EAX,l*/
if (idivl((int32_t)dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES(43);
PREFETCH_RUN(43, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
default:
@ -536,7 +584,8 @@ static int opHLT(uint32_t fetchdat)
CLOCK_CYCLES(5);
CPU_BLOCK_END();
PREFETCH_RUN(100, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -548,6 +597,7 @@ static int opLOCK(uint32_t fetchdat)
cpu_state.pc++;
CLOCK_CYCLES(4);
PREFETCH_PREFIX();
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
@ -569,6 +619,7 @@ static int opBOUND_w_a16(uint32_t fetchdat)
}
CLOCK_CYCLES(is486 ? 7 : 10);
PREFETCH_RUN(is486 ? 7 : 10, 2, rmdat, 2,0,0,0, 0);
return 0;
}
static int opBOUND_w_a32(uint32_t fetchdat)
@ -587,6 +638,7 @@ static int opBOUND_w_a32(uint32_t fetchdat)
}
CLOCK_CYCLES(is486 ? 7 : 10);
PREFETCH_RUN(is486 ? 7 : 10, 2, rmdat, 2,0,0,0, 1);
return 0;
}
@ -606,6 +658,7 @@ static int opBOUND_l_a16(uint32_t fetchdat)
}
CLOCK_CYCLES(is486 ? 7 : 10);
PREFETCH_RUN(is486 ? 7 : 10, 2, rmdat, 1,1,0,0, 0);
return 0;
}
static int opBOUND_l_a32(uint32_t fetchdat)
@ -624,6 +677,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
}
CLOCK_CYCLES(is486 ? 7 : 10);
PREFETCH_RUN(is486 ? 7 : 10, 2, rmdat, 1,1,0,0, 1);
return 0;
}
@ -638,6 +692,7 @@ static int opCLTS(uint32_t fetchdat)
}
cr0 &= ~8;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,0,0,0, 0);
return 0;
}

72
src/x86_ops_mov.h
View file

@ -2,48 +2,56 @@ static int opMOV_AL_imm(uint32_t fetchdat)
{
AL = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_AH_imm(uint32_t fetchdat)
{
AH = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_BL_imm(uint32_t fetchdat)
{
BL = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_BH_imm(uint32_t fetchdat)
{
BH = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_CL_imm(uint32_t fetchdat)
{
CL = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_CH_imm(uint32_t fetchdat)
{
CH = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_DL_imm(uint32_t fetchdat)
{
DL = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_DH_imm(uint32_t fetchdat)
{
DH = getbytef();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
@ -51,48 +59,56 @@ static int opMOV_AX_imm(uint32_t fetchdat)
{
AX = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_BX_imm(uint32_t fetchdat)
{
BX = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_CX_imm(uint32_t fetchdat)
{
CX = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_DX_imm(uint32_t fetchdat)
{
DX = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_SI_imm(uint32_t fetchdat)
{
SI = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_DI_imm(uint32_t fetchdat)
{
DI = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_BP_imm(uint32_t fetchdat)
{
BP = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_SP_imm(uint32_t fetchdat)
{
SP = getwordf();
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
@ -101,6 +117,7 @@ static int opMOV_EAX_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
EAX = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_EBX_imm(uint32_t fetchdat)
@ -108,6 +125,7 @@ static int opMOV_EBX_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
EBX = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_ECX_imm(uint32_t fetchdat)
@ -115,6 +133,7 @@ static int opMOV_ECX_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
ECX = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_EDX_imm(uint32_t fetchdat)
@ -122,6 +141,7 @@ static int opMOV_EDX_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
EDX = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_ESI_imm(uint32_t fetchdat)
@ -129,6 +149,7 @@ static int opMOV_ESI_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
ESI = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_EDI_imm(uint32_t fetchdat)
@ -136,6 +157,7 @@ static int opMOV_EDI_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
EDI = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_EBP_imm(uint32_t fetchdat)
@ -143,6 +165,7 @@ static int opMOV_EBP_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
EBP = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
static int opMOV_ESP_imm(uint32_t fetchdat)
@ -150,6 +173,7 @@ static int opMOV_ESP_imm(uint32_t fetchdat)
uint32_t templ = getlong(); if (cpu_state.abrt) return 1;
ESP = templ;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
@ -161,6 +185,7 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
seteab(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 0);
return cpu_state.abrt;
}
static int opMOV_b_imm_a32(uint32_t fetchdat)
@ -170,6 +195,7 @@ static int opMOV_b_imm_a32(uint32_t fetchdat)
temp = getbyte(); if (cpu_state.abrt) return 1;
seteab(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 1);
return cpu_state.abrt;
}
@ -180,6 +206,7 @@ static int opMOV_w_imm_a16(uint32_t fetchdat)
temp = getword(); if (cpu_state.abrt) return 1;
seteaw(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 4, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 0);
return cpu_state.abrt;
}
static int opMOV_w_imm_a32(uint32_t fetchdat)
@ -189,6 +216,7 @@ static int opMOV_w_imm_a32(uint32_t fetchdat)
temp = getword(); if (cpu_state.abrt) return 1;
seteaw(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 4, rmdat, 0,0,(cpu_mod == 3) ? 1:0,0, 1);
return cpu_state.abrt;
}
static int opMOV_l_imm_a16(uint32_t fetchdat)
@ -198,6 +226,7 @@ static int opMOV_l_imm_a16(uint32_t fetchdat)
temp = getlong(); if (cpu_state.abrt) return 1;
seteal(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 6, rmdat, 0,0,0,(cpu_mod == 3) ? 1:0, 0);
return cpu_state.abrt;
}
static int opMOV_l_imm_a32(uint32_t fetchdat)
@ -207,6 +236,7 @@ static int opMOV_l_imm_a32(uint32_t fetchdat)
temp = getlong(); if (cpu_state.abrt) return 1;
seteal(temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 6, rmdat, 0,0,0,(cpu_mod == 3) ? 1:0, 1);
return cpu_state.abrt;
}
@ -217,6 +247,7 @@ static int opMOV_AL_a16(uint32_t fetchdat)
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AL = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 3, -1, 1,0,0,0, 0);
return 0;
}
static int opMOV_AL_a32(uint32_t fetchdat)
@ -225,6 +256,7 @@ static int opMOV_AL_a32(uint32_t fetchdat)
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AL = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 5, -1, 1,0,0,0, 1);
return 0;
}
static int opMOV_AX_a16(uint32_t fetchdat)
@ -233,6 +265,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 3, -1, 1,0,0,0, 0);
return 0;
}
static int opMOV_AX_a32(uint32_t fetchdat)
@ -241,6 +274,7 @@ static int opMOV_AX_a32(uint32_t fetchdat)
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 5, -1, 1,0,0,0, 1);
return 0;
}
static int opMOV_EAX_a16(uint32_t fetchdat)
@ -249,6 +283,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
EAX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 3, -1, 0,1,0,0, 0);
return 0;
}
static int opMOV_EAX_a32(uint32_t fetchdat)
@ -257,6 +292,7 @@ static int opMOV_EAX_a32(uint32_t fetchdat)
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
EAX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 5, -1, 0,1,0,0, 1);
return 0;
}
@ -265,6 +301,7 @@ static int opMOV_a16_AL(uint32_t fetchdat)
uint16_t addr = getwordf();
writememb(cpu_state.ea_seg->base, addr, AL);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
return cpu_state.abrt;
}
static int opMOV_a32_AL(uint32_t fetchdat)
@ -272,6 +309,7 @@ static int opMOV_a32_AL(uint32_t fetchdat)
uint32_t addr = getlong();
writememb(cpu_state.ea_seg->base, addr, AL);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
return cpu_state.abrt;
}
static int opMOV_a16_AX(uint32_t fetchdat)
@ -279,6 +317,7 @@ static int opMOV_a16_AX(uint32_t fetchdat)
uint16_t addr = getwordf();
writememw(cpu_state.ea_seg->base, addr, AX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
return cpu_state.abrt;
}
static int opMOV_a32_AX(uint32_t fetchdat)
@ -286,6 +325,7 @@ static int opMOV_a32_AX(uint32_t fetchdat)
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
writememw(cpu_state.ea_seg->base, addr, AX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 5, -1, 0,0,1,0, 1);
return cpu_state.abrt;
}
static int opMOV_a16_EAX(uint32_t fetchdat)
@ -293,6 +333,7 @@ static int opMOV_a16_EAX(uint32_t fetchdat)
uint16_t addr = getwordf();
writememl(cpu_state.ea_seg->base, addr, EAX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 3, -1, 0,0,0,1, 0);
return cpu_state.abrt;
}
static int opMOV_a32_EAX(uint32_t fetchdat)
@ -300,6 +341,7 @@ static int opMOV_a32_EAX(uint32_t fetchdat)
uint32_t addr = getlong(); if (cpu_state.abrt) return 1;
writememl(cpu_state.ea_seg->base, addr, EAX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 5, -1, 0,0,0,1, 1);
return cpu_state.abrt;
}
@ -310,6 +352,7 @@ static int opLEA_w_a16(uint32_t fetchdat)
ILLEGAL_ON(cpu_mod == 3);
cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opLEA_w_a32(uint32_t fetchdat)
@ -318,6 +361,7 @@ static int opLEA_w_a32(uint32_t fetchdat)
ILLEGAL_ON(cpu_mod == 3);
cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -327,6 +371,7 @@ static int opLEA_l_a16(uint32_t fetchdat)
ILLEGAL_ON(cpu_mod == 3);
cpu_state.regs[cpu_reg].l = cpu_state.eaaddr & 0xffff;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opLEA_l_a32(uint32_t fetchdat)
@ -335,6 +380,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
ILLEGAL_ON(cpu_mod == 3);
cpu_state.regs[cpu_reg].l = cpu_state.eaaddr;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -346,6 +392,7 @@ static int opXLAT_a16(uint32_t fetchdat)
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AL = temp;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opXLAT_a32(uint32_t fetchdat)
@ -354,6 +401,7 @@ static int opXLAT_a32(uint32_t fetchdat)
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AL = temp;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
return 0;
}
@ -364,12 +412,14 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
{
setr8(cpu_rm, getr8(cpu_reg));
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
seteab(getr8(cpu_reg));
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 0);
}
return cpu_state.abrt;
}
@ -380,12 +430,14 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
{
setr8(cpu_rm, getr8(cpu_reg));
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
seteab(getr8(cpu_reg));
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 1);
}
return cpu_state.abrt;
}
@ -396,12 +448,14 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
{
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
seteaw(cpu_state.regs[cpu_reg].w);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 0);
}
return cpu_state.abrt;
}
@ -412,12 +466,14 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
{
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
seteaw(cpu_state.regs[cpu_reg].w);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,1,0, 1);
}
return cpu_state.abrt;
}
@ -428,12 +484,14 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
{
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
seteal(cpu_state.regs[cpu_reg].l);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,0,1, 0);
}
return cpu_state.abrt;
}
@ -444,12 +502,14 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
{
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
seteal(cpu_state.regs[cpu_reg].l);
CLOCK_CYCLES(is486 ? 1 : 2);
PREFETCH_RUN(2, 2, rmdat, 0,0,0,1, 1);
}
return cpu_state.abrt;
}
@ -461,6 +521,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
{
setr8(cpu_reg, getr8(cpu_rm));
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
@ -469,6 +530,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
temp = geteab(); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 0);
}
return 0;
}
@ -479,6 +541,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
{
setr8(cpu_reg, getr8(cpu_rm));
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
@ -487,6 +550,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
temp = geteab(); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 1);
}
return 0;
}
@ -497,6 +561,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
{
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
@ -505,6 +570,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
temp = geteaw(); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 0);
}
return 0;
}
@ -515,6 +581,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
{
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
@ -523,6 +590,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
temp = geteaw(); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 1,0,0,0, 1);
}
return 0;
}
@ -533,6 +601,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
{
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0);
}
else
{
@ -541,6 +610,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
temp = geteal(); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0,1,0,0, 0);
}
return 0;
}
@ -551,6 +621,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
{
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1);
}
else
{
@ -559,6 +630,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
temp = geteal(); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
PREFETCH_RUN(4, 2, rmdat, 0,1,0,0, 1);
}
return 0;
}

28
src/x86_ops_mov_ctrl.h
View file

@ -33,6 +33,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_CRx_a32(uint32_t fetchdat)
@ -70,6 +71,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -84,6 +86,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_DRx_a32(uint32_t fetchdat)
@ -97,11 +100,14 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
static int opMOV_CRx_r_a16(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
@ -119,6 +125,12 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
if (is486 && !(cr0 & (1 << 30)))
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
cpu_update_waitstates();
break;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
@ -141,10 +153,13 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_CRx_r_a32(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
@ -162,6 +177,12 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
if (is486 && !(cr0 & (1 << 30)))
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
cpu_update_waitstates();
break;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
@ -184,6 +205,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
break;
}
CLOCK_CYCLES(10);
PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -198,6 +220,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_DRx_r_a32(uint32_t fetchdat)
@ -211,6 +234,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
fetch_ea_16(fetchdat);
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -225,6 +249,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_r_TRx_a32(uint32_t fetchdat)
@ -238,6 +263,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}
@ -251,6 +277,7 @@ static int opMOV_TRx_r_a16(uint32_t fetchdat)
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
return 0;
}
static int opMOV_TRx_r_a32(uint32_t fetchdat)
@ -263,6 +290,7 @@ static int opMOV_TRx_r_a32(uint32_t fetchdat)
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
return 0;
}

18
src/x86_ops_mov_seg.h
View file

@ -25,6 +25,7 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_w_seg_a32(uint32_t fetchdat)
@ -54,6 +55,7 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -90,6 +92,7 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_l_seg_a32(uint32_t fetchdat)
@ -125,6 +128,7 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 3, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -165,6 +169,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return cpu_state.abrt;
}
static int opMOV_seg_w_a32(uint32_t fetchdat)
@ -204,6 +209,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
}
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return cpu_state.abrt;
}
@ -220,6 +226,7 @@ static int opLDS_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 0;
}
static int opLDS_w_a32(uint32_t fetchdat)
@ -234,6 +241,7 @@ static int opLDS_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 0;
}
static int opLDS_l_a16(uint32_t fetchdat)
@ -249,6 +257,7 @@ static int opLDS_l_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 0);
return 0;
}
static int opLDS_l_a32(uint32_t fetchdat)
@ -264,6 +273,7 @@ static int opLDS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 1);
return 0;
}
@ -279,6 +289,7 @@ static int opLSS_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 1;
}
static int opLSS_w_a32(uint32_t fetchdat)
@ -293,6 +304,7 @@ static int opLSS_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 1;
}
static int opLSS_l_a16(uint32_t fetchdat)
@ -308,6 +320,7 @@ static int opLSS_l_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0);
return 1;
}
static int opLSS_l_a32(uint32_t fetchdat)
@ -323,6 +336,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1);
return 1;
}
@ -339,6 +353,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 0); \
return 0; \
} \
\
@ -354,6 +369,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 2,0,0,0, 1); \
return 0; \
} \
\
@ -370,6 +386,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 0); \
return 0; \
} \
\
@ -386,6 +403,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
PREFETCH_RUN(7, 2, rmdat, 1,1,0,0, 1); \
return 0; \
}

14
src/x86_ops_movx.h
View file

@ -7,6 +7,7 @@ static int opMOVZX_w_b_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVZX_w_b_a32(uint32_t fetchdat)
@ -18,6 +19,7 @@ static int opMOVZX_w_b_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opMOVZX_l_b_a16(uint32_t fetchdat)
@ -29,6 +31,7 @@ static int opMOVZX_l_b_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVZX_l_b_a32(uint32_t fetchdat)
@ -40,6 +43,7 @@ static int opMOVZX_l_b_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opMOVZX_w_w_a16(uint32_t fetchdat)
@ -51,6 +55,7 @@ static int opMOVZX_w_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVZX_w_w_a32(uint32_t fetchdat)
@ -62,6 +67,7 @@ static int opMOVZX_w_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opMOVZX_l_w_a16(uint32_t fetchdat)
@ -73,6 +79,7 @@ static int opMOVZX_l_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVZX_l_w_a32(uint32_t fetchdat)
@ -84,6 +91,7 @@ static int opMOVZX_l_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
@ -98,6 +106,7 @@ static int opMOVSX_w_b_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w |= 0xff00;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVSX_w_b_a32(uint32_t fetchdat)
@ -111,6 +120,7 @@ static int opMOVSX_w_b_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w |= 0xff00;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opMOVSX_l_b_a16(uint32_t fetchdat)
@ -124,6 +134,7 @@ static int opMOVSX_l_b_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l |= 0xffffff00;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVSX_l_b_a32(uint32_t fetchdat)
@ -137,6 +148,7 @@ static int opMOVSX_l_b_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l |= 0xffffff00;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opMOVSX_l_w_a16(uint32_t fetchdat)
@ -150,6 +162,7 @@ static int opMOVSX_l_w_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l |= 0xffff0000;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opMOVSX_l_w_a32(uint32_t fetchdat)
@ -163,5 +176,6 @@ static int opMOVSX_l_w_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l |= 0xffff0000;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}

12
src/x86_ops_mul.h
View file

@ -15,6 +15,7 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 4, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_iw_a32(uint32_t fetchdat)
@ -34,6 +35,7 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 4, rmdat, 1,0,0,0, 1);
return 0;
}
@ -54,6 +56,7 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
PREFETCH_RUN(25, 6, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_il_a32(uint32_t fetchdat)
@ -73,6 +76,7 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
PREFETCH_RUN(25, 6, rmdat, 0,1,0,0, 1);
return 0;
}
@ -94,6 +98,7 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 3, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_ib_a32(uint32_t fetchdat)
@ -114,6 +119,7 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 3, rmdat, 1,0,0,0, 1);
return 0;
}
@ -134,6 +140,7 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 3, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_ib_a32(uint32_t fetchdat)
@ -153,6 +160,7 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 3, rmdat, 0,1,0,0, 1);
return 0;
}
@ -171,6 +179,7 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_w_a32(uint32_t fetchdat)
@ -186,6 +195,7 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 1);
return 0;
}
@ -202,6 +212,7 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_l_a32(uint32_t fetchdat)
@ -217,6 +228,7 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 1);
return 0;
}

55
src/x86_ops_pmode.h
View file

@ -18,6 +18,7 @@ static int opARPL_a16(uint32_t fetchdat)
flags &= ~Z_FLAG;
CLOCK_CYCLES(is486 ? 9 : 20);
PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 0);
return 0;
}
static int opARPL_a32(uint32_t fetchdat)
@ -40,10 +41,11 @@ static int opARPL_a32(uint32_t fetchdat)
flags &= ~Z_FLAG;
CLOCK_CYCLES(is486 ? 9 : 20);
PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 1);
return 0;
}
#define opLAR(name, fetch_ea, is32) \
#define opLAR(name, fetch_ea, is32, ea32) \
static int opLAR_ ## name(uint32_t fetchdat) \
{ \
int valid; \
@ -84,15 +86,16 @@ static int opARPL_a32(uint32_t fetchdat)
cpl_override = 0; \
} \
CLOCK_CYCLES(11); \
PREFETCH_RUN(11, 2, rmdat, 2,0,0,0, ea32); \
return cpu_state.abrt; \
}
opLAR(w_a16, fetch_ea_16, 0)
opLAR(w_a32, fetch_ea_32, 0)
opLAR(l_a16, fetch_ea_16, 1)
opLAR(l_a32, fetch_ea_32, 1)
opLAR(w_a16, fetch_ea_16, 0, 0)
opLAR(w_a32, fetch_ea_32, 0, 1)
opLAR(l_a16, fetch_ea_16, 1, 0)
opLAR(l_a32, fetch_ea_32, 1, 1)
#define opLSL(name, fetch_ea, is32) \
#define opLSL(name, fetch_ea, is32, ea32) \
static int opLSL_ ## name(uint32_t fetchdat) \
{ \
int valid; \
@ -139,16 +142,17 @@ opLAR(l_a32, fetch_ea_32, 1)
cpl_override = 0; \
} \
CLOCK_CYCLES(10); \
PREFETCH_RUN(10, 2, rmdat, 4,0,0,0, ea32); \
return cpu_state.abrt; \
}
opLSL(w_a16, fetch_ea_16, 0)
opLSL(w_a32, fetch_ea_32, 0)
opLSL(l_a16, fetch_ea_16, 1)
opLSL(l_a32, fetch_ea_32, 1)
opLSL(w_a16, fetch_ea_16, 0, 0)
opLSL(w_a32, fetch_ea_32, 0, 1)
opLSL(l_a16, fetch_ea_16, 1, 0)
opLSL(l_a32, fetch_ea_32, 1, 1)
static int op0F00_common(uint32_t fetchdat)
static int op0F00_common(uint32_t fetchdat, int ea32)
{
int dpl, valid, granularity;
uint32_t addr, base, limit;
@ -161,10 +165,12 @@ static int op0F00_common(uint32_t fetchdat)
case 0x00: /*SLDT*/
seteaw(ldt.seg);
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x08: /*STR*/
seteaw(tr.seg);
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x10: /*LLDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
@ -190,6 +196,7 @@ static int op0F00_common(uint32_t fetchdat)
ldt.base = base;
ldt.seg = sel;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
break;
case 0x18: /*LTR*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
@ -215,6 +222,7 @@ static int op0F00_common(uint32_t fetchdat)
}
tr.base = base;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
break;
case 0x20: /*VERR*/
sel = geteaw(); if (cpu_state.abrt) return 1;
@ -234,6 +242,7 @@ static int op0F00_common(uint32_t fetchdat)
if ((desc & 0x0800) && !(desc & 0x0200)) valid = 0; /*Non-readable code*/
if (valid) flags |= Z_FLAG;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
break;
case 0x28: /*VERW*/
sel = geteaw(); if (cpu_state.abrt) return 1;
@ -251,6 +260,7 @@ static int op0F00_common(uint32_t fetchdat)
if (!(desc & 0x0200)) valid = 0; /*Read-only data*/
if (valid) flags |= Z_FLAG;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
break;
default:
@ -268,7 +278,7 @@ static int op0F00_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
return op0F00_common(fetchdat);
return op0F00_common(fetchdat, 0);
}
static int op0F00_a32(uint32_t fetchdat)
{
@ -276,10 +286,10 @@ static int op0F00_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
return op0F00_common(fetchdat);
return op0F00_common(fetchdat, 1);
}
static int op0F01_common(uint32_t fetchdat, int is32, int is286)
static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
{
uint32_t base;
uint16_t limit, tempw;
@ -293,6 +303,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
base |= 0xff000000;
writememl(easeg, cpu_state.eaaddr + 2, base);
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
break;
case 0x08: /*SIDT*/
seteaw(idt.limit);
@ -301,6 +312,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
base |= 0xff000000;
writememl(easeg, cpu_state.eaaddr + 2, base);
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
break;
case 0x10: /*LGDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
@ -317,6 +329,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
gdt.base = base;
if (!is32) gdt.base &= 0xffffff;
CLOCK_CYCLES(11);
PREFETCH_RUN(11, 2, rmdat, 1,1,0,0, ea32);
break;
case 0x18: /*LIDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
@ -333,12 +346,14 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
idt.base = base;
if (!is32) idt.base &= 0xffffff;
CLOCK_CYCLES(11);
PREFETCH_RUN(11, 2, rmdat, 1,1,0,0, ea32);
break;
case 0x20: /*SMSW*/
if (is486) seteaw(msw);
else seteaw(msw | 0xFF00);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x30: /*LMSW*/
if ((CPL || eflags&VM_FLAG) && (msw&1))
@ -350,6 +365,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
tempw = geteaw(); if (cpu_state.abrt) return 1;
if (msw & 1) tempw |= 1;
msw = tempw;
PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x38: /*INVLPG*/
@ -363,6 +379,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
}
mmu_invalidate(ds + cpu_state.eaaddr);
CLOCK_CYCLES(12);
PREFETCH_RUN(12, 2, rmdat, 0,0,0,0, ea32);
break;
}
@ -379,30 +396,30 @@ static int op0F01_w_a16(uint32_t fetchdat)
{
fetch_ea_16(fetchdat);
return op0F01_common(fetchdat, 0, 0);
return op0F01_common(fetchdat, 0, 0, 0);
}
static int op0F01_w_a32(uint32_t fetchdat)
{
fetch_ea_32(fetchdat);
return op0F01_common(fetchdat, 0, 0);
return op0F01_common(fetchdat, 0, 0, 1);
}
static int op0F01_l_a16(uint32_t fetchdat)
{
fetch_ea_16(fetchdat);
return op0F01_common(fetchdat, 1, 0);
return op0F01_common(fetchdat, 1, 0, 0);
}
static int op0F01_l_a32(uint32_t fetchdat)
{
fetch_ea_32(fetchdat);
return op0F01_common(fetchdat, 1, 0);
return op0F01_common(fetchdat, 1, 0, 1);
}
static int op0F01_286(uint32_t fetchdat)
{
fetch_ea_16(fetchdat);
return op0F01_common(fetchdat, 0, 1);
return op0F01_common(fetchdat, 0, 1, 0);
}

6
src/x86_ops_prefix.h
View file

@ -8,6 +8,7 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
cpu_state.ea_seg = &seg; \
cpu_state.ssegs = 1; \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[fetchdat & 0xff](fetchdat >> 8); \
} \
@ -21,6 +22,7 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
cpu_state.ea_seg = &seg; \
cpu_state.ssegs = 1; \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
} \
@ -34,6 +36,7 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
cpu_state.ea_seg = &seg; \
cpu_state.ssegs = 1; \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
} \
@ -47,6 +50,7 @@ static int op ## name ## _l_a32(uint32_t fetchdat) \
cpu_state.ea_seg = &seg; \
cpu_state.ssegs = 1; \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
}
@ -66,6 +70,7 @@ static int op_66(uint32_t fetchdat) /*Data size select*/
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int op_67(uint32_t fetchdat) /*Address size select*/
@ -76,5 +81,6 @@ static int op_67(uint32_t fetchdat) /*Address size select*/
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}

35
src/x86_ops_ret.h
View file

@ -44,34 +44,56 @@
static int opRETF_a16(uint32_t fetchdat)
{
int cycles_old = cycles;
CPU_BLOCK_END();
RETF_a16(0);
PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRETF_a32(uint32_t fetchdat)
{
int cycles_old = cycles;
CPU_BLOCK_END();
RETF_a32(0);
PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,2,0,0, 1);
PREFETCH_FLUSH();
return 0;
}
static int opRETF_a16_imm(uint32_t fetchdat)
{
int cycles_old = cycles;
uint16_t offset = getwordf();
CPU_BLOCK_END();
RETF_a16(offset);
PREFETCH_RUN(cycles_old-cycles, 3, -1, 2,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRETF_a32_imm(uint32_t fetchdat)
{
int cycles_old = cycles;
uint16_t offset = getwordf();
CPU_BLOCK_END();
RETF_a32(offset);
PREFETCH_RUN(cycles_old-cycles, 3, -1, 0,2,0,0, 1);
PREFETCH_FLUSH();
return 0;
}
static int opIRET_286(uint32_t fetchdat)
{
int cycles_old = cycles;
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@ -107,11 +129,16 @@ static int opIRET_286(uint32_t fetchdat)
flags_extract();
nmi_enable = 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
PREFETCH_FLUSH();
return cpu_state.abrt;
}
static int opIRET(uint32_t fetchdat)
{
int cycles_old = cycles;
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@ -147,11 +174,16 @@ static int opIRET(uint32_t fetchdat)
flags_extract();
nmi_enable = 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
PREFETCH_FLUSH();
return cpu_state.abrt;
}
static int opIRETD(uint32_t fetchdat)
{
int cycles_old = cycles;
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@ -189,6 +221,9 @@ static int opIRETD(uint32_t fetchdat)
flags_extract();
nmi_enable = 1;
CPU_BLOCK_END();
PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,2,0,0, 1);
PREFETCH_FLUSH();
return cpu_state.abrt;
}

73
src/x86_ops_shift.h
View file

@ -1,4 +1,4 @@
#define OP_SHIFT_b(c) \
#define OP_SHIFT_b(c, ea32) \
{ \
uint8_t temp_orig = temp; \
if (!c) return 0; \
@ -17,6 +17,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x08: /*ROR b,CL*/ \
while (c > 0) \
@ -31,6 +32,7 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x10: /*RCL b,CL*/ \
temp2 = flags & C_FLAG; \
@ -47,6 +49,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x18: /*RCR b,CL*/ \
temp2 = flags & C_FLAG; \
@ -63,27 +66,31 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x20: case 0x30: /*SHL b,CL*/ \
seteab(temp << c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x28: /*SHR b,CL*/ \
seteab(temp >> c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x38: /*SAR b,CL*/ \
temp = (int8_t)temp >> c; \
seteab(temp); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
} \
}
#define OP_SHIFT_w(c) \
#define OP_SHIFT_w(c, ea32) \
{ \
uint16_t temp_orig = temp; \
if (!c) return 0; \
@ -102,6 +109,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x08: /*ROR w, c*/ \
while (c > 0) \
@ -116,6 +124,7 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x10: /*RCL w, c*/ \
temp2 = flags & C_FLAG; \
@ -132,6 +141,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x18: /*RCR w, c*/ \
temp2 = flags & C_FLAG; \
@ -148,27 +158,31 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x20: case 0x30: /*SHL w, c*/ \
seteaw(temp << c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x28: /*SHR w, c*/ \
seteaw(temp >> c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x38: /*SAR w, c*/ \
temp = (int16_t)temp >> c; \
seteaw(temp); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
} \
}
#define OP_SHIFT_l(c) \
#define OP_SHIFT_l(c, ea32) \
{ \
uint32_t temp_orig = temp; \
if (!c) return 0; \
@ -187,6 +201,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x08: /*ROR l, c*/ \
while (c > 0) \
@ -201,6 +216,7 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x10: /*RCL l, c*/ \
temp2 = CF_SET(); \
@ -217,6 +233,7 @@
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x18: /*RCR l, c*/ \
temp2 = flags & C_FLAG; \
@ -233,22 +250,26 @@
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x20: case 0x30: /*SHL l, c*/ \
seteal(temp << c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x28: /*SHR l, c*/ \
seteal(temp >> c); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x38: /*SAR l, c*/ \
temp = (int32_t)temp >> c; \
seteal(temp); if (cpu_state.abrt) return 1; \
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
} \
}
@ -261,8 +282,9 @@ static int opC0_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 0);
return 0;
}
static int opC0_a32(uint32_t fetchdat)
@ -273,8 +295,9 @@ static int opC0_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 1);
return 0;
}
static int opC1_w_a16(uint32_t fetchdat)
@ -285,8 +308,9 @@ static int opC1_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 0);
return 0;
}
static int opC1_w_a32(uint32_t fetchdat)
@ -297,8 +321,9 @@ static int opC1_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 1);
return 0;
}
static int opC1_l_a16(uint32_t fetchdat)
@ -309,8 +334,9 @@ static int opC1_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 0);
return 0;
}
static int opC1_l_a32(uint32_t fetchdat)
@ -321,8 +347,9 @@ static int opC1_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
PREFETCH_PREFIX();
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 1);
return 0;
}
@ -334,7 +361,7 @@ static int opD0_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 0);
return 0;
}
static int opD0_a32(uint32_t fetchdat)
@ -345,7 +372,7 @@ static int opD0_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 1);
return 0;
}
static int opD1_w_a16(uint32_t fetchdat)
@ -356,7 +383,7 @@ static int opD1_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 0);
return 0;
}
static int opD1_w_a32(uint32_t fetchdat)
@ -367,7 +394,7 @@ static int opD1_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 1);
return 0;
}
static int opD1_l_a16(uint32_t fetchdat)
@ -378,7 +405,7 @@ static int opD1_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 0);
return 0;
}
static int opD1_l_a32(uint32_t fetchdat)
@ -389,7 +416,7 @@ static int opD1_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 1);
return 0;
}
@ -402,7 +429,7 @@ static int opD2_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = CL & 31;
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 0);
return 0;
}
static int opD2_a32(uint32_t fetchdat)
@ -414,7 +441,7 @@ static int opD2_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = CL & 31;
temp = geteab(); if (cpu_state.abrt) return 1;
OP_SHIFT_b(c);
OP_SHIFT_b(c, 1);
return 0;
}
static int opD3_w_a16(uint32_t fetchdat)
@ -426,7 +453,7 @@ static int opD3_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = CL & 31;
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 0);
return 0;
}
static int opD3_w_a32(uint32_t fetchdat)
@ -438,7 +465,7 @@ static int opD3_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = CL & 31;
temp = geteaw(); if (cpu_state.abrt) return 1;
OP_SHIFT_w(c);
OP_SHIFT_w(c, 1);
return 0;
}
static int opD3_l_a16(uint32_t fetchdat)
@ -450,7 +477,7 @@ static int opD3_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
c = CL & 31;
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 0);
return 0;
}
static int opD3_l_a32(uint32_t fetchdat)
@ -462,7 +489,7 @@ static int opD3_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
c = CL & 31;
temp = geteal(); if (cpu_state.abrt) return 1;
OP_SHIFT_l(c);
OP_SHIFT_l(c, 1);
return 0;
}
@ -529,6 +556,7 @@ static int opD3_l_a32(uint32_t fetchdat)
operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
return 0; \
} \
static int op ## operation ## _CL_a16(uint32_t fetchdat) \
@ -540,6 +568,7 @@ static int opD3_l_a32(uint32_t fetchdat)
operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
return 0; \
} \
static int op ## operation ## _i_a32(uint32_t fetchdat) \
@ -551,6 +580,7 @@ static int opD3_l_a32(uint32_t fetchdat)
operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
return 0; \
} \
static int op ## operation ## _CL_a32(uint32_t fetchdat) \
@ -562,6 +592,7 @@ static int opD3_l_a32(uint32_t fetchdat)
operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
return 0; \
}

36
src/x86_ops_stack.h
View file

@ -3,6 +3,7 @@
{ \
PUSH_W(reg); \
CLOCK_CYCLES((is486) ? 1 : 2); \
PREFETCH_RUN(2, 1, -1, 0,0,1,0, 0); \
return cpu_state.abrt; \
}
@ -11,6 +12,7 @@
{ \
PUSH_L(reg); \
CLOCK_CYCLES((is486) ? 1 : 2); \
PREFETCH_RUN(2, 1, -1, 0,0,0,1, 0); \
return cpu_state.abrt; \
}
@ -19,6 +21,7 @@
{ \
reg = POP_W(); \
CLOCK_CYCLES((is486) ? 1 : 4); \
PREFETCH_RUN(4, 1, -1, 1,0,0,0, 0); \
return cpu_state.abrt; \
}
@ -27,6 +30,7 @@
{ \
reg = POP_L(); \
CLOCK_CYCLES((is486) ? 1 : 4); \
PREFETCH_RUN(4, 1, -1, 0,1,0,0, 0); \
return cpu_state.abrt; \
}
@ -94,6 +98,7 @@ static int opPUSHA_w(uint32_t fetchdat)
if (!cpu_state.abrt) SP -= 16;
}
CLOCK_CYCLES((is486) ? 11 : 18);
PREFETCH_RUN(18, 1, -1, 0,0,8,0, 0);
return cpu_state.abrt;
}
static int opPUSHA_l(uint32_t fetchdat)
@ -123,6 +128,7 @@ static int opPUSHA_l(uint32_t fetchdat)
if (!cpu_state.abrt) SP -= 32;
}
CLOCK_CYCLES((is486) ? 11 : 18);
PREFETCH_RUN(18, 1, -1, 0,0,0,8, 0);
return cpu_state.abrt;
}
@ -151,6 +157,7 @@ static int opPOPA_w(uint32_t fetchdat)
SP += 16;
}
CLOCK_CYCLES((is486) ? 9 : 24);
PREFETCH_RUN(24, 1, -1, 7,0,0,0, 0);
return 0;
}
static int opPOPA_l(uint32_t fetchdat)
@ -178,6 +185,7 @@ static int opPOPA_l(uint32_t fetchdat)
SP += 32;
}
CLOCK_CYCLES((is486) ? 9 : 24);
PREFETCH_RUN(24, 1, -1, 0,7,0,0, 0);
return 0;
}
@ -186,6 +194,7 @@ static int opPUSH_imm_w(uint32_t fetchdat)
uint16_t val = getwordf();
PUSH_W(val);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
return cpu_state.abrt;
}
static int opPUSH_imm_l(uint32_t fetchdat)
@ -193,6 +202,7 @@ static int opPUSH_imm_l(uint32_t fetchdat)
uint32_t val = getlong(); if (cpu_state.abrt) return 1;
PUSH_L(val);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 3, -1, 0,0,0,1, 0);
return cpu_state.abrt;
}
@ -204,6 +214,7 @@ static int opPUSH_imm_bw(uint32_t fetchdat)
PUSH_W(tempw);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 2, -1, 0,0,1,0, 0);
return cpu_state.abrt;
}
static int opPUSH_imm_bl(uint32_t fetchdat)
@ -214,6 +225,7 @@ static int opPUSH_imm_bl(uint32_t fetchdat)
PUSH_L(templ);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 2, -1, 0,0,0,1, 0);
return cpu_state.abrt;
}
@ -233,6 +245,7 @@ static int opPOPW_a16(uint32_t fetchdat)
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 1,0,(cpu_mod == 3) ? 0:1,0, 0);
return cpu_state.abrt;
}
static int opPOPW_a32(uint32_t fetchdat)
@ -251,6 +264,7 @@ static int opPOPW_a32(uint32_t fetchdat)
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 1,0,(cpu_mod == 3) ? 0:1,0, 1);
return cpu_state.abrt;
}
@ -270,6 +284,7 @@ static int opPOPL_a16(uint32_t fetchdat)
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 0,1,0,(cpu_mod == 3) ? 0:1, 0);
return cpu_state.abrt;
}
static int opPOPL_a32(uint32_t fetchdat)
@ -288,6 +303,7 @@ static int opPOPL_a32(uint32_t fetchdat)
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 0,1,0,(cpu_mod == 3) ? 0:1, 1);
return cpu_state.abrt;
}
@ -297,6 +313,7 @@ static int opENTER_w(uint32_t fetchdat)
uint16_t offset = getwordf();
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
int reads = 0, writes = 1, instr_cycles = 0;
PUSH_W(BP); if (cpu_state.abrt) return 1;
frame_ptr = ESP;
@ -313,16 +330,20 @@ static int opENTER_w(uint32_t fetchdat)
PUSH_W(tempw);
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
CLOCK_CYCLES((is486) ? 3 : 4);
reads++; writes++; instr_cycles += (is486) ? 3 : 4;
}
PUSH_W(frame_ptr);
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
CLOCK_CYCLES((is486) ? 3 : 5);
writes++; instr_cycles += (is486) ? 3 : 5;
}
BP = frame_ptr;
if (stack32) ESP -= offset;
else SP -= offset;
CLOCK_CYCLES((is486) ? 14 : 10);
instr_cycles += (is486) ? 14 : 10;
PREFETCH_RUN(instr_cycles, 3, -1, reads,0,writes,0, 0);
return 0;
}
static int opENTER_l(uint32_t fetchdat)
@ -330,6 +351,7 @@ static int opENTER_l(uint32_t fetchdat)
uint16_t offset = getwordf();
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
int reads = 0, writes = 1, instr_cycles = 0;
PUSH_L(EBP); if (cpu_state.abrt) return 1;
frame_ptr = ESP;
@ -346,16 +368,20 @@ static int opENTER_l(uint32_t fetchdat)
PUSH_L(templ);
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
CLOCK_CYCLES((is486) ? 3 : 4);
reads++; writes++; instr_cycles += (is486) ? 3 : 4;
}
PUSH_L(frame_ptr);
if (cpu_state.abrt) { ESP = tempESP; EBP = tempEBP; return 1; }
CLOCK_CYCLES((is486) ? 3 : 5);
writes++; instr_cycles += (is486) ? 3 : 5;
}
EBP = frame_ptr;
if (stack32) ESP -= offset;
else SP -= offset;
CLOCK_CYCLES((is486) ? 14 : 10);
instr_cycles += (is486) ? 14 : 10;
PREFETCH_RUN(instr_cycles, 3, -1, reads,0,writes,0, 0);
return 0;
}
@ -371,6 +397,7 @@ static int opLEAVE_w(uint32_t fetchdat)
BP = temp;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opLEAVE_l(uint32_t fetchdat)
@ -384,6 +411,7 @@ static int opLEAVE_l(uint32_t fetchdat)
EBP = temp;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,1,0,0, 0);
return 0;
}
@ -393,12 +421,14 @@ static int opLEAVE_l(uint32_t fetchdat)
{ \
PUSH_W(seg); \
CLOCK_CYCLES(2); \
PREFETCH_RUN(2, 1, -1, 0,0,1,0, 0); \
return cpu_state.abrt; \
} \
static int opPUSH_ ## seg ## _l(uint32_t fetchdat) \
{ \
PUSH_L(seg); \
CLOCK_CYCLES(2); \
PREFETCH_RUN(2, 1, -1, 0,0,0,1, 0); \
return cpu_state.abrt; \
}
@ -410,6 +440,7 @@ static int opLEAVE_l(uint32_t fetchdat)
temp_seg = POP_W(); if (cpu_state.abrt) return 1; \
loadseg(temp_seg, realseg); if (cpu_state.abrt) ESP = temp_esp; \
CLOCK_CYCLES(is486 ? 3 : 7); \
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0,0,1,0, 0); \
return cpu_state.abrt; \
} \
static int opPOP_ ## seg ## _l(uint32_t fetchdat) \
@ -419,6 +450,7 @@ static int opLEAVE_l(uint32_t fetchdat)
temp_seg = POP_L(); if (cpu_state.abrt) return 1; \
loadseg(temp_seg & 0xffff, realseg); if (cpu_state.abrt) ESP = temp_esp; \
CLOCK_CYCLES(is486 ? 3 : 7); \
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0,0,1,0, 0); \
return cpu_state.abrt; \
}
@ -443,7 +475,8 @@ static int opPOP_SS_w(uint32_t fetchdat)
temp_seg = POP_W(); if (cpu_state.abrt) return 1;
loadseg(temp_seg, &_ss); if (cpu_state.abrt) { ESP = temp_esp; return 1; }
CLOCK_CYCLES(is486 ? 3 : 7);
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0,0,1,0, 0);
cpu_state.oldpc = cpu_state.pc;
cpu_state.op32 = use32;
cpu_state.ssegs = 0;
@ -462,6 +495,7 @@ static int opPOP_SS_l(uint32_t fetchdat)
temp_seg = POP_L(); if (cpu_state.abrt) return 1;
loadseg(temp_seg & 0xffff, &_ss); if (cpu_state.abrt) { ESP = temp_esp; return 1; }
CLOCK_CYCLES(is486 ? 3 : 7);
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0,0,1,0, 0);
cpu_state.oldpc = cpu_state.pc;
cpu_state.op32 = use32;

42
src/x86_ops_string.h
View file

@ -5,6 +5,7 @@ static int opMOVSB_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opMOVSB_a32(uint32_t fetchdat)
@ -14,6 +15,7 @@ static int opMOVSB_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -24,6 +26,7 @@ static int opMOVSW_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opMOVSW_a32(uint32_t fetchdat)
@ -33,6 +36,7 @@ static int opMOVSW_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -43,6 +47,7 @@ static int opMOVSL_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 0);
return 0;
}
static int opMOVSL_a32(uint32_t fetchdat)
@ -52,6 +57,7 @@ static int opMOVSL_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 1);
return 0;
}
@ -64,6 +70,7 @@ static int opCMPSB_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
return 0;
}
static int opCMPSB_a32(uint32_t fetchdat)
@ -74,6 +81,7 @@ static int opCMPSB_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
return 0;
}
@ -85,6 +93,7 @@ static int opCMPSW_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
return 0;
}
static int opCMPSW_a32(uint32_t fetchdat)
@ -95,6 +104,7 @@ static int opCMPSW_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
return 0;
}
@ -106,6 +116,7 @@ static int opCMPSL_a16(uint32_t fetchdat)
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 0);
return 0;
}
static int opCMPSL_a32(uint32_t fetchdat)
@ -116,6 +127,7 @@ static int opCMPSL_a32(uint32_t fetchdat)
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 1);
return 0;
}
@ -125,6 +137,7 @@ static int opSTOSB_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return 0;
}
static int opSTOSB_a32(uint32_t fetchdat)
@ -133,6 +146,7 @@ static int opSTOSB_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
return 0;
}
@ -142,6 +156,7 @@ static int opSTOSW_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return 0;
}
static int opSTOSW_a32(uint32_t fetchdat)
@ -150,6 +165,7 @@ static int opSTOSW_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
return 0;
}
@ -159,6 +175,7 @@ static int opSTOSL_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
return 0;
}
static int opSTOSL_a32(uint32_t fetchdat)
@ -167,6 +184,7 @@ static int opSTOSL_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 1);
return 0;
}
@ -178,6 +196,7 @@ static int opLODSB_a16(uint32_t fetchdat)
if (flags & D_FLAG) SI--;
else SI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opLODSB_a32(uint32_t fetchdat)
@ -187,6 +206,7 @@ static int opLODSB_a32(uint32_t fetchdat)
if (flags & D_FLAG) ESI--;
else ESI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
return 0;
}
@ -197,6 +217,7 @@ static int opLODSW_a16(uint32_t fetchdat)
if (flags & D_FLAG) SI -= 2;
else SI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opLODSW_a32(uint32_t fetchdat)
@ -206,6 +227,7 @@ static int opLODSW_a32(uint32_t fetchdat)
if (flags & D_FLAG) ESI -= 2;
else ESI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
return 0;
}
@ -216,6 +238,7 @@ static int opLODSL_a16(uint32_t fetchdat)
if (flags & D_FLAG) SI -= 4;
else SI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
return 0;
}
static int opLODSL_a32(uint32_t fetchdat)
@ -225,6 +248,7 @@ static int opLODSL_a32(uint32_t fetchdat)
if (flags & D_FLAG) ESI -= 4;
else ESI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 1);
return 0;
}
@ -236,6 +260,7 @@ static int opSCASB_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opSCASB_a32(uint32_t fetchdat)
@ -245,6 +270,7 @@ static int opSCASB_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
return 0;
}
@ -255,6 +281,7 @@ static int opSCASW_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
return 0;
}
static int opSCASW_a32(uint32_t fetchdat)
@ -264,6 +291,7 @@ static int opSCASW_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
return 0;
}
@ -274,6 +302,7 @@ static int opSCASL_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 0);
return 0;
}
static int opSCASL_a32(uint32_t fetchdat)
@ -283,6 +312,7 @@ static int opSCASL_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 1);
return 0;
}
@ -295,6 +325,7 @@ static int opINSB_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opINSB_a32(uint32_t fetchdat)
@ -306,6 +337,7 @@ static int opINSB_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -319,6 +351,7 @@ static int opINSW_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opINSW_a32(uint32_t fetchdat)
@ -331,6 +364,7 @@ static int opINSW_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -346,6 +380,7 @@ static int opINSL_a16(uint32_t fetchdat)
if (flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 0);
return 0;
}
static int opINSL_a32(uint32_t fetchdat)
@ -360,6 +395,7 @@ static int opINSL_a32(uint32_t fetchdat)
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 1);
return 0;
}
@ -371,6 +407,7 @@ static int opOUTSB_a16(uint32_t fetchdat)
else SI++;
outb(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opOUTSB_a32(uint32_t fetchdat)
@ -381,6 +418,7 @@ static int opOUTSB_a32(uint32_t fetchdat)
else ESI++;
outb(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -393,6 +431,7 @@ static int opOUTSW_a16(uint32_t fetchdat)
else SI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 0);
return 0;
}
static int opOUTSW_a32(uint32_t fetchdat)
@ -404,6 +443,7 @@ static int opOUTSW_a32(uint32_t fetchdat)
else ESI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 1);
return 0;
}
@ -418,6 +458,7 @@ static int opOUTSL_a16(uint32_t fetchdat)
else SI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 0,1,0,1, 0);
return 0;
}
static int opOUTSL_a32(uint32_t fetchdat)
@ -431,5 +472,6 @@ static int opOUTSL_a32(uint32_t fetchdat)
else ESI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 0,1,0,1, 1);
return 0;
}

21
src/x86_ops_xchg.h
View file

@ -6,6 +6,7 @@ static int opXCHG_b_a16(uint32_t fetchdat)
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opXCHG_b_a32(uint32_t fetchdat)
@ -16,6 +17,7 @@ static int opXCHG_b_a32(uint32_t fetchdat)
seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -27,6 +29,7 @@ static int opXCHG_w_a16(uint32_t fetchdat)
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
static int opXCHG_w_a32(uint32_t fetchdat)
@ -37,6 +40,7 @@ static int opXCHG_w_a32(uint32_t fetchdat)
seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@ -48,6 +52,7 @@ static int opXCHG_l_a16(uint32_t fetchdat)
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
static int opXCHG_l_a32(uint32_t fetchdat)
@ -58,6 +63,7 @@ static int opXCHG_l_a32(uint32_t fetchdat)
seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
PREFETCH_RUN((cpu_mod == 3) ? 3 : 5, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}
@ -68,6 +74,7 @@ static int opXCHG_AX_BX(uint32_t fetchdat)
AX = BX;
BX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_CX(uint32_t fetchdat)
@ -76,6 +83,7 @@ static int opXCHG_AX_CX(uint32_t fetchdat)
AX = CX;
CX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_DX(uint32_t fetchdat)
@ -84,6 +92,7 @@ static int opXCHG_AX_DX(uint32_t fetchdat)
AX = DX;
DX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_SI(uint32_t fetchdat)
@ -92,6 +101,7 @@ static int opXCHG_AX_SI(uint32_t fetchdat)
AX = SI;
SI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_DI(uint32_t fetchdat)
@ -100,6 +110,7 @@ static int opXCHG_AX_DI(uint32_t fetchdat)
AX = DI;
DI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_BP(uint32_t fetchdat)
@ -108,6 +119,7 @@ static int opXCHG_AX_BP(uint32_t fetchdat)
AX = BP;
BP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_AX_SP(uint32_t fetchdat)
@ -116,6 +128,7 @@ static int opXCHG_AX_SP(uint32_t fetchdat)
AX = SP;
SP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -125,6 +138,7 @@ static int opXCHG_EAX_EBX(uint32_t fetchdat)
EAX = EBX;
EBX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ECX(uint32_t fetchdat)
@ -133,6 +147,7 @@ static int opXCHG_EAX_ECX(uint32_t fetchdat)
EAX = ECX;
ECX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EDX(uint32_t fetchdat)
@ -141,6 +156,7 @@ static int opXCHG_EAX_EDX(uint32_t fetchdat)
EAX = EDX;
EDX = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ESI(uint32_t fetchdat)
@ -149,6 +165,7 @@ static int opXCHG_EAX_ESI(uint32_t fetchdat)
EAX = ESI;
ESI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EDI(uint32_t fetchdat)
@ -157,6 +174,7 @@ static int opXCHG_EAX_EDI(uint32_t fetchdat)
EAX = EDI;
EDI = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_EBP(uint32_t fetchdat)
@ -165,6 +183,7 @@ static int opXCHG_EAX_EBP(uint32_t fetchdat)
EAX = EBP;
EBP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opXCHG_EAX_ESP(uint32_t fetchdat)
@ -173,6 +192,7 @@ static int opXCHG_EAX_ESP(uint32_t fetchdat)
EAX = ESP;
ESP = temp;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
}
@ -182,6 +202,7 @@ static int opXCHG_EAX_ESP(uint32_t fetchdat)
{ \
reg = (reg >> 24) | ((reg >> 8) & 0xff00) | ((reg << 8) & 0xff0000) | ((reg << 24) & 0xff000000); \
CLOCK_CYCLES(1); \
PREFETCH_RUN(1, 1, -1, 0,0,0,0, 0); \
return 0; \
}