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Move flags and eflags variables into cpu_struct.

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This commit is contained in:
SarahW 2018-11-28 09:42:04 +00:00
commit a4d3aa1912
25 changed files with 1013 additions and 958 deletions
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18
src/386.c
View file

@ -250,13 +250,13 @@ dontprint=0;
if (!cpu_state.abrt)
{
trap = flags & T_FLAG;
trap = cpu_state.flags & T_FLAG;
opcode = fetchdat & 0xFF;
fetchdat >>= 8;
if (output == 3)
{
pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X\n",CS,cs,cpu_state.pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask);
pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X\n",CS,cs,cpu_state.pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,cpu_state.flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask);
}
cpu_state.pc++;
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
@ -312,13 +312,13 @@ dontprint=0;
}
else
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (1 << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
@ -336,7 +336,7 @@ dontprint=0;
nmi = 0;
}
}
else if ((flags&I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
{
temp=picinterrupt();
if (temp!=0xFF)
@ -352,13 +352,13 @@ dontprint=0;
}
else
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (temp << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));

10
src/386_common.h
View file

@ -15,7 +15,7 @@ extern uint16_t ea_rseg;
int checkio(int port);
#define check_io_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
#define check_io_perm(port) if (!IOPLp || (cpu_state.eflags&VM_FLAG)) \
{ \
int tempi = checkio(port); \
if (cpu_state.abrt) return 1; \
@ -26,7 +26,7 @@ int checkio(int port);
} \
}
#define checkio_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
#define checkio_perm(port) if (!IOPLp || (cpu_state.eflags&VM_FLAG)) \
{ \
int tempi = checkio(port); \
if (cpu_state.abrt) break; \
@ -58,14 +58,14 @@ int checkio(int port);
} while (0)
#define CHECK_READ(seg, low, high) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || ((msw & 1) && !(eflags & VM_FLAG) && (((seg)->access & 10) == 8))) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && (((seg)->access & 10) == 8))) \
{ \
x86gpf("Limit check", 0); \
return 1; \
}
#define CHECK_WRITE(seg, low, high) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || !((seg)->access & 2) || ((msw & 1) && !(eflags & VM_FLAG) && ((seg)->access & 8))) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || !((seg)->access & 2) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && ((seg)->access & 8))) \
{ \
x86gpf("Limit check", 0); \
return 1; \
@ -79,7 +79,7 @@ int checkio(int port);
}
#define NOTRM if (!(msw & 1) || (eflags & VM_FLAG))\
#define NOTRM if (!(msw & 1) || (cpu_state.eflags & VM_FLAG))\
{ \
x86_int(6); \
return 1; \

44
src/386_dynarec.c
View file

@ -217,21 +217,21 @@ void x86_int(int num)
{
if (stack32)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-2,cpu_state.flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
@ -264,21 +264,21 @@ void x86_int_sw(int num)
{
if (stack32)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-2,cpu_state.flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
@ -303,13 +303,13 @@ int x86_int_sw_rm(int num)
if (cpu_state.abrt) return 1;
writememw(ss,((SP-2)&0xFFFF),flags); if (cpu_state.abrt) {pclog("abrt5\n"); return 1; }
writememw(ss,((SP-2)&0xFFFF),cpu_state.flags); if (cpu_state.abrt) {pclog("abrt5\n"); return 1; }
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc); if (cpu_state.abrt) {pclog("abrt6\n"); return 1; }
SP-=6;
eflags &= ~VIF_FLAG;
flags &= ~T_FLAG;
cpu_state.eflags &= ~VIF_FLAG;
cpu_state.flags &= ~T_FLAG;
cpu_state.pc = new_pc;
loadcs(new_cs);
oxpc=cpu_state.pc;
@ -507,7 +507,7 @@ int dontprint=0;
#include "386_ops.h"
#define CACHE_ON() (!(cr0 & (1 << 30)) /*&& (cr0 & 1)*/ && !(flags & T_FLAG))
#define CACHE_ON() (!(cr0 & (1 << 30)) /*&& (cr0 & 1)*/ && !(cpu_state.flags & T_FLAG))
//#define CACHE_ON() 0
static int cycles_main = 0;
@ -560,7 +560,7 @@ void exec386_dynarec(int cycs)
// fatal("Dead with cache off\n");
if (!cpu_state.abrt)
{
trap = flags & T_FLAG;
trap = cpu_state.flags & T_FLAG;
opcode = fetchdat & 0xFF;
fetchdat >>= 8;
@ -720,7 +720,7 @@ inrecomp=0;
// fatal("Dead\n");
if (!cpu_state.abrt)
{
trap = flags & T_FLAG;
trap = cpu_state.flags & T_FLAG;
opcode = fetchdat & 0xFF;
fetchdat >>= 8;
@ -800,7 +800,7 @@ inrecomp=0;
if (!cpu_state.abrt)
{
trap = flags & T_FLAG;
trap = cpu_state.flags & T_FLAG;
opcode = fetchdat & 0xFF;
fetchdat >>= 8;
@ -892,13 +892,13 @@ inrecomp=0;
}
else
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (1 << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
@ -916,7 +916,7 @@ inrecomp=0;
nmi = 0;
}
}
else if ((flags&I_FLAG) && pic_intpending)
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
{
temp=picinterrupt();
if (temp!=0xFF)
@ -930,13 +930,13 @@ inrecomp=0;
}
else
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr=temp<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));

877
src/808x.c
View file

File diff suppressed because it is too large Load diff

4
src/codegen.c
View file

@ -48,7 +48,7 @@ void codegen_generate_reset()
void codegen_check_seg_read(codeblock_t *block, ir_data_t *ir, x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (eflags & VM_FLAG))
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
@ -65,7 +65,7 @@ void codegen_check_seg_read(codeblock_t *block, ir_data_t *ir, x86seg *seg)
void codegen_check_seg_write(codeblock_t *block, ir_data_t *ir, x86seg *seg)
{
/*Segments always valid in real/V86 mode*/
if (!(cr0 & 1) || (eflags & VM_FLAG))
if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
return;
/*CS and SS must always be valid*/
if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)

8
src/codegen_ops_jump.c
View file

@ -159,7 +159,7 @@ uint32_t ropRET_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32
uint32_t ropRETF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
if ((msw&1) && !(eflags&VM_FLAG))
if ((msw&1) && !(cpu_state.eflags&VM_FLAG))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
@ -184,7 +184,7 @@ uint32_t ropRETF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
}
uint32_t ropRETF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
if ((msw&1) && !(eflags&VM_FLAG))
if ((msw&1) && !(cpu_state.eflags&VM_FLAG))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
@ -212,7 +212,7 @@ uint32_t ropRETF_imm_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
{
uint16_t offset;
if ((msw&1) && !(eflags&VM_FLAG))
if ((msw&1) && !(cpu_state.eflags&VM_FLAG))
return 0;
offset = fastreadw(cs + op_pc);
@ -240,7 +240,7 @@ uint32_t ropRETF_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
{
uint16_t offset;
if ((msw&1) && !(eflags&VM_FLAG))
if ((msw&1) && !(cpu_state.eflags&VM_FLAG))
return 0;
offset = fastreadw(cs + op_pc);

5
src/ibm.h
View file

@ -188,6 +188,8 @@ struct
uint32_t l;
uint16_t w;
} CR0;
uint16_t flags, eflags;
} cpu_state;
#define cycles cpu_state._cycles
@ -214,7 +216,6 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128);
#define cpu_state_offset(MEMBER) ((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)
uint16_t flags,eflags;
uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
extern int ins,output;
@ -273,7 +274,7 @@ uint32_t dr[8];
#define CR4_PVI (1 << 1)
#define CR4_PSE (1 << 4)
#define IOPL ((flags>>12)&3)
#define IOPL ((cpu_state.flags >> 12) & 3)
#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
//#define IOPLp 1

2
src/x86.h
View file

@ -55,7 +55,7 @@ extern uint16_t *mod1add[2][8];
extern uint32_t *mod1seg[8];
#define IRQTEST ((flags&I_FLAG) && (pic.pend&~pic.mask) && !noint)
#define IRQTEST ((cpu_state.flags & I_FLAG) && (pic.pend&~pic.mask) && !noint)
extern int cgate32;

114
src/x86_flags.h
View file

@ -66,7 +66,7 @@ static inline int ZF_SET()
return !cpu_state.flags_res;
case FLAGS_UNKNOWN:
return flags & Z_FLAG;
return cpu_state.flags & Z_FLAG;
}
return 0;
}
@ -106,7 +106,7 @@ static inline int NF_SET()
return cpu_state.flags_res & 0x80000000;
case FLAGS_UNKNOWN:
return flags & N_FLAG;
return cpu_state.flags & N_FLAG;
}
return 0;
}
@ -142,7 +142,7 @@ static inline int PF_SET()
return znptable8[cpu_state.flags_res & 0xff] & P_FLAG;
case FLAGS_UNKNOWN:
return flags & P_FLAG;
return cpu_state.flags & P_FLAG;
}
return 0;
}
@ -194,7 +194,7 @@ static inline int VF_SET()
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80000000));
case FLAGS_UNKNOWN:
return flags & V_FLAG;
return cpu_state.flags & V_FLAG;
}
return 0;
}
@ -234,7 +234,7 @@ static inline int AF_SET()
return ((cpu_state.flags_op1 & 0xF) - (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_UNKNOWN:
return flags & A_FLAG;
return cpu_state.flags & A_FLAG;
}
return 0;
}
@ -286,7 +286,7 @@ static inline int CF_SET()
case FLAGS_INC16:
case FLAGS_INC32:
case FLAGS_UNKNOWN:
return flags & C_FLAG;
return cpu_state.flags & C_FLAG;
}
return 0;
}
@ -309,7 +309,7 @@ static inline void flags_rebuild()
if (ZF_SET()) tempf |= Z_FLAG;
if (NF_SET()) tempf |= N_FLAG;
if (VF_SET()) tempf |= V_FLAG;
flags = (flags & ~0x8d5) | tempf;
cpu_state.flags = (cpu_state.flags & ~0x8d5) | tempf;
cpu_state.flags_op = FLAGS_UNKNOWN;
}
}
@ -324,9 +324,9 @@ static inline void flags_rebuild_c()
if (cpu_state.flags_op != FLAGS_UNKNOWN)
{
if (CF_SET())
flags |= C_FLAG;
cpu_state.flags |= C_FLAG;
else
flags &= ~C_FLAG;
cpu_state.flags &= ~C_FLAG;
}
}
@ -447,67 +447,85 @@ static inline void setsub32nc(uint32_t a, uint32_t b)
static inline void setadc8(uint8_t a, uint8_t b)
{
uint16_t c=(uint16_t)a+(uint16_t)b+tempc;
uint16_t c = (uint16_t)a + (uint16_t)b + tempc;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable8[c&0xFF];
if (c&0x100) flags|=C_FLAG;
if (!((a^b)&0x80)&&((a^c)&0x80)) flags|=V_FLAG;
if (((a&0xF)+(b&0xF))&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= znptable8[c&0xFF];
if (c & 0x100)
cpu_state.flags |= C_FLAG;
if (!((a ^ b) & 0x80) && ((a ^ c) & 0x80))
cpu_state.flags |= V_FLAG;
if (((a & 0xF) + (b & 0xF)) & 0x10)
cpu_state.flags |= A_FLAG;
}
static inline void setadc16(uint16_t a, uint16_t b)
{
uint32_t c=(uint32_t)a+(uint32_t)b+tempc;
uint32_t c = (uint32_t)a + (uint32_t)b + tempc;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable16[c&0xFFFF];
if (c&0x10000) flags|=C_FLAG;
if (!((a^b)&0x8000)&&((a^c)&0x8000)) flags|=V_FLAG;
if (((a&0xF)+(b&0xF))&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= znptable16[c&0xFFFF];
if (c & 0x10000)
cpu_state.flags |= C_FLAG;
if (!((a ^ b) & 0x8000) && ((a ^ c) & 0x8000))
cpu_state.flags |= V_FLAG;
if (((a & 0xF) + (b & 0xF)) & 0x10)
cpu_state.flags |= A_FLAG;
}
static inline void setsbc8(uint8_t a, uint8_t b)
{
uint16_t c=(uint16_t)a-(((uint16_t)b)+tempc);
uint16_t c = (uint16_t)a - (((uint16_t)b) + tempc);
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable8[c&0xFF];
if (c&0x100) flags|=C_FLAG;
if ((a^b)&(a^c)&0x80) flags|=V_FLAG;
if (((a&0xF)-(b&0xF))&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= znptable8[c&0xFF];
if (c & 0x100)
cpu_state.flags |= C_FLAG;
if ((a ^ b) & (a ^ c) & 0x80)
cpu_state.flags |= V_FLAG;
if (((a & 0xF) - (b & 0xF)) & 0x10)
cpu_state.flags |= A_FLAG;
}
static inline void setsbc16(uint16_t a, uint16_t b)
{
uint32_t c=(uint32_t)a-(((uint32_t)b)+tempc);
uint32_t c = (uint32_t)a - (((uint32_t)b) + tempc);
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=(znptable16[c&0xFFFF]&~4);
flags|=(znptable8[c&0xFF]&4);
if (c&0x10000) flags|=C_FLAG;
if ((a^b)&(a^c)&0x8000) flags|=V_FLAG;
if (((a&0xF)-(b&0xF))&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= (znptable16[c&0xFFFF] & ~4);
cpu_state.flags |= (znptable8[c&0xFF] & 4);
if (c & 0x10000)
cpu_state.flags |= C_FLAG;
if ((a ^ b) & (a ^ c) & 0x8000)
cpu_state.flags |= V_FLAG;
if (((a & 0xF) - (b & 0xF)) & 0x10)
cpu_state.flags |= A_FLAG;
}
static inline void setadc32(uint32_t a, uint32_t b)
{
uint32_t c=(uint32_t)a+(uint32_t)b+tempc;
uint32_t c = (uint32_t)a + (uint32_t)b + tempc;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=((c&0x80000000)?N_FLAG:((!c)?Z_FLAG:0));
flags|=(znptable8[c&0xFF]&P_FLAG);
if ((c<a) || (c==a && tempc)) flags|=C_FLAG;
if (!((a^b)&0x80000000)&&((a^c)&0x80000000)) flags|=V_FLAG;
if (((a&0xF)+(b&0xF)+tempc)&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= ((c & 0x80000000) ? N_FLAG : ((!c) ? Z_FLAG : 0));
cpu_state.flags |= (znptable8[c&0xFF] & P_FLAG);
if ((c < a) || (c == a && tempc))
cpu_state.flags |= C_FLAG;
if (!((a ^ b) & 0x80000000) && ((a ^ c) & 0x80000000))
cpu_state.flags |= V_FLAG;
if (((a & 0xF) + (b & 0xF) + tempc) & 0x10)
cpu_state.flags |= A_FLAG;
}
static inline void setsbc32(uint32_t a, uint32_t b)
{
uint32_t c=(uint32_t)a-(((uint32_t)b)+tempc);
uint32_t c = (uint32_t)a - (((uint32_t)b) + tempc);
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=((c&0x80000000)?N_FLAG:((!c)?Z_FLAG:0));
flags|=(znptable8[c&0xFF]&P_FLAG);
if ((c>a) || (c==a && tempc)) flags|=C_FLAG;
if ((a^b)&(a^c)&0x80000000) flags|=V_FLAG;
if (((a&0xF)-((b&0xF)+tempc))&0x10) flags|=A_FLAG;
cpu_state.flags &= ~0x8D5;
cpu_state.flags |= ((c & 0x80000000) ? N_FLAG : ((!c) ? Z_FLAG : 0));
cpu_state.flags |= (znptable8[c&0xFF] & P_FLAG);
if ((c > a) || (c == a && tempc))
cpu_state.flags |= C_FLAG;
if ((a ^ b) & (a ^ c) & 0x80000000)
cpu_state.flags |= V_FLAG;
if (((a & 0xF) - ((b & 0xF) + tempc)) & 0x10)
cpu_state.flags |= A_FLAG;
}

8
src/x86_ops_atomic.h
View file

@ -141,9 +141,9 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
if (cpu_state.abrt) return 0;
flags_rebuild();
if (temp == temp2 && temp_hi == temp2_hi)
flags |= Z_FLAG;
cpu_state.flags |= Z_FLAG;
else
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
cycles -= (cpu_mod == 3) ? 6 : 10;
return 0;
}
@ -173,9 +173,9 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
if (cpu_state.abrt) return 0;
flags_rebuild();
if (temp == temp2 && temp_hi == temp2_hi)
flags |= Z_FLAG;
cpu_state.flags |= Z_FLAG;
else
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
cycles -= (cpu_mod == 3) ? 6 : 10;
return 0;
}

40
src/x86_ops_bcd.h
View file

@ -1,14 +1,14 @@
static int opAAA(uint32_t fetchdat)
{
flags_rebuild();
if ((flags & A_FLAG) || ((AL & 0xF) > 9))
if ((cpu_state.flags & A_FLAG) || ((AL & 0xF) > 9))
{
AL += 6;
AH++;
flags |= (A_FLAG | C_FLAG);
cpu_state.flags |= (A_FLAG | C_FLAG);
}
else
flags &= ~(A_FLAG | C_FLAG);
cpu_state.flags &= ~(A_FLAG | C_FLAG);
AL &= 0xF;
CLOCK_CYCLES(is486 ? 3 : 4);
PREFETCH_RUN(is486 ? 3 : 4, 1, -1, 0,0,0,0, 0);
@ -42,14 +42,14 @@ static int opAAM(uint32_t fetchdat)
static int opAAS(uint32_t fetchdat)
{
flags_rebuild();
if ((flags & A_FLAG) || ((AL & 0xF) > 9))
if ((cpu_state.flags & A_FLAG) || ((AL & 0xF) > 9))
{
AL -= 6;
AH--;
flags |= (A_FLAG | C_FLAG);
cpu_state.flags |= (A_FLAG | C_FLAG);
}
else
flags &= ~(A_FLAG | C_FLAG);
cpu_state.flags &= ~(A_FLAG | C_FLAG);
AL &= 0xF;
CLOCK_CYCLES(is486 ? 3 : 4);
PREFETCH_RUN(is486 ? 3 : 4, 1, -1, 0,0,0,0, 0);
@ -61,23 +61,23 @@ static int opDAA(uint32_t fetchdat)
uint16_t tempw;
flags_rebuild();
if ((flags & A_FLAG) || ((AL & 0xf) > 9))
if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9))
{
int tempi = ((uint16_t)AL) + 6;
AL += 6;
flags |= A_FLAG;
if (tempi & 0x100) flags |= C_FLAG;
cpu_state.flags |= A_FLAG;
if (tempi & 0x100) cpu_state.flags |= C_FLAG;
}
if ((flags & C_FLAG) || (AL > 0x9f))
if ((cpu_state.flags & C_FLAG) || (AL > 0x9f))
{
AL += 0x60;
flags |= C_FLAG;
cpu_state.flags |= C_FLAG;
}
tempw = flags & (C_FLAG | A_FLAG);
tempw = cpu_state.flags & (C_FLAG | A_FLAG);
setznp8(AL);
flags_rebuild();
flags |= tempw;
cpu_state.flags |= tempw;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,0, 0);
@ -89,23 +89,23 @@ static int opDAS(uint32_t fetchdat)
uint16_t tempw;
flags_rebuild();
if ((flags & A_FLAG) || ((AL & 0xf) > 9))
if ((cpu_state.flags & A_FLAG) || ((AL & 0xf) > 9))
{
int tempi = ((uint16_t)AL) - 6;
AL -= 6;
flags |= A_FLAG;
if (tempi & 0x100) flags |= C_FLAG;
cpu_state.flags |= A_FLAG;
if (tempi & 0x100) cpu_state.flags |= C_FLAG;
}
if ((flags & C_FLAG) || (AL > 0x9f))
if ((cpu_state.flags & C_FLAG) || (AL > 0x9f))
{
AL -= 0x60;
flags |= C_FLAG;
cpu_state.flags |= C_FLAG;
}
tempw = flags & (C_FLAG | A_FLAG);
tempw = cpu_state.flags & (C_FLAG | A_FLAG);
setznp8(AL);
flags_rebuild();
flags |= tempw;
cpu_state.flags |= tempw;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,0, 0);

64
src/x86_ops_bit.h
View file

@ -7,8 +7,8 @@ static int opBT_w_r_a16(uint32_t fetchdat)
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
temp = geteaw(); if (cpu_state.abrt) return 1;
flags_rebuild();
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 1,0,0,0, 0);
@ -23,8 +23,8 @@ static int opBT_w_r_a32(uint32_t fetchdat)
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
temp = geteaw(); if (cpu_state.abrt) return 1;
flags_rebuild();
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 1,0,0,0, 1);
@ -39,8 +39,8 @@ static int opBT_l_r_a16(uint32_t fetchdat)
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
temp = geteal(); if (cpu_state.abrt) return 1;
flags_rebuild();
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 0,1,0,0, 0);
@ -55,8 +55,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
temp = geteal(); if (cpu_state.abrt) return 1;
flags_rebuild();
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 2, rmdat, 0,1,0,0, 1);
@ -78,8 +78,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
else flags &= ~C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1,0,1,0, 0); \
@ -99,8 +99,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
else flags &= ~C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1,0,1,0, 1); \
@ -120,8 +120,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
seteal(temp); if (cpu_state.abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
else flags &= ~C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0,1,0,1, 0); \
@ -141,8 +141,8 @@ static int opBT_l_r_a32(uint32_t fetchdat)
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
seteal(temp); if (cpu_state.abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
else flags &= ~C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0,1,0,1, 1); \
@ -169,8 +169,8 @@ static int opBA_w_a16(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x20: /*BT w,imm*/
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
@ -191,8 +191,8 @@ static int opBA_w_a16(uint32_t fetchdat)
break;
}
seteaw(temp); if (cpu_state.abrt) return 1;
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
@ -213,8 +213,8 @@ static int opBA_w_a32(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x20: /*BT w,imm*/
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
@ -235,8 +235,8 @@ static int opBA_w_a32(uint32_t fetchdat)
break;
}
seteaw(temp); if (cpu_state.abrt) return 1;
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
@ -258,8 +258,8 @@ static int opBA_l_a16(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x20: /*BT w,imm*/
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
@ -280,8 +280,8 @@ static int opBA_l_a16(uint32_t fetchdat)
break;
}
seteal(temp); if (cpu_state.abrt) return 1;
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
@ -302,8 +302,8 @@ static int opBA_l_a32(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x20: /*BT w,imm*/
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
@ -324,8 +324,8 @@ static int opBA_l_a32(uint32_t fetchdat)
break;
}
seteal(temp); if (cpu_state.abrt) return 1;
if (tempc) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (tempc) cpu_state.flags |= C_FLAG;
else cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(6);
PREFETCH_RUN(6, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;

4
src/x86_ops_bitscan.h
View file

@ -4,7 +4,7 @@
if (temp) \
{ \
int c; \
flags &= ~Z_FLAG; \
cpu_state.flags &= ~Z_FLAG; \
for (c = start; c != end; c += dir) \
{ \
CLOCK_CYCLES(time); \
@ -17,7 +17,7 @@
} \
} \
else \
flags |= Z_FLAG;
cpu_state.flags |= Z_FLAG;
static int opBSF_w_a16(uint32_t fetchdat)
{

94
src/x86_ops_flag.h
View file

@ -1,7 +1,7 @@
static int opCMC(uint32_t fetchdat)
{
flags_rebuild();
flags ^= C_FLAG;
cpu_state.flags ^= C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
@ -11,14 +11,14 @@ static int opCMC(uint32_t fetchdat)
static int opCLC(uint32_t fetchdat)
{
flags_rebuild();
flags &= ~C_FLAG;
cpu_state.flags &= ~C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opCLD(uint32_t fetchdat)
{
flags &= ~D_FLAG;
cpu_state.flags &= ~D_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
@ -27,10 +27,10 @@ static int opCLI(uint32_t fetchdat)
{
if (!IOPLp)
{
if ((!(eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((eflags & VM_FLAG) && (cr4 & CR4_VME)))
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME)))
{
eflags &= ~VIF_FLAG;
cpu_state.eflags &= ~VIF_FLAG;
}
else
{
@ -39,7 +39,7 @@ static int opCLI(uint32_t fetchdat)
}
}
else
flags &= ~I_FLAG;
cpu_state.flags &= ~I_FLAG;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
@ -49,14 +49,14 @@ static int opCLI(uint32_t fetchdat)
static int opSTC(uint32_t fetchdat)
{
flags_rebuild();
flags |= C_FLAG;
cpu_state.flags |= C_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
}
static int opSTD(uint32_t fetchdat)
{
flags |= D_FLAG;
cpu_state.flags |= D_FLAG;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;
@ -65,16 +65,16 @@ static int opSTI(uint32_t fetchdat)
{
if (!IOPLp)
{
if ((!(eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((eflags & VM_FLAG) && (cr4 & CR4_VME)))
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME)))
{
if (eflags & VIP_FLAG)
if (cpu_state.eflags & VIP_FLAG)
{
x86gpf(NULL,0);
return 1;
}
else
eflags |= VIF_FLAG;
cpu_state.eflags |= VIF_FLAG;
}
else
{
@ -83,7 +83,7 @@ static int opSTI(uint32_t fetchdat)
}
}
else
flags |= I_FLAG;
cpu_state.flags |= I_FLAG;
CPU_BLOCK_END();
@ -95,7 +95,7 @@ static int opSTI(uint32_t fetchdat)
static int opSAHF(uint32_t fetchdat)
{
flags_rebuild();
flags = (flags & 0xff00) | (AH & 0xd5) | 2;
cpu_state.flags = (cpu_state.flags & 0xff00) | (AH & 0xd5) | 2;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
@ -106,7 +106,7 @@ static int opSAHF(uint32_t fetchdat)
static int opLAHF(uint32_t fetchdat)
{
flags_rebuild();
AH = flags & 0xff;
AH = cpu_state.flags & 0xff;
CLOCK_CYCLES(3);
PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
return 0;
@ -114,15 +114,15 @@ static int opLAHF(uint32_t fetchdat)
static int opPUSHF(uint32_t fetchdat)
{
if ((eflags & VM_FLAG) && (IOPL < 3))
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
{
if (cr4 & CR4_VME)
{
uint16_t temp;
flags_rebuild();
temp = (flags & ~I_FLAG) | 0x3000;
if (eflags & VIF_FLAG)
temp = (cpu_state.flags & ~I_FLAG) | 0x3000;
if (cpu_state.eflags & VIF_FLAG)
temp |= I_FLAG;
PUSH_W(temp);
}
@ -135,7 +135,7 @@ static int opPUSHF(uint32_t fetchdat)
else
{
flags_rebuild();
PUSH_W(flags);
PUSH_W(cpu_state.flags);
}
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
@ -144,16 +144,16 @@ static int opPUSHF(uint32_t fetchdat)
static int opPUSHFD(uint32_t fetchdat)
{
uint16_t tempw;
if ((eflags & VM_FLAG) && (IOPL < 3))
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
{
x86gpf(NULL, 0);
return 1;
}
if (cpu_CR4_mask & CR4_VME) tempw = eflags & 0x3c;
else if (CPUID) tempw = eflags & 0x24;
else tempw = eflags & 4;
if (cpu_CR4_mask & CR4_VME) tempw = cpu_state.eflags & 0x3c;
else if (CPUID) tempw = cpu_state.eflags & 0x24;
else tempw = cpu_state.eflags & 4;
flags_rebuild();
PUSH_L(flags | (tempw << 16));
PUSH_L(cpu_state.flags | (tempw << 16));
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
return cpu_state.abrt;
@ -163,7 +163,7 @@ static int opPOPF_286(uint32_t fetchdat)
{
uint16_t tempw;
if ((eflags & VM_FLAG) && (IOPL < 3))
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
{
x86gpf(NULL, 0);
return 1;
@ -171,10 +171,10 @@ static int opPOPF_286(uint32_t fetchdat)
tempw = POP_W(); if (cpu_state.abrt) return 1;
if (!(msw & 1)) flags = (flags & 0x7000) | (tempw & 0x0fd5) | 2;
else if (!(CPL)) flags = (tempw & 0x7fd5) | 2;
else if (IOPLp) flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
else flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
if (!(msw & 1)) cpu_state.flags = (cpu_state.flags & 0x7000) | (tempw & 0x0fd5) | 2;
else if (!(CPL)) cpu_state.flags = (tempw & 0x7fd5) | 2;
else if (IOPLp) cpu_state.flags = (cpu_state.flags & 0x3000) | (tempw & 0x4fd5) | 2;
else cpu_state.flags = (cpu_state.flags & 0x3200) | (tempw & 0x4dd5) | 2;
flags_extract();
CLOCK_CYCLES(5);
@ -188,7 +188,7 @@ static int opPOPF(uint32_t fetchdat)
{
uint16_t tempw;
if ((eflags & VM_FLAG) && (IOPL < 3))
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
{
if (cr4 & CR4_VME)
{
@ -201,17 +201,17 @@ static int opPOPF(uint32_t fetchdat)
return 1;
}
if ((tempw & T_FLAG) || ((tempw & I_FLAG) && (eflags & VIP_FLAG)))
if ((tempw & T_FLAG) || ((tempw & I_FLAG) && (cpu_state.eflags & VIP_FLAG)))
{
ESP = old_esp;
x86gpf(NULL, 0);
return 1;
}
if (tempw & I_FLAG)
eflags |= VIF_FLAG;
cpu_state.eflags |= VIF_FLAG;
else
eflags &= ~VIF_FLAG;
flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
cpu_state.eflags &= ~VIF_FLAG;
cpu_state.flags = (cpu_state.flags & 0x3200) | (tempw & 0x4dd5) | 2;
}
else
{
@ -226,11 +226,11 @@ static int opPOPF(uint32_t fetchdat)
return 1;
if (!(CPL) || !(msw & 1))
flags = (tempw & 0x7fd5) | 2;
cpu_state.flags = (tempw & 0x7fd5) | 2;
else if (IOPLp)
flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
cpu_state.flags = (cpu_state.flags & 0x3000) | (tempw & 0x4fd5) | 2;
else
flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
cpu_state.flags = (cpu_state.flags & 0x3200) | (tempw & 0x4dd5) | 2;
}
flags_extract();
@ -245,7 +245,7 @@ static int opPOPFD(uint32_t fetchdat)
{
uint32_t templ;
if ((eflags & VM_FLAG) && (IOPL < 3))
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
{
x86gpf(NULL, 0);
return 1;
@ -253,16 +253,16 @@ static int opPOPFD(uint32_t fetchdat)
templ = POP_L(); if (cpu_state.abrt) return 1;
if (!(CPL) || !(msw & 1)) flags = (templ & 0x7fd5) | 2;
else if (IOPLp) flags = (flags & 0x3000) | (templ & 0x4fd5) | 2;
else flags = (flags & 0x3200) | (templ & 0x4dd5) | 2;
if (!(CPL) || !(msw & 1)) cpu_state.flags = (templ & 0x7fd5) | 2;
else if (IOPLp) cpu_state.flags = (cpu_state.flags & 0x3000) | (templ & 0x4fd5) | 2;
else cpu_state.flags = (cpu_state.flags & 0x3200) | (templ & 0x4dd5) | 2;
templ &= is486 ? 0x3c0000 : 0;
templ |= ((eflags&3) << 16);
if (cpu_CR4_mask & CR4_VME) eflags = (templ >> 16) & 0x3f;
else if (CPUID) eflags = (templ >> 16) & 0x27;
else if (is486) eflags = (templ >> 16) & 7;
else eflags = (templ >> 16) & 3;
templ |= ((cpu_state.eflags&3) << 16);
if (cpu_CR4_mask & CR4_VME) cpu_state.eflags = (templ >> 16) & 0x3f;
else if (CPUID) cpu_state.eflags = (templ >> 16) & 0x27;
else if (is486) cpu_state.eflags = (templ >> 16) & 7;
else cpu_state.eflags = (templ >> 16) & 3;
flags_extract();

8
src/x86_ops_int.h
View file

@ -1,7 +1,7 @@
static int opINT3(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;
@ -15,7 +15,7 @@ static int opINT3(uint32_t fetchdat)
static int opINT1(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;
@ -31,7 +31,7 @@ static int opINT(uint32_t fetchdat)
int cycles_old = cycles; UNUSED(cycles_old);
uint8_t temp = getbytef();
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
if (cr4 & CR4_VME)
{
@ -104,7 +104,7 @@ static int opINTO(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;

76
src/x86_ops_misc.h
View file

@ -86,8 +86,8 @@ static int opF6_a16(uint32_t fetchdat)
case 0x20: /*MUL AL,b*/
AX = AL * dst;
flags_rebuild();
if (AH) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (AH) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(13);
PREFETCH_RUN(13, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
@ -95,8 +95,8 @@ static int opF6_a16(uint32_t fetchdat)
tempws = (int)((int8_t)AL) * (int)((int8_t)dst);
AX = tempws & 0xffff;
flags_rebuild();
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
@ -110,8 +110,8 @@ static int opF6_a16(uint32_t fetchdat)
if (!cpu_iscyrix)
{
flags_rebuild();
flags |= 0x8D5; /*Not a Cyrix*/
flags &= ~1;
cpu_state.flags |= 0x8D5; /*Not a Cyrix*/
cpu_state.flags &= ~1;
}
}
else
@ -133,8 +133,8 @@ static int opF6_a16(uint32_t fetchdat)
if (!cpu_iscyrix)
{
flags_rebuild();
flags|=0x8D5; /*Not a Cyrix*/
flags &= ~1;
cpu_state.flags|=0x8D5; /*Not a Cyrix*/
cpu_state.flags &= ~1;
}
}
else
@ -192,8 +192,8 @@ static int opF6_a32(uint32_t fetchdat)
case 0x20: /*MUL AL,b*/
AX = AL * dst;
flags_rebuild();
if (AH) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (AH) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(13);
PREFETCH_RUN(13, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
@ -201,8 +201,8 @@ static int opF6_a32(uint32_t fetchdat)
tempws = (int)((int8_t)AL) * (int)((int8_t)dst);
AX = tempws & 0xffff;
flags_rebuild();
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int16_t)AX >> 7) != 0 && ((int16_t)AX >> 7) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
@ -216,8 +216,8 @@ static int opF6_a32(uint32_t fetchdat)
if (!cpu_iscyrix)
{
flags_rebuild();
flags |= 0x8D5; /*Not a Cyrix*/
flags &= ~1;
cpu_state.flags |= 0x8D5; /*Not a Cyrix*/
cpu_state.flags &= ~1;
}
}
else
@ -239,8 +239,8 @@ static int opF6_a32(uint32_t fetchdat)
if (!cpu_iscyrix)
{
flags_rebuild();
flags|=0x8D5; /*Not a Cyrix*/
flags &= ~1;
cpu_state.flags |= 0x8D5; /*Not a Cyrix*/
cpu_state.flags &= ~1;
}
}
else
@ -303,8 +303,8 @@ static int opF7_w_a16(uint32_t fetchdat)
AX = templ & 0xFFFF;
DX = templ >> 16;
flags_rebuild();
if (DX) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (DX) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
@ -313,8 +313,8 @@ static int opF7_w_a16(uint32_t fetchdat)
AX = templ & 0xFFFF;
DX = templ >> 16;
flags_rebuild();
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(22);
PREFETCH_RUN(22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
@ -403,8 +403,8 @@ static int opF7_w_a32(uint32_t fetchdat)
AX = templ & 0xFFFF;
DX = templ >> 16;
flags_rebuild();
if (DX) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (DX) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
@ -413,8 +413,8 @@ static int opF7_w_a32(uint32_t fetchdat)
AX = templ & 0xFFFF;
DX = templ >> 16;
flags_rebuild();
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int32_t)templ >> 15) != 0 && ((int32_t)templ >> 15) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(22);
PREFETCH_RUN(22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
@ -503,8 +503,8 @@ static int opF7_l_a16(uint32_t fetchdat)
EAX = temp64 & 0xffffffff;
EDX = temp64 >> 32;
flags_rebuild();
if (EDX) flags |= (C_FLAG|V_FLAG);
else flags &= ~(C_FLAG|V_FLAG);
if (EDX) cpu_state.flags |= (C_FLAG|V_FLAG);
else cpu_state.flags &= ~(C_FLAG|V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
@ -513,8 +513,8 @@ static int opF7_l_a16(uint32_t fetchdat)
EAX = temp64 & 0xffffffff;
EDX = temp64 >> 32;
flags_rebuild();
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(38);
PREFETCH_RUN(38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
@ -579,8 +579,8 @@ static int opF7_l_a32(uint32_t fetchdat)
EAX = temp64 & 0xffffffff;
EDX = temp64 >> 32;
flags_rebuild();
if (EDX) flags |= (C_FLAG|V_FLAG);
else flags &= ~(C_FLAG|V_FLAG);
if (EDX) cpu_state.flags |= (C_FLAG|V_FLAG);
else cpu_state.flags &= ~(C_FLAG|V_FLAG);
CLOCK_CYCLES(21);
PREFETCH_RUN(21, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
@ -589,8 +589,8 @@ static int opF7_l_a32(uint32_t fetchdat)
EAX = temp64 & 0xffffffff;
EDX = temp64 >> 32;
flags_rebuild();
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) flags |= (C_FLAG | V_FLAG);
else flags &= ~(C_FLAG | V_FLAG);
if (((int64_t)temp64 >> 31) != 0 && ((int64_t)temp64 >> 31) != -1) cpu_state.flags |= (C_FLAG | V_FLAG);
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(38);
PREFETCH_RUN(38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
@ -619,12 +619,12 @@ static int opF7_l_a32(uint32_t fetchdat)
static int opHLT(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
x86gpf(NULL,0);
return 1;
}
if (!((flags&I_FLAG) && pic_intpending))
if (!((cpu_state.flags & I_FLAG) && pic_intpending))
{
CLOCK_CYCLES_ALWAYS(100);
cpu_state.pc--;
@ -739,7 +739,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
static int opCLTS(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't CLTS\n");
x86gpf(NULL,0);
@ -782,7 +782,7 @@ static int opLOADALL(uint32_t fetchdat)
return 1;
}
msw = (msw & 1) | readmemw(0, 0x806);
flags = (readmemw(0, 0x818) & 0xffd5) | 2;
cpu_state.flags = (readmemw(0, 0x818) & 0xffd5) | 2;
flags_extract();
tr.seg = readmemw(0, 0x816);
cpu_state.pc = readmemw(0, 0x81A);
@ -890,8 +890,8 @@ static int opLOADALL386(uint32_t fetchdat)
uint32_t la_addr = es + EDI;
cr0 = readmeml(0, la_addr);
flags = readmemw(0, la_addr + 4);
eflags = readmemw(0, la_addr + 6);
cpu_state.flags = readmemw(0, la_addr + 4);
cpu_state.eflags = readmemw(0, la_addr + 6);
flags_extract();
cpu_state.pc = readmeml(0, la_addr + 8);
EDI = readmeml(0, la_addr + 0xC);

24
src/x86_ops_mov_ctrl.h
View file

@ -1,6 +1,6 @@
static int opMOV_r_CRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from CRx\n");
x86gpf(NULL, 0);
@ -38,7 +38,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
}
static int opMOV_r_CRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from CRx\n");
x86gpf(NULL, 0);
@ -77,7 +77,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
static int opMOV_r_DRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from DRx\n");
x86gpf(NULL, 0);
@ -91,7 +91,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
}
static int opMOV_r_DRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from DRx\n");
x86gpf(NULL, 0);
@ -108,7 +108,7 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
x86gpf(NULL,0);
@ -164,7 +164,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
{
uint32_t old_cr0 = cr0;
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
x86gpf(NULL,0);
@ -219,7 +219,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
static int opMOV_DRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load DRx\n");
x86gpf(NULL, 0);
@ -233,7 +233,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
}
static int opMOV_DRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load DRx\n");
x86gpf(NULL, 0);
@ -248,7 +248,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
static int opMOV_r_TRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from TRx\n");
x86gpf(NULL, 0);
@ -262,7 +262,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
}
static int opMOV_r_TRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from TRx\n");
x86gpf(NULL, 0);
@ -277,7 +277,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
static int opMOV_TRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load TRx\n");
x86gpf(NULL, 0);
@ -290,7 +290,7 @@ static int opMOV_TRx_r_a16(uint32_t fetchdat)
}
static int opMOV_TRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load TRx\n");
x86gpf(NULL, 0);

48
src/x86_ops_mul.h
View file

@ -12,8 +12,8 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
templ = ((int)tempw) * ((int)tempw2);
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
@ -34,8 +34,8 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
templ = ((int)tempw) * ((int)tempw2);
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
@ -57,8 +57,8 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
temp64 = ((int64_t)templ) * ((int64_t)templ2);
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
@ -79,8 +79,8 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
temp64 = ((int64_t)templ) * ((int64_t)templ2);
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
@ -103,8 +103,8 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
templ = ((int)tempw) * ((int)tempw2);
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
@ -126,8 +126,8 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
templ = ((int)tempw) * ((int)tempw2);
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
@ -150,8 +150,8 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
temp64 = ((int64_t)templ)*((int64_t)templ2);
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
@ -173,8 +173,8 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
temp64 = ((int64_t)templ)*((int64_t)templ2);
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
@ -196,8 +196,8 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 0);
@ -215,8 +215,8 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((templ >> 15) != 0 && (templ >> 15) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 1);
@ -235,8 +235,8 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 0);
@ -254,8 +254,8 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) cpu_state.flags |= C_FLAG | V_FLAG;
else cpu_state.flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 1);

38
src/x86_ops_pmode.h
View file

@ -14,10 +14,10 @@ static int opARPL_a16(uint32_t fetchdat)
{
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
seteaw(temp_seg); if (cpu_state.abrt) return 1;
flags |= Z_FLAG;
cpu_state.flags |= Z_FLAG;
}
else
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
CLOCK_CYCLES(is486 ? 9 : 20);
PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 0);
@ -39,10 +39,10 @@ static int opARPL_a32(uint32_t fetchdat)
{
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
seteaw(temp_seg); if (cpu_state.abrt) return 1;
flags |= Z_FLAG;
cpu_state.flags |= Z_FLAG;
}
else
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
CLOCK_CYCLES(is486 ? 9 : 20);
PREFETCH_RUN(is486 ? 9 : 20, 2, rmdat, 1,0,1,0, 1);
@ -63,7 +63,7 @@ static int opARPL_a32(uint32_t fetchdat)
sel = geteaw(); if (cpu_state.abrt) return 1; \
\
flags_rebuild(); \
if (!(sel & 0xfffc)) { flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
if (!(sel & 0xfffc)) { cpu_state.flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
if (valid) \
{ \
@ -71,7 +71,7 @@ static int opARPL_a32(uint32_t fetchdat)
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
cpl_override = 0; if (cpu_state.abrt) return 1; \
} \
flags &= ~Z_FLAG; \
cpu_state.flags &= ~Z_FLAG; \
if ((desc & 0x1f00) == 0x000) valid = 0; \
if ((desc & 0x1f00) == 0x800) valid = 0; \
if ((desc & 0x1f00) == 0xa00) valid = 0; \
@ -83,7 +83,7 @@ static int opARPL_a32(uint32_t fetchdat)
} \
if (valid) \
{ \
flags |= Z_FLAG; \
cpu_state.flags |= Z_FLAG; \
cpl_override = 1; \
if (is32) \
cpu_state.regs[cpu_reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
@ -114,7 +114,7 @@ opLAR(l_a32, fetch_ea_32, 1, 1)
\
sel = geteaw(); if (cpu_state.abrt) return 1; \
flags_rebuild(); \
flags &= ~Z_FLAG; \
cpu_state.flags &= ~Z_FLAG; \
if (!(sel & 0xfffc)) return 0; /*Null selector*/ \
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
if (valid) \
@ -133,7 +133,7 @@ opLAR(l_a32, fetch_ea_32, 1, 1)
} \
if (valid) \
{ \
flags |= Z_FLAG; \
cpu_state.flags |= Z_FLAG; \
cpl_override = 1; \
if (is32) \
{ \
@ -185,7 +185,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
PREFETCH_RUN(4, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x10: /*LLDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
{
pclog("Invalid LLDT!\n");
x86gpf(NULL,0);
@ -213,7 +213,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 0:1,2,0,0, ea32);
break;
case 0x18: /*LTR*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
{
pclog("Invalid LTR!\n");
x86gpf(NULL,0);
@ -248,7 +248,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
SEG_CHECK_READ(cpu_state.ea_seg);
sel = geteaw(); if (cpu_state.abrt) return 1;
flags_rebuild();
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
if (!(sel & 0xfffc)) return 0; /*Null selector*/
cpl_override = 1;
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
@ -261,7 +261,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
if (dpl < CPL || dpl < (sel & 3)) valid = 0;
}
if ((desc & 0x0800) && !(desc & 0x0200)) valid = 0; /*Non-readable code*/
if (valid) flags |= Z_FLAG;
if (valid) cpu_state.flags |= Z_FLAG;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
break;
@ -270,7 +270,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
SEG_CHECK_READ(cpu_state.ea_seg);
sel = geteaw(); if (cpu_state.abrt) return 1;
flags_rebuild();
flags &= ~Z_FLAG;
cpu_state.flags &= ~Z_FLAG;
if (!(sel & 0xfffc)) return 0; /*Null selector*/
cpl_override = 1;
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
@ -281,7 +281,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
if (dpl < CPL || dpl < (sel & 3)) valid = 0;
if (desc & 0x0800) valid = 0; /*Code*/
if (!(desc & 0x0200)) valid = 0; /*Read-only data*/
if (valid) flags |= Z_FLAG;
if (valid) cpu_state.flags |= Z_FLAG;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1:2,0,0,0, ea32);
break;
@ -342,7 +342,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
PREFETCH_RUN(7, 2, rmdat, 0,0,1,1, ea32);
break;
case 0x10: /*LGDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
{
pclog("Invalid LGDT!\n");
x86gpf(NULL,0);
@ -361,7 +361,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
PREFETCH_RUN(11, 2, rmdat, 1,1,0,0, ea32);
break;
case 0x18: /*LIDT*/
if ((CPL || eflags&VM_FLAG) && (cr0&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
{
pclog("Invalid LIDT!\n");
x86gpf(NULL,0);
@ -390,7 +390,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;
case 0x30: /*LMSW*/
if ((CPL || eflags&VM_FLAG) && (msw&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (msw&1))
{
pclog("LMSW - ring not zero!\n");
x86gpf(NULL, 0);
@ -417,7 +417,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
case 0x38: /*INVLPG*/
if (is486)
{
if ((CPL || eflags&VM_FLAG) && (cr0&1))
if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1))
{
pclog("Invalid INVLPG!\n");
x86gpf(NULL, 0);

84
src/x86_ops_rep.h
View file

@ -14,8 +14,8 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
temp = inb(DX); \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
@ -43,8 +43,8 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
temp = inw(DX); \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
@ -74,8 +74,8 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
temp = inl(DX); \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
@ -101,8 +101,8 @@ static int opREP_OUTSB_ ## size(uint32_t fetchdat)
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
outb(DX, temp); \
if (flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
if (cpu_state.flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
@ -128,8 +128,8 @@ static int opREP_OUTSW_ ## size(uint32_t fetchdat)
check_io_perm(DX); \
check_io_perm(DX+1); \
outw(DX, temp); \
if (flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
@ -157,8 +157,8 @@ static int opREP_OUTSL_ ## size(uint32_t fetchdat)
check_io_perm(DX+2); \
check_io_perm(DX+3); \
outl(DX, temp); \
if (flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
@ -192,8 +192,8 @@ static int opREP_MOVSB_ ## size(uint32_t fetchdat)
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
@ -230,8 +230,8 @@ static int opREP_MOVSW_ ## size(uint32_t fetchdat)
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
@ -268,8 +268,8 @@ static int opREP_MOVSL_ ## size(uint32_t fetchdat)
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
@ -301,8 +301,8 @@ static int opREP_STOSB_ ## size(uint32_t fetchdat)
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
writememb(es, DEST_REG, AL); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
@ -331,8 +331,8 @@ static int opREP_STOSW_ ## size(uint32_t fetchdat)
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG+1); \
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
@ -361,8 +361,8 @@ static int opREP_STOSL_ ## size(uint32_t fetchdat)
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG+3); \
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
@ -391,8 +391,8 @@ static int opREP_LODSB_ ## size(uint32_t fetchdat)
while (CNT_REG > 0) \
{ \
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
if (cpu_state.flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
@ -420,8 +420,8 @@ static int opREP_LODSW_ ## size(uint32_t fetchdat)
while (CNT_REG > 0) \
{ \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
@ -449,8 +449,8 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
while (CNT_REG > 0) \
{ \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
@ -483,8 +483,8 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
@ -513,8 +513,8 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
@ -543,8 +543,8 @@ static int opREP_CMPSL_ ## size(uint32_t fetchdat)
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
@ -575,8 +575,8 @@ static int opREP_SCASB_ ## size(uint32_t fetchdat)
uint8_t temp = readmemb(es, DEST_REG); if (cpu_state.abrt) break;\
setsub8(AL, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
@ -608,8 +608,8 @@ static int opREP_SCASW_ ## size(uint32_t fetchdat)
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
setsub16(AX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
@ -641,8 +641,8 @@ static int opREP_SCASL_ ## size(uint32_t fetchdat)
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
setsub32(EAX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \

34
src/x86_ops_ret.h
View file

@ -1,5 +1,5 @@
#define RETF_a16(stack_offset) \
if ((msw&1) && !(eflags&VM_FLAG)) \
if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
{ \
pmoderetf(0, stack_offset); \
return 1; \
@ -21,7 +21,7 @@
cycles -= timing_retf_rm;
#define RETF_a32(stack_offset) \
if ((msw&1) && !(eflags&VM_FLAG)) \
if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
{ \
pmoderetf(1, stack_offset); \
return 1; \
@ -94,7 +94,7 @@ static int opIRET_286(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;
@ -113,14 +113,14 @@ static int opIRET_286(uint32_t fetchdat)
{
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (flags & 0x7000) | (readmemw(ss, ESP + 4) & 0xffd5) | 2;
cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
}
else
{
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (flags & 0x7000) | (readmemw(ss, ((SP + 4) & 0xffff)) & 0x0fd5) | 2;
cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ((SP + 4) & 0xffff)) & 0x0fd5) | 2;
SP += 6;
}
loadcs(new_cs);
@ -139,7 +139,7 @@ static int opIRET(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
if (cr4 & CR4_VME)
{
@ -151,17 +151,17 @@ static int opIRET(uint32_t fetchdat)
if (cpu_state.abrt)
return 1;
if ((new_flags & T_FLAG) || ((new_flags & I_FLAG) && (eflags & VIP_FLAG)))
if ((new_flags & T_FLAG) || ((new_flags & I_FLAG) && (cpu_state.eflags & VIP_FLAG)))
{
x86gpf(NULL, 0);
return 1;
}
SP += 6;
if (new_flags & I_FLAG)
eflags |= VIF_FLAG;
cpu_state.eflags |= VIF_FLAG;
else
eflags &= ~VIF_FLAG;
flags = (flags & 0x3300) | (new_flags & 0x4cd5) | 2;
cpu_state.eflags &= ~VIF_FLAG;
cpu_state.flags = (cpu_state.flags & 0x3300) | (new_flags & 0x4cd5) | 2;
loadcs(new_cs);
cpu_state.pc = new_pc;
@ -189,14 +189,14 @@ static int opIRET(uint32_t fetchdat)
{
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
cpu_state.flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
}
else
{
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
cpu_state.flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
SP += 6;
}
loadcs(new_cs);
@ -216,7 +216,7 @@ static int opIRETD(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;
@ -235,16 +235,16 @@ static int opIRETD(uint32_t fetchdat)
{
cpu_state.pc = readmeml(ss, ESP);
new_cs = readmemw(ss, ESP + 4);
flags = (readmemw(ss, ESP + 8) & 0xffd5) | 2;
eflags = readmemw(ss, ESP + 10);
cpu_state.flags = (readmemw(ss, ESP + 8) & 0xffd5) | 2;
cpu_state.eflags = readmemw(ss, ESP + 10);
ESP += 12;
}
else
{
cpu_state.pc = readmeml(ss, SP);
new_cs = readmemw(ss, ((SP + 4) & 0xffff));
flags = (readmemw(ss,(SP + 8) & 0xffff) & 0xffd5) | 2;
eflags = readmemw(ss, (SP + 10) & 0xffff);
cpu_state.flags = (readmemw(ss,(SP + 8) & 0xffff) & 0xffd5) | 2;
cpu_state.eflags = readmemw(ss, (SP + 10) & 0xffff);
SP += 12;
}
loadcs(new_cs);

90
src/x86_ops_shift.h
View file

@ -13,9 +13,9 @@
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
@ -28,14 +28,14 @@
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x10: /*RCL b,CL*/ \
temp2 = flags & C_FLAG; \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
@ -45,14 +45,14 @@
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x18: /*RCR b,CL*/ \
temp2 = flags & C_FLAG; \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
@ -62,9 +62,9 @@
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
@ -105,9 +105,9 @@
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
@ -120,14 +120,14 @@
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x10: /*RCL w, c*/ \
temp2 = flags & C_FLAG; \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
@ -137,14 +137,14 @@
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
case 0x18: /*RCR w, c*/ \
temp2 = flags & C_FLAG; \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
@ -154,9 +154,9 @@
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
break; \
@ -197,9 +197,9 @@
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
@ -212,9 +212,9 @@
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
@ -229,14 +229,14 @@
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
case 0x18: /*RCR l, c*/ \
temp2 = flags & C_FLAG; \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
@ -246,9 +246,9 @@
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
flags &= ~(C_FLAG | V_FLAG); \
if (temp2) flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
break; \
@ -541,7 +541,7 @@ static int opD3_l_a32(uint32_t fetchdat)
seteaw(tempw); if (cpu_state.abrt) return 1; \
setznp16(tempw); \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
}
#define SHLD_l() \
@ -553,7 +553,7 @@ static int opD3_l_a32(uint32_t fetchdat)
seteal(templ); if (cpu_state.abrt) return 1; \
setznp32(templ); \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
}
@ -567,7 +567,7 @@ static int opD3_l_a32(uint32_t fetchdat)
seteaw(tempw); if (cpu_state.abrt) return 1; \
setznp16(tempw); \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
}
#define SHRD_l() \
@ -579,7 +579,7 @@ static int opD3_l_a32(uint32_t fetchdat)
seteal(templ); if (cpu_state.abrt) return 1; \
setznp32(templ); \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
if (tempc) cpu_state.flags |= C_FLAG; \
}
#define opSHxD(operation) \

168
src/x86_ops_string.h
View file

@ -6,8 +6,8 @@ static int opMOVSB_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
return 0;
@ -20,8 +20,8 @@ static int opMOVSB_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
return 0;
@ -35,8 +35,8 @@ static int opMOVSW_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 0);
return 0;
@ -49,8 +49,8 @@ static int opMOVSW_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,1,0, 1);
return 0;
@ -64,8 +64,8 @@ static int opMOVSL_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 0);
return 0;
@ -78,8 +78,8 @@ static int opMOVSL_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es);
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,1, 1);
return 0;
@ -95,8 +95,8 @@ static int opCMPSB_a16(uint32_t fetchdat)
src = readmemb(cpu_state.ea_seg->base, SI);
dst = readmemb(es, DI); if (cpu_state.abrt) return 1;
setsub8(src, dst);
if (flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
return 0;
@ -110,8 +110,8 @@ static int opCMPSB_a32(uint32_t fetchdat)
src = readmemb(cpu_state.ea_seg->base, ESI);
dst = readmemb(es, EDI); if (cpu_state.abrt) return 1;
setsub8(src, dst);
if (flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
return 0;
@ -126,8 +126,8 @@ static int opCMPSW_a16(uint32_t fetchdat)
src = readmemw(cpu_state.ea_seg->base, SI);
dst = readmemw(es, DI); if (cpu_state.abrt) return 1;
setsub16(src, dst);
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 0);
return 0;
@ -141,8 +141,8 @@ static int opCMPSW_a32(uint32_t fetchdat)
src = readmemw(cpu_state.ea_seg->base, ESI);
dst = readmemw(es, EDI); if (cpu_state.abrt) return 1;
setsub16(src, dst);
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2,0,0,0, 1);
return 0;
@ -157,8 +157,8 @@ static int opCMPSL_a16(uint32_t fetchdat)
src = readmeml(cpu_state.ea_seg->base, SI);
dst = readmeml(es, DI); if (cpu_state.abrt) return 1;
setsub32(src, dst);
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 0);
return 0;
@ -172,8 +172,8 @@ static int opCMPSL_a32(uint32_t fetchdat)
src = readmeml(cpu_state.ea_seg->base, ESI);
dst = readmeml(es, EDI); if (cpu_state.abrt) return 1;
setsub32(src, dst);
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES((is486) ? 8 : 10);
PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0,2,0,0, 1);
return 0;
@ -183,8 +183,8 @@ static int opSTOSB_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememb(es, DI, AL); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI--;
else DI++;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return 0;
@ -193,8 +193,8 @@ static int opSTOSB_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememb(es, EDI, AL); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI--;
else EDI++;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
return 0;
@ -204,8 +204,8 @@ static int opSTOSW_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememw(es, DI, AX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 2;
else DI += 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return 0;
@ -214,8 +214,8 @@ static int opSTOSW_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememw(es, EDI, AX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 1);
return 0;
@ -225,8 +225,8 @@ static int opSTOSL_a16(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememl(es, DI, EAX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 4;
else DI += 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
return 0;
@ -235,8 +235,8 @@ static int opSTOSL_a32(uint32_t fetchdat)
{
SEG_CHECK_WRITE(&cpu_state.seg_es);
writememl(es, EDI, EAX); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,0,1, 1);
return 0;
@ -250,8 +250,8 @@ static int opLODSB_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
AL = temp;
if (flags & D_FLAG) SI--;
else SI++;
if (cpu_state.flags & D_FLAG) SI--;
else SI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
return 0;
@ -263,8 +263,8 @@ static int opLODSB_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
AL = temp;
if (flags & D_FLAG) ESI--;
else ESI++;
if (cpu_state.flags & D_FLAG) ESI--;
else ESI++;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
return 0;
@ -277,8 +277,8 @@ static int opLODSW_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
AX = temp;
if (flags & D_FLAG) SI -= 2;
else SI += 2;
if (cpu_state.flags & D_FLAG) SI -= 2;
else SI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
return 0;
@ -290,8 +290,8 @@ static int opLODSW_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
AX = temp;
if (flags & D_FLAG) ESI -= 2;
else ESI += 2;
if (cpu_state.flags & D_FLAG) ESI -= 2;
else ESI += 2;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 1,0,0,0, 1);
return 0;
@ -304,8 +304,8 @@ static int opLODSL_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
EAX = temp;
if (flags & D_FLAG) SI -= 4;
else SI += 4;
if (cpu_state.flags & D_FLAG) SI -= 4;
else SI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
return 0;
@ -317,8 +317,8 @@ static int opLODSL_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
EAX = temp;
if (flags & D_FLAG) ESI -= 4;
else ESI += 4;
if (cpu_state.flags & D_FLAG) ESI -= 4;
else ESI += 4;
CLOCK_CYCLES(5);
PREFETCH_RUN(5, 1, -1, 0,1,0,0, 1);
return 0;
@ -332,8 +332,8 @@ static int opSCASB_a16(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemb(es, DI); if (cpu_state.abrt) return 1;
setsub8(AL, temp);
if (flags & D_FLAG) DI--;
else DI++;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
return 0;
@ -345,8 +345,8 @@ static int opSCASB_a32(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemb(es, EDI); if (cpu_state.abrt) return 1;
setsub8(AL, temp);
if (flags & D_FLAG) EDI--;
else EDI++;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
return 0;
@ -359,8 +359,8 @@ static int opSCASW_a16(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemw(es, DI); if (cpu_state.abrt) return 1;
setsub16(AX, temp);
if (flags & D_FLAG) DI -= 2;
else DI += 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 0);
return 0;
@ -372,8 +372,8 @@ static int opSCASW_a32(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmemw(es, EDI); if (cpu_state.abrt) return 1;
setsub16(AX, temp);
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 1,0,0,0, 1);
return 0;
@ -386,8 +386,8 @@ static int opSCASL_a16(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmeml(es, DI); if (cpu_state.abrt) return 1;
setsub32(EAX, temp);
if (flags & D_FLAG) DI -= 4;
else DI += 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 0);
return 0;
@ -399,8 +399,8 @@ static int opSCASL_a32(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es);
temp = readmeml(es, EDI); if (cpu_state.abrt) return 1;
setsub32(EAX, temp);
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(7);
PREFETCH_RUN(7, 1, -1, 0,1,0,0, 1);
return 0;
@ -414,8 +414,8 @@ static int opINSB_a16(uint32_t fetchdat)
check_io_perm(DX);
temp = inb(DX);
writememb(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI--;
else DI++;
if (cpu_state.flags & D_FLAG) DI--;
else DI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
return 0;
@ -428,8 +428,8 @@ static int opINSB_a32(uint32_t fetchdat)
check_io_perm(DX);
temp = inb(DX);
writememb(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI--;
else EDI++;
if (cpu_state.flags & D_FLAG) EDI--;
else EDI++;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
return 0;
@ -444,8 +444,8 @@ static int opINSW_a16(uint32_t fetchdat)
check_io_perm(DX + 1);
temp = inw(DX);
writememw(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 2;
else DI += 2;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 0);
return 0;
@ -459,8 +459,8 @@ static int opINSW_a32(uint32_t fetchdat)
check_io_perm(DX + 1);
temp = inw(DX);
writememw(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 2;
else EDI += 2;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 1,0,1,0, 1);
return 0;
@ -477,8 +477,8 @@ static int opINSL_a16(uint32_t fetchdat)
check_io_perm(DX + 3);
temp = inl(DX);
writememl(es, DI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) DI -= 4;
else DI += 4;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 0);
return 0;
@ -494,8 +494,8 @@ static int opINSL_a32(uint32_t fetchdat)
check_io_perm(DX + 3);
temp = inl(DX);
writememl(es, EDI, temp); if (cpu_state.abrt) return 1;
if (flags & D_FLAG) EDI -= 4;
else EDI += 4;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(15);
PREFETCH_RUN(15, 1, -1, 0,1,0,1, 1);
return 0;
@ -508,8 +508,8 @@ static int opOUTSB_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
if (flags & D_FLAG) SI--;
else SI++;
if (cpu_state.flags & D_FLAG) SI--;
else SI++;
outb(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 0);
@ -522,8 +522,8 @@ static int opOUTSB_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
if (flags & D_FLAG) ESI--;
else ESI++;
if (cpu_state.flags & D_FLAG) ESI--;
else ESI++;
outb(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 1);
@ -538,8 +538,8 @@ static int opOUTSW_a16(uint32_t fetchdat)
temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
if (flags & D_FLAG) SI -= 2;
else SI += 2;
if (cpu_state.flags & D_FLAG) SI -= 2;
else SI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 0);
@ -553,8 +553,8 @@ static int opOUTSW_a32(uint32_t fetchdat)
temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
check_io_perm(DX);
check_io_perm(DX + 1);
if (flags & D_FLAG) ESI -= 2;
else ESI += 2;
if (cpu_state.flags & D_FLAG) ESI -= 2;
else ESI += 2;
outw(DX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 1,0,1,0, 1);
@ -571,8 +571,8 @@ static int opOUTSL_a16(uint32_t fetchdat)
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
if (flags & D_FLAG) SI -= 4;
else SI += 4;
if (cpu_state.flags & D_FLAG) SI -= 4;
else SI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 0,1,0,1, 0);
@ -588,8 +588,8 @@ static int opOUTSL_a32(uint32_t fetchdat)
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
if (flags & D_FLAG) ESI -= 4;
else ESI += 4;
if (cpu_state.flags & D_FLAG) ESI -= 4;
else ESI += 4;
outl(EDX, temp);
CLOCK_CYCLES(14);
PREFETCH_RUN(14, 1, -1, 0,1,0,1, 1);

85
src/x86seg.c
View file

@ -115,21 +115,21 @@ void x86_doabrt(int x86_abrt)
uint32_t addr = (x86_abrt << 2) + idt.base;
if (stack32)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-2,cpu_state.flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.flags &= ~I_FLAG;
cpu_state.flags &= ~T_FLAG;
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
@ -315,7 +315,7 @@ int loadseg(uint16_t seg, x86seg *s)
uint32_t addr;
int dpl;
if (msw&1 && !(eflags&VM_FLAG))
if (msw&1 && !(cpu_state.eflags&VM_FLAG))
{
// intcount++;
if (!(seg&~3))
@ -499,7 +499,7 @@ void loadcs(uint16_t seg)
uint16_t segdat[4];
uint32_t addr;
if (output) pclog("Load CS %04X\n",seg);
if (msw&1 && !(eflags&VM_FLAG))
if (msw&1 && !(cpu_state.eflags&VM_FLAG))
{
// intcount++;
// flushmmucache();
@ -608,8 +608,8 @@ void loadcs(uint16_t seg)
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
CS=seg;
if (eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
}
}
@ -621,7 +621,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
uint16_t type,seg2;
uint32_t newpc;
// pclog("Load CS JMP %04X\n",seg);
if (msw&1 && !(eflags&VM_FLAG))
if (msw&1 && !(cpu_state.eflags&VM_FLAG))
{
if (!(seg&~3))
{
@ -827,7 +827,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
optype=JMP;
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
flags &= ~NT_FLAG;
cpu_state.flags &= ~NT_FLAG;
cpl_override=0;
// case 0xB00: /*386 Busy task gate*/
// if (optype==JMP) pclog("Task switch!\n");
@ -853,8 +853,8 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
CS=seg;
if (eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
cycles -= timing_jmp_rm;
}
@ -941,7 +941,7 @@ void loadcscall(uint16_t seg)
int csout = output;
if (msw&1 && !(eflags&VM_FLAG))
if (msw&1 && !(cpu_state.eflags&VM_FLAG))
{
//flushmmucache();
if (csout) pclog("Protected mode CS load! %04X\n",seg);
@ -1370,8 +1370,8 @@ void loadcscall(uint16_t seg)
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
CS=seg;
if (eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2;
else cpu_state.seg_cs.access=(0<<5) | 2;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
}
}
@ -1383,7 +1383,7 @@ void pmoderetf(int is32, uint16_t off)
uint32_t addr, oaddr;
uint16_t segdat[4],segdat2[4],seg,newss;
uint32_t oldsp=ESP;
if (output) pclog("RETF %i %04X:%04X %08X %04X\n",is32,CS,cpu_state.pc,cr0,eflags);
if (output) pclog("RETF %i %04X:%04X %08X %04X\n",is32,CS,cpu_state.pc,cr0,cpu_state.eflags);
if (is32)
{
newpc=POPL();
@ -1683,7 +1683,7 @@ void pmodeint(int num, int soft)
// if (!num) pclog("Pmode int 0 at %04X(%06X):%08X\n",CS,cs,pc);
// pclog("Pmode int %02X %i %04X:%08X %04X:%08X %i\n",num,soft,CS,pc, SS, ESP, abrt);
if (eflags&VM_FLAG && IOPL!=3 && soft)
if (cpu_state.eflags&VM_FLAG && IOPL!=3 && soft)
{
if (output) pclog("V86 banned int\n");
pclog("V86 banned int!\n");
@ -1806,7 +1806,7 @@ void pmodeint(int num, int soft)
x86np("Int gate CS not present\n", segdat[1] & 0xfffc);
return;
}
if ((eflags&VM_FLAG) && DPL2)
if ((cpu_state.eflags & VM_FLAG) && DPL2)
{
pclog("V86 calling int gate, DPL != 0\n");
x86gpf(NULL,segdat[1]&0xFFFC);
@ -1896,7 +1896,7 @@ void pmodeint(int num, int soft)
if (type>=0x800)
{
// if (output) pclog("Push 32 %i\n",eflags&VM_FLAG);
if (eflags & VM_FLAG)
if (cpu_state.eflags & VM_FLAG)
{
PUSHL(GS);
PUSHL(FS);
@ -1909,7 +1909,7 @@ void pmodeint(int num, int soft)
}
PUSHL(oldss);
PUSHL(oldsp);
PUSHL(flags|(eflags<<16));
PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
// if (soft) pclog("Pushl CS %08X\n", CS);
PUSHL(CS);
// if (soft) pclog("Pushl PC %08X\n", pc);
@ -1921,7 +1921,7 @@ void pmodeint(int num, int soft)
// if (output) pclog("Push 16\n");
PUSHW(oldss);
PUSHW(oldsp);
PUSHW(flags);
PUSHW(cpu_state.flags);
// if (soft) pclog("Pushw CS %04X\n", CS);
PUSHW(CS);
// if (soft) pclog("Pushw pc %04X\n", pc);
@ -1947,7 +1947,7 @@ void pmodeint(int num, int soft)
x86np("Int gate CS not present\n", segdat[1] & 0xfffc);
return;
}
if ((eflags & VM_FLAG) && DPL2<CPL)
if ((cpu_state.eflags & VM_FLAG) && DPL2<CPL)
{
pclog("Int gate V86 mode DPL2<CPL\n");
x86gpf(NULL,seg&~3);
@ -1956,7 +1956,7 @@ void pmodeint(int num, int soft)
// if (!stack_changed && ssegs) restore_stack();
if (type>0x800)
{
PUSHL(flags|(eflags<<16));
PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
// if (soft) pclog("Pushlc CS %08X\n", CS);
PUSHL(CS);
// if (soft) pclog("Pushlc PC %08X\n", pc);
@ -1964,7 +1964,7 @@ void pmodeint(int num, int soft)
}
else
{
PUSHW(flags);
PUSHW(cpu_state.flags);
// if (soft) pclog("Pushwc CS %04X\n", CS);
PUSHW(CS);
// if (soft) pclog("Pushwc PC %04X\n", pc);
@ -1993,14 +1993,14 @@ void pmodeint(int num, int soft)
cpl_override = 0;
#endif
eflags&=~VM_FLAG;
cpu_state.eflags &= ~VM_FLAG;
cpu_cur_status &= ~CPU_STATUS_V86;
if (!(type&0x100))
{
flags&=~I_FLAG;
cpu_state.flags &= ~I_FLAG;
// pclog("INT %02X disabling interrupts %i\n",num,soft);
}
flags&=~(T_FLAG|NT_FLAG);
cpu_state.flags &= ~(T_FLAG|NT_FLAG);
// if (output) pclog("Final Stack %04X:%08X\n",SS,ESP);
cycles -= timing_int_pm;
break;
@ -2065,7 +2065,7 @@ void pmodeiret(int is32)
uint16_t seg = 0;
uint32_t addr, oaddr;
uint32_t oldsp=ESP;
if (is386 && (eflags&VM_FLAG))
if (is386 && (cpu_state.eflags & VM_FLAG))
{
// if (output) pclog("V86 IRET\n");
if (IOPL!=3)
@ -2093,7 +2093,7 @@ void pmodeiret(int is32)
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
CS=seg;
flags=(flags&0x3000)|(tempflags&0xCFD5)|2;
cpu_state.flags = (cpu_state.flags & 0x3000) | (tempflags & 0xCFD5) | 2;
cycles -= timing_iret_rm;
return;
}
@ -2102,7 +2102,7 @@ void pmodeiret(int is32)
//flushmmucache();
// if (output) pclog("Pmode IRET %04X:%04X ",CS,pc);
if (flags&NT_FLAG)
if (cpu_state.flags & NT_FLAG)
{
// pclog("NT IRET\n");
seg=readmemw(tr.base,0);
@ -2155,7 +2155,7 @@ void pmodeiret(int is32)
segs[2]=POPL();
segs[3]=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
// pclog("Pop stack %04X:%04X\n",newss,newsp);
eflags=tempflags>>16;
cpu_state.eflags = tempflags>>16;
cpu_cur_status |= CPU_STATUS_V86;
loadseg(segs[0],&cpu_state.seg_es);
do_seg_v86_init(&cpu_state.seg_es);
@ -2185,7 +2185,7 @@ void pmodeiret(int is32)
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
use32=0;
cpu_cur_status &= ~CPU_STATUS_USE32;
flags=(tempflags&0xFFD5)|2;
cpu_state.flags = (tempflags&0xFFD5)|2;
cycles -= timing_iret_v86;
// pclog("V86 IRET to %04X:%04X %04X:%04X %04X %04X %04X %04X %i\n",CS,pc,SS,SP,DS,ES,FS,GS,abrt);
// if (CS==0xFFFF && pc==0xFFFFFFFF) timetolive=12;
@ -2422,8 +2422,8 @@ void pmodeiret(int is32)
cycles -= timing_iret_pm_outer;
}
cpu_state.pc=newpc;
flags=(flags&~flagmask)|(tempflags&flagmask&0xFFD5)|2;
if (is32) eflags=tempflags>>16;
cpu_state.flags = (cpu_state.flags&~flagmask) | (tempflags&flagmask&0xFFD5)|2;
if (is32) cpu_state.eflags = tempflags>>16;
// pclog("done\n");
}
@ -2477,13 +2477,13 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
}
if (cpu_state.abrt) return;
if (optype==IRET) flags&=~NT_FLAG;
if (optype==IRET) cpu_state.flags&=~NT_FLAG;
// if (output) pclog("Write PC %08X %08X\n",tr.base,pc);
cpu_386_flags_rebuild();
writememl(tr.base,0x1C,cr3);
writememl(tr.base,0x20,cpu_state.pc);
writememl(tr.base,0x24,flags|(eflags<<16));
writememl(tr.base,0x24,cpu_state.flags | (cpu_state.eflags<<16));
writememl(tr.base,0x28,EAX);
writememl(tr.base,0x2C,ECX);
@ -2556,8 +2556,8 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
cpu_state.pc=new_pc;
// if (output) pclog("New pc %08X\n",new_pc);
flags=new_flags;
eflags=new_flags>>16;
cpu_state.flags = new_flags;
cpu_state.eflags = new_flags>>16;
cpu_386_flags_extract();
// if (output) pclog("Load LDT %04X\n",new_ldt);
@ -2574,7 +2574,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
// if (output) pclog("Limit %04X Base %08X\n",ldt.limit,ldt.base);
if (eflags & VM_FLAG)
if (cpu_state.eflags & VM_FLAG)
{
loadcs(new_cs);
set_use32(0);
@ -2695,12 +2695,13 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
}
if (cpu_state.abrt) return;
if (optype==IRET) flags&=~NT_FLAG;
if (optype == IRET)
cpu_state.flags &= ~NT_FLAG;
// if (output) pclog("Write PC %08X %08X\n",tr.base,pc);
cpu_386_flags_rebuild();
writememw(tr.base,0x0E,cpu_state.pc);
writememw(tr.base,0x10,flags);
writememw(tr.base,0x10,cpu_state.flags);
writememw(tr.base,0x12,AX);
writememw(tr.base,0x14,CX);
@ -2760,7 +2761,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
cpu_state.pc=new_pc;
// if (output) pclog("New pc %08X\n",new_pc);
flags=new_flags;
cpu_state.flags = new_flags;
cpu_386_flags_extract();
// if (output) pclog("Load LDT %04X\n",new_ldt);

24
src/x87_ops_arith.h
View file

@ -206,9 +206,9 @@ static int opFCOMI(uint32_t fetchdat)
cpu_state.pc++;
if (fplog) pclog("FICOM\n");
flags_rebuild();
flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) flags |= C_FLAG;
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
CLOCK_CYCLES(4);
return 0;
}
@ -218,9 +218,9 @@ static int opFCOMIP(uint32_t fetchdat)
cpu_state.pc++;
if (fplog) pclog("FICOMP\n");
flags_rebuild();
flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) flags |= C_FLAG;
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
x87_pop();
CLOCK_CYCLES(4);
return 0;
@ -415,9 +415,9 @@ static int opFUCOMI(uint32_t fetchdat)
cpu_state.pc++;
if (fplog) pclog("FUCOMI\n");
flags_rebuild();
flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) flags |= C_FLAG;
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
CLOCK_CYCLES(4);
return 0;
}
@ -427,9 +427,9 @@ static int opFUCOMIP(uint32_t fetchdat)
cpu_state.pc++;
if (fplog) pclog("FUCOMIP\n");
flags_rebuild();
flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) flags |= C_FLAG;
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
x87_pop();
CLOCK_CYCLES(4);
return 0;