Pack decoded ModR/M data into a single word - minor recompiler speedup.
This commit is contained in:
SarahW
parent
31298d6be1
commit
535604b760
34 changed files with 1263 additions and 1270 deletions
28
src/386.c
28
src/386.c
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@ -66,11 +66,11 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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if (rm == 4)
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if (cpu_rm == 4)
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{
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uint8_t sib = rmdat >> 8;
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switch (mod)
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switch (cpu_mod)
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{
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case 0:
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eaaddr = cpu_state.regs[sib & 7].l;
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@ -87,7 +87,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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break;
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}
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/*SIB byte present*/
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if ((sib & 7) == 5 && !mod)
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if ((sib & 7) == 5 && !cpu_mod)
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eaaddr = getlong();
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else if ((sib & 6) == 4 && !ssegs)
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{
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@ -100,16 +100,16 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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}
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else
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{
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eaaddr = cpu_state.regs[rm].l;
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if (mod)
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eaaddr = cpu_state.regs[cpu_rm].l;
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if (cpu_mod)
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{
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if (rm == 5 && !ssegs)
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if (cpu_rm == 5 && !ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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ea_seg = &_ss;
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}
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if (mod == 1)
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if (cpu_mod == 1)
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{
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eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.pc++;
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@ -119,7 +119,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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eaaddr += getlong();
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}
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}
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else if (rm == 5)
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else if (cpu_rm == 5)
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{
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eaaddr = getlong();
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}
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@ -139,13 +139,13 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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if (!mod && rm == 6)
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if (!cpu_mod && cpu_rm == 6)
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{
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eaaddr = getword();
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}
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else
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{
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switch (mod)
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switch (cpu_mod)
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{
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case 0:
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eaaddr = 0;
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@ -157,8 +157,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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eaaddr = getword();
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break;
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}
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eaaddr += (*mod1add[0][rm]) + (*mod1add[1][rm]);
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if (mod1seg[rm] == &ss && !ssegs)
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eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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@ -176,8 +176,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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}
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}
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#define fetch_ea_16(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 0; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 0
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#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 0; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 0
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#include "x86_flags.h"
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@ -153,8 +153,8 @@ static inline uint64_t getquad()
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static inline uint8_t geteab()
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{
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if (mod == 3)
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return (rm & 4) ? cpu_state.regs[rm & 3].b.h : cpu_state.regs[rm&3].b.l;
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if (cpu_mod == 3)
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return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
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if (eal_r)
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return *(uint8_t *)eal_r;
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return readmemb(easeg, eaaddr);
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@ -162,8 +162,8 @@ static inline uint8_t geteab()
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static inline uint16_t geteaw()
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{
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if (mod == 3)
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return cpu_state.regs[rm].w;
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if (cpu_mod == 3)
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return cpu_state.regs[cpu_rm].w;
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// cycles-=3;
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if (eal_r)
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return *(uint16_t *)eal_r;
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@ -172,8 +172,8 @@ static inline uint16_t geteaw()
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static inline uint32_t geteal()
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{
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if (mod == 3)
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return cpu_state.regs[rm].l;
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if (cpu_mod == 3)
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return cpu_state.regs[cpu_rm].l;
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// cycles-=3;
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if (eal_r)
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return *eal_r;
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@ -206,9 +206,9 @@ static inline void seteaq(uint64_t v)
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writememql(easeg, eaaddr, v);
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}
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#define seteab(v) if (mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v); } else if (rm&4) cpu_state.regs[rm&3].b.h=v; else cpu_state.regs[rm].b.l=v
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#define seteaw(v) if (mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v); } else cpu_state.regs[rm].w=v
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#define seteal(v) if (mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v); } else cpu_state.regs[rm].l=v
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#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v);
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@ -74,11 +74,11 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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if (rm == 4)
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if (cpu_rm == 4)
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{
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uint8_t sib = rmdat >> 8;
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switch (mod)
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switch (cpu_mod)
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{
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case 0:
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eaaddr = cpu_state.regs[sib & 7].l;
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@ -95,7 +95,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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break;
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}
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/*SIB byte present*/
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if ((sib & 7) == 5 && !mod)
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if ((sib & 7) == 5 && !cpu_mod)
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eaaddr = getlong();
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else if ((sib & 6) == 4 && !ssegs)
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{
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@ -108,16 +108,16 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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}
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else
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{
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eaaddr = cpu_state.regs[rm].l;
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if (mod)
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eaaddr = cpu_state.regs[cpu_rm].l;
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if (cpu_mod)
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{
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if (rm == 5 && !ssegs)
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if (cpu_rm == 5 && !ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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ea_seg = &_ss;
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}
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if (mod == 1)
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if (cpu_mod == 1)
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{
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eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.pc++;
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@ -127,7 +127,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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eaaddr += getlong();
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}
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}
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else if (rm == 5)
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else if (cpu_rm == 5)
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{
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eaaddr = getlong();
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}
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@ -147,13 +147,13 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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if (!mod && rm == 6)
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if (!cpu_mod && cpu_rm == 6)
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{
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eaaddr = getword();
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}
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else
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{
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switch (mod)
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switch (cpu_mod)
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{
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case 0:
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eaaddr = 0;
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@ -165,8 +165,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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eaaddr = getword();
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break;
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}
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eaaddr += (*mod1add[0][rm]) + (*mod1add[1][rm]);
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if (mod1seg[rm] == &ss && !ssegs)
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eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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@ -184,8 +184,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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}
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}
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#define fetch_ea_16(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 1
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#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 1
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#include "x86_flags.h"
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@ -45,8 +45,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
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}
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}
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#define fetch_ea_16(rmdat) cpu_state.pc++; if (mod != 3) fetch_ea_16_long(rmdat);
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#define fetch_ea_32(rmdat) cpu_state.pc++; if (mod != 3) fetch_ea_32_long(rmdat);
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#define fetch_ea_16(rmdat) cpu_state.pc++; if (cpu_mod != 3) fetch_ea_16_long(rmdat);
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#define fetch_ea_32(rmdat) cpu_state.pc++; if (cpu_mod != 3) fetch_ea_32_long(rmdat);
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448
src/808x.c
448
src/808x.c
File diff suppressed because it is too large
Load diff
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@ -136,7 +136,7 @@ static int LOAD_REG_L(int reg)
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static int LOAD_VAR_W(uintptr_t addr)
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{
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int host_reg = find_host_reg();
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host_reg_mapping[host_reg] = reg;
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host_reg_mapping[host_reg] = 0;
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addbyte(0x66); /*MOVL host_reg,[reg]*/
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addbyte(0x8b);
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@ -148,7 +148,7 @@ static int LOAD_VAR_W(uintptr_t addr)
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static int LOAD_VAR_L(uintptr_t addr)
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{
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int host_reg = find_host_reg();
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host_reg_mapping[host_reg] = reg;
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host_reg_mapping[host_reg] = 0;
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addbyte(0x8b); /*MOVL host_reg,[reg]*/
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addbyte(0x05 | (host_reg << 3));
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@ -160,7 +160,7 @@ static int LOAD_VAR_L(uintptr_t addr)
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static int LOAD_REG_IMM(uint32_t imm)
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{
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int host_reg = find_host_reg();
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host_reg_mapping[host_reg] = reg;
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host_reg_mapping[host_reg] = 0;
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addbyte(0xc7); /*MOVL host_reg, imm*/
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addbyte(0xc0 | host_reg);
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@ -172,7 +172,7 @@ static int LOAD_REG_IMM(uint32_t imm)
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static int LOAD_HOST_REG(int host_reg)
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{
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int new_host_reg = find_host_reg();
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host_reg_mapping[new_host_reg] = reg;
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host_reg_mapping[new_host_reg] = 0;
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addbyte(0x89); /*MOV new_host_reg, host_reg*/
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addbyte(0xc0 | (host_reg << 3) | new_host_reg);
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@ -608,7 +608,7 @@ void codegen_debug()
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static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
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{
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if (!mod && rm == 6)
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if (!cpu_mod && cpu_rm == 6)
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{
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addbyte(0xC7); /*MOVL $0,(ssegs)*/
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addbyte(0x04);
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@ -621,7 +621,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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{
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int base_reg, index_reg;
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switch (rm)
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switch (cpu_rm)
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{
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case 0: case 1: case 7:
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base_reg = LOAD_REG_W(REG_BX);
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@ -636,9 +636,9 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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base_reg = LOAD_REG_W(REG_DI);
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break;
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}
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if (!(rm & 4))
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if (!(cpu_rm & 4))
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{
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if (rm & 1)
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if (cpu_rm & 1)
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index_reg = LOAD_REG_W(REG_DI);
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else
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index_reg = LOAD_REG_W(REG_SI);
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@ -646,10 +646,10 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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base_reg &= 7;
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index_reg &= 7;
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switch (mod)
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switch (cpu_mod)
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{
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case 0:
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if (rm & 4)
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if (cpu_rm & 4)
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{
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addbyte(0x41); /*MOVZX EAX, base_reg*/
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addbyte(0x0f);
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@ -675,7 +675,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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}
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break;
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case 1:
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if (rm & 4)
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if (cpu_rm & 4)
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{
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addbyte(0x67); /*LEA EAX, base_reg+imm8*/
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addbyte(0x41);
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@ -695,7 +695,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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(*op_pc)++;
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break;
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case 2:
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if (rm & 4)
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if (cpu_rm & 4)
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{
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addbyte(0x67); /*LEA EAX, base_reg+imm8*/
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addbyte(0x41);
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@ -716,7 +716,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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break;
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}
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if (mod || !(rm & 4))
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if (cpu_mod || !(cpu_rm & 4))
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{
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addbyte(0x25); /*ANDL $0xffff, %eax*/
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addlong(0xffff);
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@ -726,7 +726,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
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addbyte(0x25);
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addlong((uint32_t)&eaaddr);
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if (mod1seg[rm] == &ss && !op_ssegs)
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if (mod1seg[cpu_rm] == &ss && !op_ssegs)
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op_ea_seg = &_ss;
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}
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return op_ea_seg;
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@ -736,14 +736,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
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{
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uint32_t new_eaaddr;
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if (rm == 4)
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if (cpu_rm == 4)
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{
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uint8_t sib = fetchdat >> 8;
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int base_reg = -1, index_reg = -1;
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(*op_pc)++;
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if (mod || (sib & 7) != 5)
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if (cpu_mod || (sib & 7) != 5)
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base_reg = LOAD_REG_L(sib & 7) & 7;
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|
||||
if (((sib >> 3) & 7) != 4)
|
||||
|
|
@ -751,7 +751,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
|
||||
if (index_reg == -1)
|
||||
{
|
||||
switch (mod)
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
if ((sib & 7) == 5)
|
||||
|
|
@ -805,7 +805,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
else
|
||||
{
|
||||
switch (mod)
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
if ((sib & 7) == 5)
|
||||
|
|
@ -869,12 +869,12 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
break;
|
||||
}
|
||||
}
|
||||
if (stack_offset && (sib & 7) == 4 && (mod || (sib & 7) != 5)) /*ESP*/
|
||||
if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) /*ESP*/
|
||||
{
|
||||
addbyte(0x05);
|
||||
addlong(stack_offset);
|
||||
}
|
||||
if (((sib & 7) == 4 || (mod && (sib & 7) == 5)) && !op_ssegs)
|
||||
if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
|
|
@ -886,7 +886,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
{
|
||||
int base_reg;
|
||||
|
||||
if (!mod && rm == 5)
|
||||
if (!cpu_mod && cpu_rm == 5)
|
||||
{
|
||||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
|
|
@ -897,12 +897,12 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
(*op_pc) += 4;
|
||||
return op_ea_seg;
|
||||
}
|
||||
base_reg = LOAD_REG_L(rm) & 7;
|
||||
if (mod)
|
||||
base_reg = LOAD_REG_L(cpu_rm) & 7;
|
||||
if (cpu_mod)
|
||||
{
|
||||
if (rm == 5 && !op_ssegs)
|
||||
if (cpu_rm == 5 && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
if (mod == 1)
|
||||
if (cpu_mod == 1)
|
||||
{
|
||||
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
|
||||
addbyte(0x41);
|
||||
|
|
@ -1167,30 +1167,19 @@ generate_call:
|
|||
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
|
||||
stack_offset = (op_32 & 0x100) ? 4 : 2;
|
||||
|
||||
mod = (fetchdat >> 6) & 3;
|
||||
reg = (fetchdat >> 3) & 7;
|
||||
rm = fetchdat & 7;
|
||||
cpu_mod = (fetchdat >> 6) & 3;
|
||||
cpu_reg = (fetchdat >> 3) & 7;
|
||||
cpu_rm = fetchdat & 7;
|
||||
|
||||
addbyte(0xC7); /*MOVL $mod,(mod)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&mod);
|
||||
addlong(mod);
|
||||
addbyte(0xC7); /*MOVL $reg,(reg)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)®);
|
||||
addlong(reg);
|
||||
addbyte(0xC7); /*MOVL $rm,(rm)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&rm);
|
||||
addlong(rm);
|
||||
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.rm_data.rm_mod_reg_data - (uintptr_t)&cpu_state);
|
||||
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
|
||||
|
||||
op_pc += pc_off;
|
||||
if (mod != 3 && !(op_32 & 0x200))
|
||||
if (cpu_mod != 3 && !(op_32 & 0x200))
|
||||
op_ea_seg = codegen_generate_ea_16_long(op_ea_seg, fetchdat, op_ssegs, &op_pc);
|
||||
if (mod != 3 && (op_32 & 0x200))
|
||||
if (cpu_mod != 3 && (op_32 & 0x200))
|
||||
op_ea_seg = codegen_generate_ea_32_long(op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
|
||||
op_pc -= pc_off;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -569,7 +569,7 @@ void codegen_debug()
|
|||
|
||||
static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
|
||||
{
|
||||
if (!mod && rm == 6)
|
||||
if (!cpu_mod && cpu_rm == 6)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x05);
|
||||
|
|
@ -579,35 +579,35 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
else
|
||||
{
|
||||
switch (mod)
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
addbyte(0xa1); /*MOVL *mod1add[0][rm], %eax*/
|
||||
addlong((uint32_t)mod1add[0][rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][rm], %eax*/
|
||||
addbyte(0xa1); /*MOVL *mod1add[0][cpu_rm], %eax*/
|
||||
addlong((uint32_t)mod1add[0][cpu_rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)mod1add[1][rm]);
|
||||
addlong((uint32_t)mod1add[1][cpu_rm]);
|
||||
break;
|
||||
case 1:
|
||||
addbyte(0xb8); /*MOVL ,%eax*/
|
||||
addlong((uint32_t)(int8_t)(rmdat >> 8));// pc++;
|
||||
addbyte(0x03); /*ADDL *mod1add[0][rm], %eax*/
|
||||
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)mod1add[0][rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][rm], %eax*/
|
||||
addlong((uint32_t)mod1add[0][cpu_rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)mod1add[1][rm]);
|
||||
addlong((uint32_t)mod1add[1][cpu_rm]);
|
||||
(*op_pc)++;
|
||||
break;
|
||||
case 2:
|
||||
addbyte(0xb8); /*MOVL ,%eax*/
|
||||
addlong((fetchdat >> 8) & 0xffff);// pc++;
|
||||
addbyte(0x03); /*ADDL *mod1add[0][rm], %eax*/
|
||||
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)mod1add[0][rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][rm], %eax*/
|
||||
addlong((uint32_t)mod1add[0][cpu_rm]);
|
||||
addbyte(0x03); /*ADDL *mod1add[1][cpu_rm], %eax*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)mod1add[1][rm]);
|
||||
addlong((uint32_t)mod1add[1][cpu_rm]);
|
||||
(*op_pc) += 2;
|
||||
break;
|
||||
}
|
||||
|
|
@ -616,7 +616,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
addbyte(0xa3);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
|
||||
if (mod1seg[rm] == &ss && !op_ssegs)
|
||||
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
}
|
||||
return op_ea_seg;
|
||||
|
|
@ -626,12 +626,12 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
{
|
||||
uint32_t new_eaaddr;
|
||||
|
||||
if (rm == 4)
|
||||
if (cpu_rm == 4)
|
||||
{
|
||||
uint8_t sib = fetchdat >> 8;
|
||||
(*op_pc)++;
|
||||
|
||||
switch (mod)
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
if ((sib & 7) == 5)
|
||||
|
|
@ -667,12 +667,12 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
(*op_pc) += 4;
|
||||
break;
|
||||
}
|
||||
if (stack_offset && (sib & 7) == 4 && (mod || (sib & 7) != 5)) /*ESP*/
|
||||
if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) /*ESP*/
|
||||
{
|
||||
addbyte(0x05);
|
||||
addlong(stack_offset);
|
||||
}
|
||||
if (((sib & 7) == 4 || (mod && (sib & 7) == 5)) && !op_ssegs)
|
||||
if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
if (((sib >> 3) & 7) != 4)
|
||||
{
|
||||
|
|
@ -705,7 +705,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
else
|
||||
{
|
||||
if (!mod && rm == 5)
|
||||
if (!cpu_mod && cpu_rm == 5)
|
||||
{
|
||||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
|
|
@ -717,15 +717,15 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
|||
}
|
||||
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.regs[rm].l - (uintptr_t)&cpu_state);
|
||||
// addbyte(0xa1); /*MOVL regs[rm].l, %eax*/
|
||||
// addlong((uint32_t)&cpu_state.regs[rm].l);
|
||||
eaaddr = cpu_state.regs[rm].l;
|
||||
if (mod)
|
||||
addbyte((uintptr_t)&cpu_state.regs[cpu_rm].l - (uintptr_t)&cpu_state);
|
||||
// addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/
|
||||
// addlong((uint32_t)&cpu_state.regs[cpu_rm].l);
|
||||
eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
if (cpu_mod)
|
||||
{
|
||||
if (rm == 5 && !op_ssegs)
|
||||
if (cpu_rm == 5 && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
if (mod == 1)
|
||||
if (cpu_mod == 1)
|
||||
{
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)(int8_t)(fetchdat >> 8));
|
||||
|
|
@ -973,27 +973,19 @@ generate_call:
|
|||
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
|
||||
stack_offset = (op_32 & 0x100) ? 4 : 2;
|
||||
|
||||
mod = (fetchdat >> 6) & 3;
|
||||
reg = (fetchdat >> 3) & 7;
|
||||
rm = fetchdat & 7;
|
||||
cpu_mod = (fetchdat >> 6) & 3;
|
||||
cpu_reg = (fetchdat >> 3) & 7;
|
||||
cpu_rm = fetchdat & 7;
|
||||
|
||||
addbyte(0xC7); /*MOVL $mod,(mod)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&mod);
|
||||
addlong(mod);
|
||||
addbyte(0xC7); /*MOVL $reg,(reg)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)®);
|
||||
addlong(reg);
|
||||
addbyte(0xC7); /*MOVL $rm,(rm)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&rm);
|
||||
addlong(rm);
|
||||
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.rm_data.rm_mod_reg_data - (uintptr_t)&cpu_state);
|
||||
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
|
||||
|
||||
op_pc += pc_off;
|
||||
if (mod != 3 && !(op_32 & 0x200))
|
||||
if (cpu_mod != 3 && !(op_32 & 0x200))
|
||||
op_ea_seg = codegen_generate_ea_16_long(op_ea_seg, fetchdat, op_ssegs, &op_pc);
|
||||
if (mod != 3 && (op_32 & 0x200))
|
||||
if (cpu_mod != 3 && (op_32 & 0x200))
|
||||
op_ea_seg = codegen_generate_ea_32_long(op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
|
||||
op_pc -= pc_off;
|
||||
}
|
||||
|
|
|
|||
13
src/ibm.h
13
src/ibm.h
|
|
@ -108,6 +108,15 @@ struct
|
|||
uint32_t flags_op1, flags_op2;
|
||||
|
||||
uint32_t pc;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
int8_t rm, mod, reg;
|
||||
} rm_mod_reg;
|
||||
uint32_t rm_mod_reg_data;
|
||||
} rm_data;
|
||||
} cpu_state;
|
||||
|
||||
/*x86reg regs[8];*/
|
||||
|
|
@ -238,6 +247,10 @@ int pitcount;
|
|||
|
||||
float pit_timer0_freq();
|
||||
|
||||
#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm
|
||||
#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod
|
||||
#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg
|
||||
|
||||
|
||||
|
||||
/*DMA*/
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@ int ssegs;
|
|||
int firstrepcycle;
|
||||
|
||||
uint32_t easeg,eaaddr,ealimit,ealimitw;
|
||||
int rm,reg,mod,rmdat;
|
||||
|
||||
int skipnextprint;
|
||||
int inhlt;
|
||||
|
|
|
|||
|
|
@ -3,18 +3,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint8_t dst = getr8(rm); \
|
||||
uint8_t src = getr8(reg); \
|
||||
uint8_t dst = getr8(cpu_rm); \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(rm, operation); \
|
||||
setr8(cpu_rm, operation); \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (abrt) return 1; \
|
||||
uint8_t src = getr8(reg); \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
|
|
@ -25,18 +25,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint8_t dst = getr8(rm); \
|
||||
uint8_t src = getr8(reg); \
|
||||
uint8_t dst = getr8(cpu_rm); \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(rm, operation); \
|
||||
setr8(cpu_rm, operation); \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint8_t dst = geteab(); if (abrt) return 1; \
|
||||
uint8_t src = getr8(reg); \
|
||||
uint8_t src = getr8(cpu_reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
|
|
@ -48,18 +48,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint16_t dst = cpu_state.regs[rm].w; \
|
||||
uint16_t src = cpu_state.regs[reg].w; \
|
||||
uint16_t dst = cpu_state.regs[cpu_rm].w; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[rm].w = operation; \
|
||||
cpu_state.regs[cpu_rm].w = operation; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[reg].w; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
|
|
@ -70,18 +70,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint16_t dst = cpu_state.regs[rm].w; \
|
||||
uint16_t src = cpu_state.regs[reg].w; \
|
||||
uint16_t dst = cpu_state.regs[cpu_rm].w; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[rm].w = operation; \
|
||||
cpu_state.regs[cpu_rm].w = operation; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint16_t dst = geteaw(); if (abrt) return 1; \
|
||||
uint16_t src = cpu_state.regs[reg].w; \
|
||||
uint16_t src = cpu_state.regs[cpu_reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
|
|
@ -93,18 +93,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint32_t dst = cpu_state.regs[rm].l; \
|
||||
uint32_t src = cpu_state.regs[reg].l; \
|
||||
uint32_t dst = cpu_state.regs[cpu_rm].l; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[rm].l = operation; \
|
||||
cpu_state.regs[cpu_rm].l = operation; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[reg].l; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
|
|
@ -115,18 +115,18 @@
|
|||
{ \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
uint32_t dst = cpu_state.regs[rm].l; \
|
||||
uint32_t src = cpu_state.regs[reg].l; \
|
||||
uint32_t dst = cpu_state.regs[cpu_rm].l; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[rm].l = operation; \
|
||||
cpu_state.regs[cpu_rm].l = operation; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
uint32_t dst = geteal(); if (abrt) return 1; \
|
||||
uint32_t src = cpu_state.regs[reg].l; \
|
||||
uint32_t src = cpu_state.regs[cpu_reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
|
|
@ -139,11 +139,11 @@
|
|||
uint8_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = getr8(reg); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(reg, operation); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
setr8(cpu_reg, operation); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -151,11 +151,11 @@
|
|||
uint8_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = getr8(reg); \
|
||||
dst = getr8(cpu_reg); \
|
||||
src = geteab(); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(reg, operation); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
setr8(cpu_reg, operation); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -164,11 +164,11 @@
|
|||
uint16_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = cpu_state.regs[reg].w; \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[reg].w = operation; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
cpu_state.regs[cpu_reg].w = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -176,11 +176,11 @@
|
|||
uint16_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = cpu_state.regs[reg].w; \
|
||||
dst = cpu_state.regs[cpu_reg].w; \
|
||||
src = geteaw(); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cpu_state.regs[reg].w = operation; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
cpu_state.regs[cpu_reg].w = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -189,11 +189,11 @@
|
|||
uint32_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_16(fetchdat); \
|
||||
dst = cpu_state.regs[reg].l; \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[reg].l = operation; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
|
||||
cpu_state.regs[cpu_reg].l = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -201,11 +201,11 @@
|
|||
uint32_t dst, src; \
|
||||
if (gettempc) tempc = CF_SET() ? 1 : 0; \
|
||||
fetch_ea_32(fetchdat); \
|
||||
dst = cpu_state.regs[reg].l; \
|
||||
dst = cpu_state.regs[cpu_reg].l; \
|
||||
src = geteal(); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cpu_state.regs[reg].l = operation; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
|
||||
cpu_state.regs[cpu_reg].l = operation; \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -255,9 +255,9 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
|
|||
uint8_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
setsub8(dst, getr8(reg));
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -265,9 +265,9 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
|||
uint8_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
setsub8(dst, getr8(reg));
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub8(dst, getr8(cpu_reg));
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -276,9 +276,9 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
|
|||
uint16_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[reg].w);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -286,9 +286,9 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
|||
uint16_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
setsub16(dst, cpu_state.regs[reg].w);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub16(dst, cpu_state.regs[cpu_reg].w);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -297,9 +297,9 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
fetch_ea_16(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[reg].l);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -307,9 +307,9 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
fetch_ea_32(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
setsub32(dst, cpu_state.regs[reg].l);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
setsub32(dst, cpu_state.regs[cpu_reg].l);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -318,8 +318,8 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
|
|||
uint8_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
setsub8(getr8(reg), src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_b_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -327,8 +327,8 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
|
|||
uint8_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
setsub8(getr8(reg), src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
setsub8(getr8(cpu_reg), src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -337,8 +337,8 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
|
|||
uint16_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
setsub16(cpu_state.regs[reg].w, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_w_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -346,8 +346,8 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
|
|||
uint16_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
setsub16(cpu_state.regs[reg].w, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
setsub16(cpu_state.regs[cpu_reg].w, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -356,8 +356,8 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(cpu_state.regs[reg].l, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_l_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -365,8 +365,8 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(cpu_state.regs[reg].l, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -399,10 +399,10 @@ static int opTEST_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -410,10 +410,10 @@ static int opTEST_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -422,10 +422,10 @@ static int opTEST_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].w;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -433,10 +433,10 @@ static int opTEST_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].w;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -445,10 +445,10 @@ static int opTEST_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].l;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_l_a32(uint32_t fetchdat)
|
||||
|
|
@ -456,10 +456,10 @@ static int opTEST_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].l;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -493,47 +493,47 @@ static int opTEST_EAX(uint32_t fetchdat)
|
|||
case 0x00: /*ADD ea, #*/ \
|
||||
setea ## ea_width(dst + src); if (abrt) return 1; \
|
||||
setadd ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x08: /*OR ea, #*/ \
|
||||
dst |= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x10: /*ADC ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst + src + tempc); if (abrt) return 1; \
|
||||
setadc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x18: /*SBB ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst - (src + tempc)); if (abrt) return 1; \
|
||||
setsbc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x20: /*AND ea, #*/ \
|
||||
dst &= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 1; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x38: /*CMP ea, #*/ \
|
||||
setsub ## flag_width(dst, src); \
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2); \
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 7); \
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
|
||||
break; \
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -9,11 +9,11 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(reg));
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
if (abrt) return 1;
|
||||
setsub8(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
static int opCMPXCHG_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -27,11 +27,11 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
if (AL == temp) seteab(getr8(reg));
|
||||
if (AL == temp) seteab(getr8(cpu_reg));
|
||||
else AL = temp;
|
||||
if (abrt) return 1;
|
||||
setsub8(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -46,11 +46,11 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[reg].w);
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
if (abrt) return 1;
|
||||
setsub16(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
static int opCMPXCHG_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -64,11 +64,11 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
if (AX == temp) seteaw(cpu_state.regs[reg].w);
|
||||
if (AX == temp) seteaw(cpu_state.regs[cpu_reg].w);
|
||||
else AX = temp;
|
||||
if (abrt) return 1;
|
||||
setsub16(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -83,11 +83,11 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[reg].l);
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
if (abrt) return 1;
|
||||
setsub32(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
static int opCMPXCHG_l_a32(uint32_t fetchdat)
|
||||
|
|
@ -101,11 +101,11 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
if (EAX == temp) seteal(cpu_state.regs[reg].l);
|
||||
if (EAX == temp) seteal(cpu_state.regs[cpu_reg].l);
|
||||
else EAX = temp;
|
||||
if (abrt) return 1;
|
||||
setsub32(temp2, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 6 : 10);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 6 : 10);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -137,7 +137,7 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
|
|||
flags |= Z_FLAG;
|
||||
else
|
||||
flags &= ~Z_FLAG;
|
||||
cycles -= (mod == 3) ? 6 : 10;
|
||||
cycles -= (cpu_mod == 3) ? 6 : 10;
|
||||
return 0;
|
||||
}
|
||||
static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
||||
|
|
@ -168,7 +168,7 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
|||
flags |= Z_FLAG;
|
||||
else
|
||||
flags &= ~Z_FLAG;
|
||||
cycles -= (mod == 3) ? 6 : 10;
|
||||
cycles -= (cpu_mod == 3) ? 6 : 10;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -183,10 +183,10 @@ static int opXADD_b_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(temp + getr8(reg)); if (abrt) return 1;
|
||||
setadd8(temp, getr8(reg));
|
||||
setr8(reg, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteab(temp + getr8(cpu_reg)); if (abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
static int opXADD_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -200,10 +200,10 @@ static int opXADD_b_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(temp + getr8(reg)); if (abrt) return 1;
|
||||
setadd8(temp, getr8(reg));
|
||||
setr8(reg, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteab(temp + getr8(cpu_reg)); if (abrt) return 1;
|
||||
setadd8(temp, getr8(cpu_reg));
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -218,10 +218,10 @@ static int opXADD_w_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[reg].w); if (abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[reg].w);
|
||||
cpu_state.regs[reg].w = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
static int opXADD_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -235,10 +235,10 @@ static int opXADD_w_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + cpu_state.regs[reg].w); if (abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[reg].w);
|
||||
cpu_state.regs[reg].w = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteaw(temp + cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
setadd16(temp, cpu_state.regs[cpu_reg].w);
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -253,10 +253,10 @@ static int opXADD_l_a16(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[reg].l); if (abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[reg].l);
|
||||
cpu_state.regs[reg].l = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
static int opXADD_l_a32(uint32_t fetchdat)
|
||||
|
|
@ -270,9 +270,9 @@ static int opXADD_l_a32(uint32_t fetchdat)
|
|||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + cpu_state.regs[reg].l); if (abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[reg].l);
|
||||
cpu_state.regs[reg].l = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 4);
|
||||
seteal(temp + cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
setadd32(temp, cpu_state.regs[cpu_reg].l);
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 4);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ static int opBT_w_r_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = 0;
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[reg].w & 15))) flags |= C_FLAG;
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -18,10 +18,10 @@ static int opBT_w_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = 0;
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[reg].w & 15))) flags |= C_FLAG;
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -32,10 +32,10 @@ static int opBT_l_r_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = 0;
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[reg].l & 31))) flags |= C_FLAG;
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -46,10 +46,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = 0;
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[reg].l & 31))) flags |= C_FLAG;
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
else flags &= ~C_FLAG;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
|
|
@ -63,10 +63,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[reg].w & 15)); \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -81,10 +81,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[reg].w & 15)); \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -99,10 +99,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[reg].l & 31)); \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
@ -117,10 +117,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
|||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[reg].l & 31)); \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
flags_rebuild(); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static int opBSF_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[reg].w, (is486) ? 1 : 3);
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -36,7 +36,7 @@ static int opBSF_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
|
||||
BS_common(0, 16, 1, cpu_state.regs[reg].w, (is486) ? 1 : 3);
|
||||
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -48,7 +48,7 @@ static int opBSF_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[reg].l, (is486) ? 1 : 3);
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -60,7 +60,7 @@ static int opBSF_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
|
||||
BS_common(0, 32, 1, cpu_state.regs[reg].l, (is486) ? 1 : 3);
|
||||
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -73,7 +73,7 @@ static int opBSR_w_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[reg].w, 3);
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -85,7 +85,7 @@ static int opBSR_w_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
|
||||
BS_common(15, -1, -1, cpu_state.regs[reg].w, 3);
|
||||
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -97,7 +97,7 @@ static int opBSR_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[reg].l, 3);
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
@ -109,7 +109,7 @@ static int opBSR_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
|
||||
BS_common(31, -1, -1, cpu_state.regs[reg].l, 3);
|
||||
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
|
||||
|
||||
CLOCK_CYCLES((is486) ? 6 : 10);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -100,13 +100,13 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + 1); if (abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp - 1); if (abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
|
|
@ -114,7 +114,7 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
|
|
@ -128,7 +128,7 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
|
|
@ -141,7 +141,7 @@ static int opFF_w_a16(uint32_t fetchdat)
|
|||
case 0x30: /*PUSH w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -165,13 +165,13 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp + 1); if (abrt) return 1;
|
||||
setadd16nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(temp - 1); if (abrt) return 1;
|
||||
setsub16nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteaw(); if (abrt) return 1;
|
||||
|
|
@ -179,7 +179,7 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
|
|
@ -193,7 +193,7 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
|
|
@ -206,7 +206,7 @@ static int opFF_w_a32(uint32_t fetchdat)
|
|||
case 0x30: /*PUSH w*/
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
PUSH_W(temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -231,13 +231,13 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + 1); if (abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp - 1); if (abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
|
|
@ -245,7 +245,7 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
|
|
@ -259,7 +259,7 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
|
|
@ -272,7 +272,7 @@ static int opFF_l_a16(uint32_t fetchdat)
|
|||
case 0x30: /*PUSH l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -296,13 +296,13 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp + 1); if (abrt) return 1;
|
||||
setadd32nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x08: /*DEC l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(temp - 1); if (abrt) return 1;
|
||||
setsub32nc(temp, 1);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
new_pc = geteal(); if (abrt) return 1;
|
||||
|
|
@ -310,7 +310,7 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
|
|
@ -324,7 +324,7 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
cpu_state.pc = new_pc;
|
||||
CPU_BLOCK_END();
|
||||
if (is486) CLOCK_CYCLES(5);
|
||||
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
|
|
@ -337,7 +337,7 @@ static int opFF_l_a32(uint32_t fetchdat)
|
|||
case 0x30: /*PUSH l*/
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
PUSH_L(temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ static int opINCDEC_b_a16(uint32_t fetchdat)
|
|||
seteab(temp + 1); if (abrt) return 1;
|
||||
setadd8nc(temp, 1);
|
||||
}
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
return 0;
|
||||
}
|
||||
static int opINCDEC_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -81,6 +81,6 @@ static int opINCDEC_b_a32(uint32_t fetchdat)
|
|||
seteab(temp + 1); if (abrt) return 1;
|
||||
setadd8nc(temp, 1);
|
||||
}
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,17 +52,17 @@ static int opF6_a16(uint32_t fetchdat)
|
|||
case 0x00: /*TEST b,#8*/
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
setznp8(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
seteab(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
seteab(0 - dst); if (abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x20: /*MUL AL,b*/
|
||||
AX = AL * dst;
|
||||
|
|
@ -142,17 +142,17 @@ static int opF6_a32(uint32_t fetchdat)
|
|||
case 0x00: /*TEST b,#8*/
|
||||
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
setznp8(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT b*/
|
||||
seteab(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG b*/
|
||||
seteab(0 - dst); if (abrt) return 1;
|
||||
setsub8(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x20: /*MUL AL,b*/
|
||||
AX = AL * dst;
|
||||
|
|
@ -235,17 +235,17 @@ static int opF7_w_a16(uint32_t fetchdat)
|
|||
case 0x00: /*TEST w*/
|
||||
src = getword(); if (abrt) return 1;
|
||||
setznp16(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
seteaw(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
seteaw(0 - dst); if (abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x20: /*MUL AX,w*/
|
||||
templ = AX * dst;
|
||||
|
|
@ -321,17 +321,17 @@ static int opF7_w_a32(uint32_t fetchdat)
|
|||
case 0x00: /*TEST w*/
|
||||
src = getword(); if (abrt) return 1;
|
||||
setznp16(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT w*/
|
||||
seteaw(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x18: /*NEG w*/
|
||||
seteaw(0 - dst); if (abrt) return 1;
|
||||
setsub16(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mm);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
||||
break;
|
||||
case 0x20: /*MUL AX,w*/
|
||||
templ = AX * dst;
|
||||
|
|
@ -407,17 +407,17 @@ static int opF7_l_a16(uint32_t fetchdat)
|
|||
case 0x00: /*TEST l*/
|
||||
src = getlong(); if (abrt) return 1;
|
||||
setznp32(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
seteal(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mml);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
seteal(0 - dst); if (abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mml);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x20: /*MUL EAX,l*/
|
||||
temp64 = (uint64_t)EAX * (uint64_t)dst;
|
||||
|
|
@ -469,17 +469,17 @@ static int opF7_l_a32(uint32_t fetchdat)
|
|||
case 0x00: /*TEST l*/
|
||||
src = getlong(); if (abrt) return 1;
|
||||
setznp32(src & dst);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
break;
|
||||
case 0x10: /*NOT l*/
|
||||
seteal(~dst); if (abrt) return 1;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mml);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x18: /*NEG l*/
|
||||
seteal(0 - dst); if (abrt) return 1;
|
||||
setsub32(0, dst);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mml);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
|
||||
break;
|
||||
case 0x20: /*MUL EAX,l*/
|
||||
temp64 = (uint64_t)EAX * (uint64_t)dst;
|
||||
|
|
@ -558,11 +558,11 @@ static int opBOUND_w_a16(uint32_t fetchdat)
|
|||
int16_t low, high;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[reg].w < low) || ((int16_t)cpu_state.regs[reg].w > high))
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
x86_int(5);
|
||||
return 1;
|
||||
|
|
@ -576,11 +576,11 @@ static int opBOUND_w_a32(uint32_t fetchdat)
|
|||
int16_t low, high;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[reg].w < low) || ((int16_t)cpu_state.regs[reg].w > high))
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
x86_int(5);
|
||||
return 1;
|
||||
|
|
@ -595,11 +595,11 @@ static int opBOUND_l_a16(uint32_t fetchdat)
|
|||
int32_t low, high;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[reg].l < low) || ((int32_t)cpu_state.regs[reg].l > high))
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
x86_int(5);
|
||||
return 1;
|
||||
|
|
@ -613,11 +613,11 @@ static int opBOUND_l_a32(uint32_t fetchdat)
|
|||
int32_t low, high;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[reg].l < low) || ((int32_t)cpu_state.regs[reg].l > high))
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
x86_int(5);
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@
|
|||
#define USATW(val) (((val) < 0) ? 0 : (((val) > 65535) ? 65535 : (val)))
|
||||
|
||||
#define MMX_GETSRC() \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
src = MM[rm]; \
|
||||
src = MM[cpu_rm]; \
|
||||
CLOCK_CYCLES(1); \
|
||||
} \
|
||||
else \
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@ static int opPADDB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] += src.b[0];
|
||||
MM[reg].b[1] += src.b[1];
|
||||
MM[reg].b[2] += src.b[2];
|
||||
MM[reg].b[3] += src.b[3];
|
||||
MM[reg].b[4] += src.b[4];
|
||||
MM[reg].b[5] += src.b[5];
|
||||
MM[reg].b[6] += src.b[6];
|
||||
MM[reg].b[7] += src.b[7];
|
||||
MM[cpu_reg].b[0] += src.b[0];
|
||||
MM[cpu_reg].b[1] += src.b[1];
|
||||
MM[cpu_reg].b[2] += src.b[2];
|
||||
MM[cpu_reg].b[3] += src.b[3];
|
||||
MM[cpu_reg].b[4] += src.b[4];
|
||||
MM[cpu_reg].b[5] += src.b[5];
|
||||
MM[cpu_reg].b[6] += src.b[6];
|
||||
MM[cpu_reg].b[7] += src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -25,14 +25,14 @@ static int opPADDB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] += src.b[0];
|
||||
MM[reg].b[1] += src.b[1];
|
||||
MM[reg].b[2] += src.b[2];
|
||||
MM[reg].b[3] += src.b[3];
|
||||
MM[reg].b[4] += src.b[4];
|
||||
MM[reg].b[5] += src.b[5];
|
||||
MM[reg].b[6] += src.b[6];
|
||||
MM[reg].b[7] += src.b[7];
|
||||
MM[cpu_reg].b[0] += src.b[0];
|
||||
MM[cpu_reg].b[1] += src.b[1];
|
||||
MM[cpu_reg].b[2] += src.b[2];
|
||||
MM[cpu_reg].b[3] += src.b[3];
|
||||
MM[cpu_reg].b[4] += src.b[4];
|
||||
MM[cpu_reg].b[5] += src.b[5];
|
||||
MM[cpu_reg].b[6] += src.b[6];
|
||||
MM[cpu_reg].b[7] += src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -45,10 +45,10 @@ static int opPADDW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] += src.w[0];
|
||||
MM[reg].w[1] += src.w[1];
|
||||
MM[reg].w[2] += src.w[2];
|
||||
MM[reg].w[3] += src.w[3];
|
||||
MM[cpu_reg].w[0] += src.w[0];
|
||||
MM[cpu_reg].w[1] += src.w[1];
|
||||
MM[cpu_reg].w[2] += src.w[2];
|
||||
MM[cpu_reg].w[3] += src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -60,10 +60,10 @@ static int opPADDW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] += src.w[0];
|
||||
MM[reg].w[1] += src.w[1];
|
||||
MM[reg].w[2] += src.w[2];
|
||||
MM[reg].w[3] += src.w[3];
|
||||
MM[cpu_reg].w[0] += src.w[0];
|
||||
MM[cpu_reg].w[1] += src.w[1];
|
||||
MM[cpu_reg].w[2] += src.w[2];
|
||||
MM[cpu_reg].w[3] += src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -76,8 +76,8 @@ static int opPADDD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] += src.l[0];
|
||||
MM[reg].l[1] += src.l[1];
|
||||
MM[cpu_reg].l[0] += src.l[0];
|
||||
MM[cpu_reg].l[1] += src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -89,8 +89,8 @@ static int opPADDD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] += src.l[0];
|
||||
MM[reg].l[1] += src.l[1];
|
||||
MM[cpu_reg].l[0] += src.l[0];
|
||||
MM[cpu_reg].l[1] += src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -103,14 +103,14 @@ static int opPADDSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sb[0] = SSATB(MM[reg].sb[0] + src.sb[0]);
|
||||
MM[reg].sb[1] = SSATB(MM[reg].sb[1] + src.sb[1]);
|
||||
MM[reg].sb[2] = SSATB(MM[reg].sb[2] + src.sb[2]);
|
||||
MM[reg].sb[3] = SSATB(MM[reg].sb[3] + src.sb[3]);
|
||||
MM[reg].sb[4] = SSATB(MM[reg].sb[4] + src.sb[4]);
|
||||
MM[reg].sb[5] = SSATB(MM[reg].sb[5] + src.sb[5]);
|
||||
MM[reg].sb[6] = SSATB(MM[reg].sb[6] + src.sb[6]);
|
||||
MM[reg].sb[7] = SSATB(MM[reg].sb[7] + src.sb[7]);
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,14 +122,14 @@ static int opPADDSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sb[0] = SSATB(MM[reg].sb[0] + src.sb[0]);
|
||||
MM[reg].sb[1] = SSATB(MM[reg].sb[1] + src.sb[1]);
|
||||
MM[reg].sb[2] = SSATB(MM[reg].sb[2] + src.sb[2]);
|
||||
MM[reg].sb[3] = SSATB(MM[reg].sb[3] + src.sb[3]);
|
||||
MM[reg].sb[4] = SSATB(MM[reg].sb[4] + src.sb[4]);
|
||||
MM[reg].sb[5] = SSATB(MM[reg].sb[5] + src.sb[5]);
|
||||
MM[reg].sb[6] = SSATB(MM[reg].sb[6] + src.sb[6]);
|
||||
MM[reg].sb[7] = SSATB(MM[reg].sb[7] + src.sb[7]);
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -142,14 +142,14 @@ static int opPADDUSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = USATB(MM[reg].b[0] + src.b[0]);
|
||||
MM[reg].b[1] = USATB(MM[reg].b[1] + src.b[1]);
|
||||
MM[reg].b[2] = USATB(MM[reg].b[2] + src.b[2]);
|
||||
MM[reg].b[3] = USATB(MM[reg].b[3] + src.b[3]);
|
||||
MM[reg].b[4] = USATB(MM[reg].b[4] + src.b[4]);
|
||||
MM[reg].b[5] = USATB(MM[reg].b[5] + src.b[5]);
|
||||
MM[reg].b[6] = USATB(MM[reg].b[6] + src.b[6]);
|
||||
MM[reg].b[7] = USATB(MM[reg].b[7] + src.b[7]);
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] + src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] + src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] + src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] + src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] + src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] + src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] + src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] + src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -161,14 +161,14 @@ static int opPADDUSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = USATB(MM[reg].b[0] + src.b[0]);
|
||||
MM[reg].b[1] = USATB(MM[reg].b[1] + src.b[1]);
|
||||
MM[reg].b[2] = USATB(MM[reg].b[2] + src.b[2]);
|
||||
MM[reg].b[3] = USATB(MM[reg].b[3] + src.b[3]);
|
||||
MM[reg].b[4] = USATB(MM[reg].b[4] + src.b[4]);
|
||||
MM[reg].b[5] = USATB(MM[reg].b[5] + src.b[5]);
|
||||
MM[reg].b[6] = USATB(MM[reg].b[6] + src.b[6]);
|
||||
MM[reg].b[7] = USATB(MM[reg].b[7] + src.b[7]);
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] + src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] + src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] + src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] + src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] + src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] + src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] + src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] + src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -181,10 +181,10 @@ static int opPADDSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sw[0] = SSATW(MM[reg].sw[0] + src.sw[0]);
|
||||
MM[reg].sw[1] = SSATW(MM[reg].sw[1] + src.sw[1]);
|
||||
MM[reg].sw[2] = SSATW(MM[reg].sw[2] + src.sw[2]);
|
||||
MM[reg].sw[3] = SSATW(MM[reg].sw[3] + src.sw[3]);
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -196,10 +196,10 @@ static int opPADDSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sw[0] = SSATW(MM[reg].sw[0] + src.sw[0]);
|
||||
MM[reg].sw[1] = SSATW(MM[reg].sw[1] + src.sw[1]);
|
||||
MM[reg].sw[2] = SSATW(MM[reg].sw[2] + src.sw[2]);
|
||||
MM[reg].sw[3] = SSATW(MM[reg].sw[3] + src.sw[3]);
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -212,10 +212,10 @@ static int opPADDUSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = USATW(MM[reg].w[0] + src.w[0]);
|
||||
MM[reg].w[1] = USATW(MM[reg].w[1] + src.w[1]);
|
||||
MM[reg].w[2] = USATW(MM[reg].w[2] + src.w[2]);
|
||||
MM[reg].w[3] = USATW(MM[reg].w[3] + src.w[3]);
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] + src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] + src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] + src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] + src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -227,10 +227,10 @@ static int opPADDUSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = USATW(MM[reg].w[0] + src.w[0]);
|
||||
MM[reg].w[1] = USATW(MM[reg].w[1] + src.w[1]);
|
||||
MM[reg].w[2] = USATW(MM[reg].w[2] + src.w[2]);
|
||||
MM[reg].w[3] = USATW(MM[reg].w[3] + src.w[3]);
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] + src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] + src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] + src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] + src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -243,15 +243,15 @@ static int opPMADDWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
if (MM[reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[reg].l[0] = 0x80000000;
|
||||
if (MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[cpu_reg].l[0] = 0x80000000;
|
||||
else
|
||||
MM[reg].sl[0] = ((int32_t)MM[reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[reg].sw[1] * (int32_t)src.sw[1]);
|
||||
MM[cpu_reg].sl[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
|
||||
if (MM[reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[reg].l[1] = 0x80000000;
|
||||
if (MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[cpu_reg].l[1] = 0x80000000;
|
||||
else
|
||||
MM[reg].sl[1] = ((int32_t)MM[reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[reg].sw[3] * (int32_t)src.sw[3]);
|
||||
MM[cpu_reg].sl[1] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -263,15 +263,15 @@ static int opPMADDWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
if (MM[reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[reg].l[0] = 0x80000000;
|
||||
if (MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[cpu_reg].l[0] = 0x80000000;
|
||||
else
|
||||
MM[reg].sl[0] = ((int32_t)MM[reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[reg].sw[1] * (int32_t)src.sw[1]);
|
||||
MM[cpu_reg].sl[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
|
||||
if (MM[reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[reg].l[1] = 0x80000000;
|
||||
if (MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[cpu_reg].l[1] = 0x80000000;
|
||||
else
|
||||
MM[reg].sl[1] = ((int32_t)MM[reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[reg].sw[3] * (int32_t)src.sw[3]);
|
||||
MM[cpu_reg].sl[1] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -282,12 +282,12 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].w[0] *= MM[rm].w[0];
|
||||
MM[reg].w[1] *= MM[rm].w[1];
|
||||
MM[reg].w[2] *= MM[rm].w[2];
|
||||
MM[reg].w[3] *= MM[rm].w[3];
|
||||
MM[cpu_reg].w[0] *= MM[cpu_rm].w[0];
|
||||
MM[cpu_reg].w[1] *= MM[cpu_rm].w[1];
|
||||
MM[cpu_reg].w[2] *= MM[cpu_rm].w[2];
|
||||
MM[cpu_reg].w[3] *= MM[cpu_rm].w[3];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -296,10 +296,10 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
MM[reg].w[0] *= src.w[0];
|
||||
MM[reg].w[1] *= src.w[1];
|
||||
MM[reg].w[2] *= src.w[2];
|
||||
MM[reg].w[3] *= src.w[3];
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
MM[cpu_reg].w[3] *= src.w[3];
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -309,12 +309,12 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].w[0] *= MM[rm].w[0];
|
||||
MM[reg].w[1] *= MM[rm].w[1];
|
||||
MM[reg].w[2] *= MM[rm].w[2];
|
||||
MM[reg].w[3] *= MM[rm].w[3];
|
||||
MM[cpu_reg].w[0] *= MM[cpu_rm].w[0];
|
||||
MM[cpu_reg].w[1] *= MM[cpu_rm].w[1];
|
||||
MM[cpu_reg].w[2] *= MM[cpu_rm].w[2];
|
||||
MM[cpu_reg].w[3] *= MM[cpu_rm].w[3];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -323,10 +323,10 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
MM[reg].w[0] *= src.w[0];
|
||||
MM[reg].w[1] *= src.w[1];
|
||||
MM[reg].w[2] *= src.w[2];
|
||||
MM[reg].w[3] *= src.w[3];
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
MM[cpu_reg].w[3] *= src.w[3];
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -337,12 +337,12 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].w[0] = ((int32_t)MM[reg].sw[0] * (int32_t)MM[rm].sw[0]) >> 16;
|
||||
MM[reg].w[1] = ((int32_t)MM[reg].sw[1] * (int32_t)MM[rm].sw[1]) >> 16;
|
||||
MM[reg].w[2] = ((int32_t)MM[reg].sw[2] * (int32_t)MM[rm].sw[2]) >> 16;
|
||||
MM[reg].w[3] = ((int32_t)MM[reg].sw[3] * (int32_t)MM[rm].sw[3]) >> 16;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)MM[cpu_rm].sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)MM[cpu_rm].sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)MM[cpu_rm].sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)MM[cpu_rm].sw[3]) >> 16;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -351,10 +351,10 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
MM[reg].w[0] = ((int32_t)MM[reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[reg].w[1] = ((int32_t)MM[reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[reg].w[2] = ((int32_t)MM[reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[reg].w[3] = ((int32_t)MM[reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -364,12 +364,12 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].w[0] = ((int32_t)MM[reg].sw[0] * (int32_t)MM[rm].sw[0]) >> 16;
|
||||
MM[reg].w[1] = ((int32_t)MM[reg].sw[1] * (int32_t)MM[rm].sw[1]) >> 16;
|
||||
MM[reg].w[2] = ((int32_t)MM[reg].sw[2] * (int32_t)MM[rm].sw[2]) >> 16;
|
||||
MM[reg].w[3] = ((int32_t)MM[reg].sw[3] * (int32_t)MM[rm].sw[3]) >> 16;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)MM[cpu_rm].sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)MM[cpu_rm].sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)MM[cpu_rm].sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)MM[cpu_rm].sw[3]) >> 16;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -378,10 +378,10 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
MM[reg].w[0] = ((int32_t)MM[reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[reg].w[1] = ((int32_t)MM[reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[reg].w[2] = ((int32_t)MM[reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[reg].w[3] = ((int32_t)MM[reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -395,14 +395,14 @@ static int opPSUBB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] -= src.b[0];
|
||||
MM[reg].b[1] -= src.b[1];
|
||||
MM[reg].b[2] -= src.b[2];
|
||||
MM[reg].b[3] -= src.b[3];
|
||||
MM[reg].b[4] -= src.b[4];
|
||||
MM[reg].b[5] -= src.b[5];
|
||||
MM[reg].b[6] -= src.b[6];
|
||||
MM[reg].b[7] -= src.b[7];
|
||||
MM[cpu_reg].b[0] -= src.b[0];
|
||||
MM[cpu_reg].b[1] -= src.b[1];
|
||||
MM[cpu_reg].b[2] -= src.b[2];
|
||||
MM[cpu_reg].b[3] -= src.b[3];
|
||||
MM[cpu_reg].b[4] -= src.b[4];
|
||||
MM[cpu_reg].b[5] -= src.b[5];
|
||||
MM[cpu_reg].b[6] -= src.b[6];
|
||||
MM[cpu_reg].b[7] -= src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -414,14 +414,14 @@ static int opPSUBB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] -= src.b[0];
|
||||
MM[reg].b[1] -= src.b[1];
|
||||
MM[reg].b[2] -= src.b[2];
|
||||
MM[reg].b[3] -= src.b[3];
|
||||
MM[reg].b[4] -= src.b[4];
|
||||
MM[reg].b[5] -= src.b[5];
|
||||
MM[reg].b[6] -= src.b[6];
|
||||
MM[reg].b[7] -= src.b[7];
|
||||
MM[cpu_reg].b[0] -= src.b[0];
|
||||
MM[cpu_reg].b[1] -= src.b[1];
|
||||
MM[cpu_reg].b[2] -= src.b[2];
|
||||
MM[cpu_reg].b[3] -= src.b[3];
|
||||
MM[cpu_reg].b[4] -= src.b[4];
|
||||
MM[cpu_reg].b[5] -= src.b[5];
|
||||
MM[cpu_reg].b[6] -= src.b[6];
|
||||
MM[cpu_reg].b[7] -= src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -434,10 +434,10 @@ static int opPSUBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] -= src.w[0];
|
||||
MM[reg].w[1] -= src.w[1];
|
||||
MM[reg].w[2] -= src.w[2];
|
||||
MM[reg].w[3] -= src.w[3];
|
||||
MM[cpu_reg].w[0] -= src.w[0];
|
||||
MM[cpu_reg].w[1] -= src.w[1];
|
||||
MM[cpu_reg].w[2] -= src.w[2];
|
||||
MM[cpu_reg].w[3] -= src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -449,10 +449,10 @@ static int opPSUBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] -= src.w[0];
|
||||
MM[reg].w[1] -= src.w[1];
|
||||
MM[reg].w[2] -= src.w[2];
|
||||
MM[reg].w[3] -= src.w[3];
|
||||
MM[cpu_reg].w[0] -= src.w[0];
|
||||
MM[cpu_reg].w[1] -= src.w[1];
|
||||
MM[cpu_reg].w[2] -= src.w[2];
|
||||
MM[cpu_reg].w[3] -= src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -465,8 +465,8 @@ static int opPSUBD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] -= src.l[0];
|
||||
MM[reg].l[1] -= src.l[1];
|
||||
MM[cpu_reg].l[0] -= src.l[0];
|
||||
MM[cpu_reg].l[1] -= src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -478,8 +478,8 @@ static int opPSUBD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] -= src.l[0];
|
||||
MM[reg].l[1] -= src.l[1];
|
||||
MM[cpu_reg].l[0] -= src.l[0];
|
||||
MM[cpu_reg].l[1] -= src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -492,14 +492,14 @@ static int opPSUBSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sb[0] = SSATB(MM[reg].sb[0] - src.sb[0]);
|
||||
MM[reg].sb[1] = SSATB(MM[reg].sb[1] - src.sb[1]);
|
||||
MM[reg].sb[2] = SSATB(MM[reg].sb[2] - src.sb[2]);
|
||||
MM[reg].sb[3] = SSATB(MM[reg].sb[3] - src.sb[3]);
|
||||
MM[reg].sb[4] = SSATB(MM[reg].sb[4] - src.sb[4]);
|
||||
MM[reg].sb[5] = SSATB(MM[reg].sb[5] - src.sb[5]);
|
||||
MM[reg].sb[6] = SSATB(MM[reg].sb[6] - src.sb[6]);
|
||||
MM[reg].sb[7] = SSATB(MM[reg].sb[7] - src.sb[7]);
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -511,14 +511,14 @@ static int opPSUBSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sb[0] = SSATB(MM[reg].sb[0] - src.sb[0]);
|
||||
MM[reg].sb[1] = SSATB(MM[reg].sb[1] - src.sb[1]);
|
||||
MM[reg].sb[2] = SSATB(MM[reg].sb[2] - src.sb[2]);
|
||||
MM[reg].sb[3] = SSATB(MM[reg].sb[3] - src.sb[3]);
|
||||
MM[reg].sb[4] = SSATB(MM[reg].sb[4] - src.sb[4]);
|
||||
MM[reg].sb[5] = SSATB(MM[reg].sb[5] - src.sb[5]);
|
||||
MM[reg].sb[6] = SSATB(MM[reg].sb[6] - src.sb[6]);
|
||||
MM[reg].sb[7] = SSATB(MM[reg].sb[7] - src.sb[7]);
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -531,14 +531,14 @@ static int opPSUBUSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = USATB(MM[reg].b[0] - src.b[0]);
|
||||
MM[reg].b[1] = USATB(MM[reg].b[1] - src.b[1]);
|
||||
MM[reg].b[2] = USATB(MM[reg].b[2] - src.b[2]);
|
||||
MM[reg].b[3] = USATB(MM[reg].b[3] - src.b[3]);
|
||||
MM[reg].b[4] = USATB(MM[reg].b[4] - src.b[4]);
|
||||
MM[reg].b[5] = USATB(MM[reg].b[5] - src.b[5]);
|
||||
MM[reg].b[6] = USATB(MM[reg].b[6] - src.b[6]);
|
||||
MM[reg].b[7] = USATB(MM[reg].b[7] - src.b[7]);
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] - src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] - src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] - src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] - src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] - src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] - src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] - src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] - src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -550,14 +550,14 @@ static int opPSUBUSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = USATB(MM[reg].b[0] - src.b[0]);
|
||||
MM[reg].b[1] = USATB(MM[reg].b[1] - src.b[1]);
|
||||
MM[reg].b[2] = USATB(MM[reg].b[2] - src.b[2]);
|
||||
MM[reg].b[3] = USATB(MM[reg].b[3] - src.b[3]);
|
||||
MM[reg].b[4] = USATB(MM[reg].b[4] - src.b[4]);
|
||||
MM[reg].b[5] = USATB(MM[reg].b[5] - src.b[5]);
|
||||
MM[reg].b[6] = USATB(MM[reg].b[6] - src.b[6]);
|
||||
MM[reg].b[7] = USATB(MM[reg].b[7] - src.b[7]);
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] - src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] - src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] - src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] - src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] - src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] - src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] - src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] - src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -570,10 +570,10 @@ static int opPSUBSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sw[0] = SSATW(MM[reg].sw[0] - src.sw[0]);
|
||||
MM[reg].sw[1] = SSATW(MM[reg].sw[1] - src.sw[1]);
|
||||
MM[reg].sw[2] = SSATW(MM[reg].sw[2] - src.sw[2]);
|
||||
MM[reg].sw[3] = SSATW(MM[reg].sw[3] - src.sw[3]);
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -585,10 +585,10 @@ static int opPSUBSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].sw[0] = SSATW(MM[reg].sw[0] - src.sw[0]);
|
||||
MM[reg].sw[1] = SSATW(MM[reg].sw[1] - src.sw[1]);
|
||||
MM[reg].sw[2] = SSATW(MM[reg].sw[2] - src.sw[2]);
|
||||
MM[reg].sw[3] = SSATW(MM[reg].sw[3] - src.sw[3]);
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -601,10 +601,10 @@ static int opPSUBUSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = USATW(MM[reg].w[0] - src.w[0]);
|
||||
MM[reg].w[1] = USATW(MM[reg].w[1] - src.w[1]);
|
||||
MM[reg].w[2] = USATW(MM[reg].w[2] - src.w[2]);
|
||||
MM[reg].w[3] = USATW(MM[reg].w[3] - src.w[3]);
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] - src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] - src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] - src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] - src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -616,10 +616,10 @@ static int opPSUBUSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = USATW(MM[reg].w[0] - src.w[0]);
|
||||
MM[reg].w[1] = USATW(MM[reg].w[1] - src.w[1]);
|
||||
MM[reg].w[2] = USATW(MM[reg].w[2] - src.w[2]);
|
||||
MM[reg].w[3] = USATW(MM[reg].w[3] - src.w[3]);
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] - src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] - src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] - src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] - src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,14 +7,14 @@ static int opPCMPEQB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = (MM[reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[reg].b[1] = (MM[reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[reg].b[2] = (MM[reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[reg].b[3] = (MM[reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[reg].b[4] = (MM[reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[reg].b[5] = (MM[reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[reg].b[6] = (MM[reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[reg].b[7] = (MM[reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -27,14 +27,14 @@ static int opPCMPEQB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = (MM[reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[reg].b[1] = (MM[reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[reg].b[2] = (MM[reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[reg].b[3] = (MM[reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[reg].b[4] = (MM[reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[reg].b[5] = (MM[reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[reg].b[6] = (MM[reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[reg].b[7] = (MM[reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -48,14 +48,14 @@ static int opPCMPGTB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = (MM[reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[reg].b[1] = (MM[reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[reg].b[2] = (MM[reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[reg].b[3] = (MM[reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[reg].b[4] = (MM[reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[reg].b[5] = (MM[reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[reg].b[6] = (MM[reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[reg].b[7] = (MM[reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -68,14 +68,14 @@ static int opPCMPGTB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = (MM[reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[reg].b[1] = (MM[reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[reg].b[2] = (MM[reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[reg].b[3] = (MM[reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[reg].b[4] = (MM[reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[reg].b[5] = (MM[reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[reg].b[6] = (MM[reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[reg].b[7] = (MM[reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -89,10 +89,10 @@ static int opPCMPEQW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = (MM[reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[reg].w[1] = (MM[reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[reg].w[2] = (MM[reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[reg].w[3] = (MM[reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -105,10 +105,10 @@ static int opPCMPEQW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = (MM[reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[reg].w[1] = (MM[reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[reg].w[2] = (MM[reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[reg].w[3] = (MM[reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,10 +122,10 @@ static int opPCMPGTW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = (MM[reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[reg].w[1] = (MM[reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[reg].w[2] = (MM[reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[reg].w[3] = (MM[reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -138,10 +138,10 @@ static int opPCMPGTW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = (MM[reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[reg].w[1] = (MM[reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[reg].w[2] = (MM[reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[reg].w[3] = (MM[reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -155,8 +155,8 @@ static int opPCMPEQD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = (MM[reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[reg].l[1] = (MM[reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -169,8 +169,8 @@ static int opPCMPEQD_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = (MM[reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[reg].l[1] = (MM[reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -184,8 +184,8 @@ static int opPCMPGTD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = (MM[reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[reg].l[1] = (MM[reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -198,8 +198,8 @@ static int opPCMPGTD_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = (MM[reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[reg].l[1] = (MM[reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ static int opPAND_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q &= src.q;
|
||||
MM[cpu_reg].q &= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPAND_a32(uint32_t fetchdat)
|
||||
|
|
@ -17,7 +17,7 @@ static int opPAND_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q &= src.q;
|
||||
MM[cpu_reg].q &= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ static int opPANDN_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q = ~MM[reg].q & src.q;
|
||||
MM[cpu_reg].q = ~MM[cpu_reg].q & src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPANDN_a32(uint32_t fetchdat)
|
||||
|
|
@ -40,7 +40,7 @@ static int opPANDN_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q = ~MM[reg].q & src.q;
|
||||
MM[cpu_reg].q = ~MM[cpu_reg].q & src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static int opPOR_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q |= src.q;
|
||||
MM[cpu_reg].q |= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPOR_a32(uint32_t fetchdat)
|
||||
|
|
@ -63,7 +63,7 @@ static int opPOR_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q |= src.q;
|
||||
MM[cpu_reg].q |= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -75,7 +75,7 @@ static int opPXOR_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q ^= src.q;
|
||||
MM[cpu_reg].q ^= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPXOR_a32(uint32_t fetchdat)
|
||||
|
|
@ -86,6 +86,6 @@ static int opPXOR_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].q ^= src.q;
|
||||
MM[cpu_reg].q ^= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,10 +3,10 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].l[0] = cpu_state.regs[rm].l;
|
||||
MM[reg].l[1] = 0;
|
||||
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -14,8 +14,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, eaaddr); if (abrt) return 1;
|
||||
MM[reg].l[0] = dst;
|
||||
MM[reg].l[1] = 0;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -26,10 +26,10 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].l[0] = cpu_state.regs[rm].l;
|
||||
MM[reg].l[1] = 0;
|
||||
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -37,8 +37,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, eaaddr); if (abrt) return 1;
|
||||
MM[reg].l[0] = dst;
|
||||
MM[reg].l[1] = 0;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -50,15 +50,15 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].l = MM[reg].l[0];
|
||||
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
|
||||
writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 1;
|
||||
writememl(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -68,15 +68,15 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].l = MM[reg].l[0];
|
||||
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
|
||||
writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 1;
|
||||
writememl(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -87,9 +87,9 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].q = MM[rm].q;
|
||||
MM[cpu_reg].q = MM[cpu_rm].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -97,7 +97,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, eaaddr); if (abrt) return 1;
|
||||
MM[reg].q = dst;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -107,9 +107,9 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].q = MM[rm].q;
|
||||
MM[cpu_reg].q = MM[cpu_rm].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -117,7 +117,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, eaaddr); if (abrt) return 1;
|
||||
MM[reg].q = dst;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -128,15 +128,15 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[rm].q = MM[reg].q;
|
||||
MM[cpu_rm].q = MM[cpu_reg].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
writememq(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 1;
|
||||
writememq(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -146,15 +146,15 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[rm].q = MM[reg].q;
|
||||
MM[cpu_rm].q = MM[cpu_reg].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
writememq(easeg, eaaddr, MM[reg].q); if (abrt) return 1;
|
||||
writememq(easeg, eaaddr, MM[cpu_reg].q); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].l[1] = MM[rm].l[0];
|
||||
MM[cpu_reg].l[1] = MM[cpu_rm].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -13,7 +13,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, eaaddr); if (abrt) return 0;
|
||||
MM[reg].l[1] = src;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -24,9 +24,9 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
MMX_ENTER();
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[reg].l[1] = MM[rm].l[0];
|
||||
MM[cpu_reg].l[1] = MM[cpu_rm].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -34,7 +34,7 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, eaaddr); if (abrt) return 0;
|
||||
MM[reg].l[1] = src;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -49,8 +49,8 @@ static int opPUNPCKHDQ_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = MM[reg].l[1];
|
||||
MM[reg].l[1] = src.l[1];
|
||||
MM[cpu_reg].l[0] = MM[cpu_reg].l[1];
|
||||
MM[cpu_reg].l[1] = src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -62,8 +62,8 @@ static int opPUNPCKHDQ_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].l[0] = MM[reg].l[1];
|
||||
MM[reg].l[1] = src.l[1];
|
||||
MM[cpu_reg].l[0] = MM[cpu_reg].l[1];
|
||||
MM[cpu_reg].l[1] = src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -76,14 +76,14 @@ static int opPUNPCKLBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[7] = src.b[3];
|
||||
MM[reg].b[6] = MM[reg].b[3];
|
||||
MM[reg].b[5] = src.b[2];
|
||||
MM[reg].b[4] = MM[reg].b[2];
|
||||
MM[reg].b[3] = src.b[1];
|
||||
MM[reg].b[2] = MM[reg].b[1];
|
||||
MM[reg].b[1] = src.b[0];
|
||||
MM[reg].b[0] = MM[reg].b[0];
|
||||
MM[cpu_reg].b[7] = src.b[3];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[3];
|
||||
MM[cpu_reg].b[5] = src.b[2];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[2];
|
||||
MM[cpu_reg].b[3] = src.b[1];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[1];
|
||||
MM[cpu_reg].b[1] = src.b[0];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -95,14 +95,14 @@ static int opPUNPCKLBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[7] = src.b[3];
|
||||
MM[reg].b[6] = MM[reg].b[3];
|
||||
MM[reg].b[5] = src.b[2];
|
||||
MM[reg].b[4] = MM[reg].b[2];
|
||||
MM[reg].b[3] = src.b[1];
|
||||
MM[reg].b[2] = MM[reg].b[1];
|
||||
MM[reg].b[1] = src.b[0];
|
||||
MM[reg].b[0] = MM[reg].b[0];
|
||||
MM[cpu_reg].b[7] = src.b[3];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[3];
|
||||
MM[cpu_reg].b[5] = src.b[2];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[2];
|
||||
MM[cpu_reg].b[3] = src.b[1];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[1];
|
||||
MM[cpu_reg].b[1] = src.b[0];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -115,14 +115,14 @@ static int opPUNPCKHBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = MM[reg].b[4];
|
||||
MM[reg].b[1] = src.b[4];
|
||||
MM[reg].b[2] = MM[reg].b[5];
|
||||
MM[reg].b[3] = src.b[5];
|
||||
MM[reg].b[4] = MM[reg].b[6];
|
||||
MM[reg].b[5] = src.b[6];
|
||||
MM[reg].b[6] = MM[reg].b[7];
|
||||
MM[reg].b[7] = src.b[7];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[4];
|
||||
MM[cpu_reg].b[1] = src.b[4];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[5];
|
||||
MM[cpu_reg].b[3] = src.b[5];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[6];
|
||||
MM[cpu_reg].b[5] = src.b[6];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[7];
|
||||
MM[cpu_reg].b[7] = src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -134,14 +134,14 @@ static int opPUNPCKHBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].b[0] = MM[reg].b[4];
|
||||
MM[reg].b[1] = src.b[4];
|
||||
MM[reg].b[2] = MM[reg].b[5];
|
||||
MM[reg].b[3] = src.b[5];
|
||||
MM[reg].b[4] = MM[reg].b[6];
|
||||
MM[reg].b[5] = src.b[6];
|
||||
MM[reg].b[6] = MM[reg].b[7];
|
||||
MM[reg].b[7] = src.b[7];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[4];
|
||||
MM[cpu_reg].b[1] = src.b[4];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[5];
|
||||
MM[cpu_reg].b[3] = src.b[5];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[6];
|
||||
MM[cpu_reg].b[5] = src.b[6];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[7];
|
||||
MM[cpu_reg].b[7] = src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -154,10 +154,10 @@ static int opPUNPCKLWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[3] = src.w[1];
|
||||
MM[reg].w[2] = MM[reg].w[1];
|
||||
MM[reg].w[1] = src.w[0];
|
||||
MM[reg].w[0] = MM[reg].w[0];
|
||||
MM[cpu_reg].w[3] = src.w[1];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[1];
|
||||
MM[cpu_reg].w[1] = src.w[0];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -169,10 +169,10 @@ static int opPUNPCKLWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[3] = src.w[1];
|
||||
MM[reg].w[2] = MM[reg].w[1];
|
||||
MM[reg].w[1] = src.w[0];
|
||||
MM[reg].w[0] = MM[reg].w[0];
|
||||
MM[cpu_reg].w[3] = src.w[1];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[1];
|
||||
MM[cpu_reg].w[1] = src.w[0];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -185,10 +185,10 @@ static int opPUNPCKHWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = MM[reg].w[2];
|
||||
MM[reg].w[1] = src.w[2];
|
||||
MM[reg].w[2] = MM[reg].w[3];
|
||||
MM[reg].w[3] = src.w[3];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[2];
|
||||
MM[cpu_reg].w[1] = src.w[2];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[3];
|
||||
MM[cpu_reg].w[3] = src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -200,10 +200,10 @@ static int opPUNPCKHWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[reg].w[0] = MM[reg].w[2];
|
||||
MM[reg].w[1] = src.w[2];
|
||||
MM[reg].w[2] = MM[reg].w[3];
|
||||
MM[reg].w[3] = src.w[3];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[2];
|
||||
MM[cpu_reg].w[1] = src.w[2];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[3];
|
||||
MM[cpu_reg].w[3] = src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -215,16 +215,16 @@ static int opPACKSSWB_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[reg].sb[7] = SSATB(src.sw[3]);
|
||||
MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -235,16 +235,16 @@ static int opPACKSSWB_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[reg].sb[7] = SSATB(src.sw[3]);
|
||||
MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -256,16 +256,16 @@ static int opPACKUSWB_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[reg].b[4] = USATB(src.sw[0]);
|
||||
MM[reg].b[5] = USATB(src.sw[1]);
|
||||
MM[reg].b[6] = USATB(src.sw[2]);
|
||||
MM[reg].b[7] = USATB(src.sw[3]);
|
||||
MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -276,16 +276,16 @@ static int opPACKUSWB_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[reg].b[4] = USATB(src.sw[0]);
|
||||
MM[reg].b[5] = USATB(src.sw[1]);
|
||||
MM[reg].b[6] = USATB(src.sw[2]);
|
||||
MM[reg].b[7] = USATB(src.sw[3]);
|
||||
MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -297,12 +297,12 @@ static int opPACKSSDW_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[reg].sw[3] = SSATW(src.sl[1]);
|
||||
MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -313,12 +313,12 @@ static int opPACKSSDW_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[reg];
|
||||
dst = MM[cpu_reg];
|
||||
|
||||
MM[reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[reg].sw[3] = SSATW(src.sl[1]);
|
||||
MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#define MMX_GETSHIFT() \
|
||||
if (mod == 3) \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
shift = MM[rm].b[0]; \
|
||||
shift = MM[cpu_rm].b[0]; \
|
||||
CLOCK_CYCLES(1); \
|
||||
} \
|
||||
else \
|
||||
|
|
@ -72,13 +72,13 @@ static int opPSLLW_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] <<= shift;
|
||||
MM[reg].w[1] <<= shift;
|
||||
MM[reg].w[2] <<= shift;
|
||||
MM[reg].w[3] <<= shift;
|
||||
MM[cpu_reg].w[0] <<= shift;
|
||||
MM[cpu_reg].w[1] <<= shift;
|
||||
MM[cpu_reg].w[2] <<= shift;
|
||||
MM[cpu_reg].w[3] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -93,13 +93,13 @@ static int opPSLLW_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] <<= shift;
|
||||
MM[reg].w[1] <<= shift;
|
||||
MM[reg].w[2] <<= shift;
|
||||
MM[reg].w[3] <<= shift;
|
||||
MM[cpu_reg].w[0] <<= shift;
|
||||
MM[cpu_reg].w[1] <<= shift;
|
||||
MM[cpu_reg].w[2] <<= shift;
|
||||
MM[cpu_reg].w[3] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -115,13 +115,13 @@ static int opPSRLW_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] >>= shift;
|
||||
MM[reg].w[1] >>= shift;
|
||||
MM[reg].w[2] >>= shift;
|
||||
MM[reg].w[3] >>= shift;
|
||||
MM[cpu_reg].w[0] >>= shift;
|
||||
MM[cpu_reg].w[1] >>= shift;
|
||||
MM[cpu_reg].w[2] >>= shift;
|
||||
MM[cpu_reg].w[3] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -136,13 +136,13 @@ static int opPSRLW_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] >>= shift;
|
||||
MM[reg].w[1] >>= shift;
|
||||
MM[reg].w[2] >>= shift;
|
||||
MM[reg].w[3] >>= shift;
|
||||
MM[cpu_reg].w[0] >>= shift;
|
||||
MM[cpu_reg].w[1] >>= shift;
|
||||
MM[cpu_reg].w[2] >>= shift;
|
||||
MM[cpu_reg].w[3] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -160,10 +160,10 @@ static int opPSRAW_a16(uint32_t fetchdat)
|
|||
if (shift > 15)
|
||||
shift = 15;
|
||||
|
||||
MM[reg].sw[0] >>= shift;
|
||||
MM[reg].sw[1] >>= shift;
|
||||
MM[reg].sw[2] >>= shift;
|
||||
MM[reg].sw[3] >>= shift;
|
||||
MM[cpu_reg].sw[0] >>= shift;
|
||||
MM[cpu_reg].sw[1] >>= shift;
|
||||
MM[cpu_reg].sw[2] >>= shift;
|
||||
MM[cpu_reg].sw[3] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -179,10 +179,10 @@ static int opPSRAW_a32(uint32_t fetchdat)
|
|||
if (shift > 15)
|
||||
shift = 15;
|
||||
|
||||
MM[reg].sw[0] >>= shift;
|
||||
MM[reg].sw[1] >>= shift;
|
||||
MM[reg].sw[2] >>= shift;
|
||||
MM[reg].sw[3] >>= shift;
|
||||
MM[cpu_reg].sw[0] >>= shift;
|
||||
MM[cpu_reg].sw[1] >>= shift;
|
||||
MM[cpu_reg].sw[2] >>= shift;
|
||||
MM[cpu_reg].sw[3] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -243,11 +243,11 @@ static int opPSLLD_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] <<= shift;
|
||||
MM[reg].l[1] <<= shift;
|
||||
MM[cpu_reg].l[0] <<= shift;
|
||||
MM[cpu_reg].l[1] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -262,11 +262,11 @@ static int opPSLLD_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] <<= shift;
|
||||
MM[reg].l[1] <<= shift;
|
||||
MM[cpu_reg].l[0] <<= shift;
|
||||
MM[cpu_reg].l[1] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -282,11 +282,11 @@ static int opPSRLD_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] >>= shift;
|
||||
MM[reg].l[1] >>= shift;
|
||||
MM[cpu_reg].l[0] >>= shift;
|
||||
MM[cpu_reg].l[1] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -301,11 +301,11 @@ static int opPSRLD_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] >>= shift;
|
||||
MM[reg].l[1] >>= shift;
|
||||
MM[cpu_reg].l[0] >>= shift;
|
||||
MM[cpu_reg].l[1] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -323,8 +323,8 @@ static int opPSRAD_a16(uint32_t fetchdat)
|
|||
if (shift > 31)
|
||||
shift = 31;
|
||||
|
||||
MM[reg].sl[0] >>= shift;
|
||||
MM[reg].sl[1] >>= shift;
|
||||
MM[cpu_reg].sl[0] >>= shift;
|
||||
MM[cpu_reg].sl[1] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -340,8 +340,8 @@ static int opPSRAD_a32(uint32_t fetchdat)
|
|||
if (shift > 31)
|
||||
shift = 31;
|
||||
|
||||
MM[reg].sl[0] >>= shift;
|
||||
MM[reg].sl[1] >>= shift;
|
||||
MM[cpu_reg].sl[0] >>= shift;
|
||||
MM[cpu_reg].sl[1] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -395,9 +395,9 @@ static int opPSLLQ_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[reg].q <<= shift;
|
||||
MM[cpu_reg].q <<= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -411,9 +411,9 @@ static int opPSLLQ_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[reg].q <<= shift;
|
||||
MM[cpu_reg].q <<= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -428,9 +428,9 @@ static int opPSRLQ_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[reg].q >>= shift;
|
||||
MM[cpu_reg].q >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -444,9 +444,9 @@ static int opPSRLQ_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[reg].q >>= shift;
|
||||
MM[cpu_reg].q >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -307,16 +307,16 @@ static int opMOV_a32_EAX(uint32_t fetchdat)
|
|||
static int opLEA_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
cpu_state.regs[reg].w = eaaddr;
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].w = eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opLEA_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
cpu_state.regs[reg].w = eaaddr;
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].w = eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -324,16 +324,16 @@ static int opLEA_w_a32(uint32_t fetchdat)
|
|||
static int opLEA_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
cpu_state.regs[reg].l = eaaddr & 0xffff;
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].l = eaaddr & 0xffff;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opLEA_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
cpu_state.regs[reg].l = eaaddr;
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].l = eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -360,15 +360,15 @@ static int opXLAT_a32(uint32_t fetchdat)
|
|||
static int opMOV_b_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
setr8(rm, getr8(reg));
|
||||
setr8(cpu_rm, getr8(cpu_reg));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
|
||||
seteab(getr8(reg));
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -376,15 +376,15 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
|
|||
static int opMOV_b_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
setr8(rm, getr8(reg));
|
||||
setr8(cpu_rm, getr8(cpu_reg));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
|
||||
seteab(getr8(reg));
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -392,15 +392,15 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
|
|||
static int opMOV_w_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].w = cpu_state.regs[reg].w;
|
||||
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
|
||||
seteaw(cpu_state.regs[reg].w);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -408,15 +408,15 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
|
|||
static int opMOV_w_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].w = cpu_state.regs[reg].w;
|
||||
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
|
||||
seteaw(cpu_state.regs[reg].w);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -424,15 +424,15 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
|
|||
static int opMOV_l_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].l = cpu_state.regs[reg].l;
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
|
||||
seteal(cpu_state.regs[reg].l);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -440,15 +440,15 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
|
|||
static int opMOV_l_r_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[rm].l = cpu_state.regs[reg].l;
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
|
||||
seteal(cpu_state.regs[reg].l);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
return abrt;
|
||||
|
|
@ -457,9 +457,9 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
|
|||
static int opMOV_r_b_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
setr8(reg, getr8(rm));
|
||||
setr8(cpu_reg, getr8(cpu_rm));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -467,7 +467,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
setr8(reg, temp);
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -475,9 +475,9 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
|||
static int opMOV_r_b_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
setr8(reg, getr8(rm));
|
||||
setr8(cpu_reg, getr8(cpu_rm));
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -485,7 +485,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
setr8(reg, temp);
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -493,9 +493,9 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
|||
static int opMOV_r_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[reg].w = cpu_state.regs[rm].w;
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -503,7 +503,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -511,9 +511,9 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
|||
static int opMOV_r_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[reg].w = cpu_state.regs[rm].w;
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -521,7 +521,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -529,9 +529,9 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
|||
static int opMOV_r_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[reg].l = cpu_state.regs[rm].l;
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -539,7 +539,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -547,9 +547,9 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
|||
static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
if (mod == 3)
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[reg].l = cpu_state.regs[rm].l;
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
}
|
||||
else
|
||||
|
|
@ -557,7 +557,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -569,14 +569,14 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
if (mod == 3) \
|
||||
cpu_state.regs[reg].w = cpu_state.regs[rm].w; \
|
||||
if (cpu_mod == 3) \
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
|
||||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].w = temp; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
} \
|
||||
CLOCK_CYCLES(1); \
|
||||
|
|
@ -587,14 +587,14 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
if (mod == 3) \
|
||||
cpu_state.regs[reg].w = cpu_state.regs[rm].w; \
|
||||
if (cpu_mod == 3) \
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
|
||||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].w = temp; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
} \
|
||||
CLOCK_CYCLES(1); \
|
||||
|
|
@ -605,14 +605,14 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
if (mod == 3) \
|
||||
cpu_state.regs[reg].l = cpu_state.regs[rm].l; \
|
||||
if (cpu_mod == 3) \
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
|
||||
else \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].l = temp; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
} \
|
||||
CLOCK_CYCLES(1); \
|
||||
|
|
@ -623,14 +623,14 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat); \
|
||||
if (cond_ ## condition) \
|
||||
{ \
|
||||
if (mod == 3) \
|
||||
cpu_state.regs[reg].l = cpu_state.regs[rm].l; \
|
||||
if (cpu_mod == 3) \
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
|
||||
else \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].l = temp; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
} \
|
||||
CLOCK_CYCLES(1); \
|
||||
|
|
|
|||
|
|
@ -7,27 +7,27 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
switch (reg)
|
||||
switch (cpu_reg)
|
||||
{
|
||||
case 0:
|
||||
cpu_state.regs[rm].l = cr0;
|
||||
cpu_state.regs[cpu_rm].l = cr0;
|
||||
if (is486)
|
||||
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
|
||||
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
|
||||
break;
|
||||
case 2:
|
||||
cpu_state.regs[rm].l = cr2;
|
||||
cpu_state.regs[cpu_rm].l = cr2;
|
||||
break;
|
||||
case 3:
|
||||
cpu_state.regs[rm].l = cr3;
|
||||
cpu_state.regs[cpu_rm].l = cr3;
|
||||
break;
|
||||
case 4:
|
||||
if (cpu_hasCR4)
|
||||
{
|
||||
cpu_state.regs[rm].l = cr4;
|
||||
cpu_state.regs[cpu_rm].l = cr4;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
|
|
@ -44,27 +44,27 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
switch (reg)
|
||||
switch (cpu_reg)
|
||||
{
|
||||
case 0:
|
||||
cpu_state.regs[rm].l = cr0;
|
||||
cpu_state.regs[cpu_rm].l = cr0;
|
||||
if (is486)
|
||||
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
|
||||
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
|
||||
break;
|
||||
case 2:
|
||||
cpu_state.regs[rm].l = cr2;
|
||||
cpu_state.regs[cpu_rm].l = cr2;
|
||||
break;
|
||||
case 3:
|
||||
cpu_state.regs[rm].l = cr3;
|
||||
cpu_state.regs[cpu_rm].l = cr3;
|
||||
break;
|
||||
case 4:
|
||||
if (cpu_hasCR4)
|
||||
{
|
||||
cpu_state.regs[rm].l = cr4;
|
||||
cpu_state.regs[cpu_rm].l = cr4;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
|
|
@ -82,7 +82,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
cpu_state.regs[rm].l = dr[reg];
|
||||
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -95,7 +95,7 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
cpu_state.regs[rm].l = dr[reg];
|
||||
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -109,33 +109,33 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
switch (reg)
|
||||
switch (cpu_reg)
|
||||
{
|
||||
case 0:
|
||||
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
|
||||
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
|
||||
flushmmucache();
|
||||
cr0 = cpu_state.regs[rm].l;
|
||||
cr0 = cpu_state.regs[cpu_rm].l;
|
||||
if (cpu_16bitbus)
|
||||
cr0 |= 0x10;
|
||||
if (!(cr0 & 0x80000000))
|
||||
mmu_perm=4;
|
||||
break;
|
||||
case 2:
|
||||
cr2 = cpu_state.regs[rm].l;
|
||||
cr2 = cpu_state.regs[cpu_rm].l;
|
||||
break;
|
||||
case 3:
|
||||
cr3 = cpu_state.regs[rm].l;
|
||||
cr3 = cpu_state.regs[cpu_rm].l;
|
||||
flushmmucache();
|
||||
break;
|
||||
case 4:
|
||||
if (cpu_hasCR4)
|
||||
{
|
||||
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
|
||||
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
pclog("Bad load CR%i\n", reg);
|
||||
pclog("Bad load CR%i\n", cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
|
|
@ -152,33 +152,33 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
switch (reg)
|
||||
switch (cpu_reg)
|
||||
{
|
||||
case 0:
|
||||
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
|
||||
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
|
||||
flushmmucache();
|
||||
cr0 = cpu_state.regs[rm].l;
|
||||
cr0 = cpu_state.regs[cpu_rm].l;
|
||||
if (cpu_16bitbus)
|
||||
cr0 |= 0x10;
|
||||
if (!(cr0 & 0x80000000))
|
||||
mmu_perm=4;
|
||||
break;
|
||||
case 2:
|
||||
cr2 = cpu_state.regs[rm].l;
|
||||
cr2 = cpu_state.regs[cpu_rm].l;
|
||||
break;
|
||||
case 3:
|
||||
cr3 = cpu_state.regs[rm].l;
|
||||
cr3 = cpu_state.regs[cpu_rm].l;
|
||||
flushmmucache();
|
||||
break;
|
||||
case 4:
|
||||
if (cpu_hasCR4)
|
||||
{
|
||||
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
|
||||
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
pclog("Bad load CR%i\n", reg);
|
||||
pclog("Bad load CR%i\n", cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
|
|
@ -196,7 +196,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
dr[reg] = cpu_state.regs[rm].l;
|
||||
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -209,7 +209,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
dr[reg] = cpu_state.regs[rm].l;
|
||||
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -223,7 +223,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
cpu_state.regs[rm].l = 0;
|
||||
cpu_state.regs[cpu_rm].l = 0;
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -236,7 +236,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
|
|||
return 1;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
cpu_state.regs[rm].l = 0;
|
||||
cpu_state.regs[cpu_rm].l = 0;
|
||||
CLOCK_CYCLES(6);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static int opMOV_w_seg_a16(uint32_t fetchdat)
|
|||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 3);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_w_seg_a32(uint32_t fetchdat)
|
||||
|
|
@ -53,7 +53,7 @@ static int opMOV_w_seg_a32(uint32_t fetchdat)
|
|||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 3);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
}
|
||||
|
||||
|
|
@ -64,32 +64,32 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = ES;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = ES;
|
||||
else seteaw(ES);
|
||||
break;
|
||||
case 0x08: /*CS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = CS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = CS;
|
||||
else seteaw(CS);
|
||||
break;
|
||||
case 0x18: /*DS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = DS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = DS;
|
||||
else seteaw(DS);
|
||||
break;
|
||||
case 0x10: /*SS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = SS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = SS;
|
||||
else seteaw(SS);
|
||||
break;
|
||||
case 0x20: /*FS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = FS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = FS;
|
||||
else seteaw(FS);
|
||||
break;
|
||||
case 0x28: /*GS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = GS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = GS;
|
||||
else seteaw(GS);
|
||||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 3);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_l_seg_a32(uint32_t fetchdat)
|
||||
|
|
@ -99,32 +99,32 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
|
|||
switch (rmdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ES*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = ES;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = ES;
|
||||
else seteaw(ES);
|
||||
break;
|
||||
case 0x08: /*CS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = CS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = CS;
|
||||
else seteaw(CS);
|
||||
break;
|
||||
case 0x18: /*DS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = DS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = DS;
|
||||
else seteaw(DS);
|
||||
break;
|
||||
case 0x10: /*SS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = SS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = SS;
|
||||
else seteaw(SS);
|
||||
break;
|
||||
case 0x20: /*FS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = FS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = FS;
|
||||
else seteaw(FS);
|
||||
break;
|
||||
case 0x28: /*GS*/
|
||||
if (mod == 3) cpu_state.regs[rm].l = GS;
|
||||
if (cpu_mod == 3) cpu_state.regs[cpu_rm].l = GS;
|
||||
else seteaw(GS);
|
||||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 3);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 3);
|
||||
return abrt;
|
||||
}
|
||||
|
||||
|
|
@ -164,7 +164,7 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
|||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_seg_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -203,7 +203,7 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
|||
break;
|
||||
}
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return abrt;
|
||||
}
|
||||
|
||||
|
|
@ -213,11 +213,11 @@ static int opLDS_w_a16(uint32_t fetchdat)
|
|||
uint16_t addr, seg;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = addr;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
@ -227,11 +227,11 @@ static int opLDS_w_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = addr;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
@ -242,11 +242,11 @@ static int opLDS_l_a16(uint32_t fetchdat)
|
|||
uint16_t seg;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = addr;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
@ -257,11 +257,11 @@ static int opLDS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = addr;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 0;
|
||||
|
|
@ -272,11 +272,11 @@ static int opLSS_w_a16(uint32_t fetchdat)
|
|||
uint16_t addr, seg;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = addr;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 1;
|
||||
|
|
@ -286,11 +286,11 @@ static int opLSS_w_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = addr;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 1;
|
||||
|
|
@ -301,11 +301,11 @@ static int opLSS_l_a16(uint32_t fetchdat)
|
|||
uint16_t seg;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = addr;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 1;
|
||||
|
|
@ -316,11 +316,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(mod == 3);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = addr;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
CLOCK_CYCLES(7);
|
||||
return 1;
|
||||
|
|
@ -332,11 +332,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(mod == 3); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].w = addr; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
return 0; \
|
||||
|
|
@ -347,11 +347,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t addr, seg; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(mod == 3); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].w = addr; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
return 0; \
|
||||
|
|
@ -363,11 +363,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(mod == 3); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].l = addr; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
return 0; \
|
||||
|
|
@ -379,11 +379,11 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
|||
uint16_t seg; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(mod == 3); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[reg].l = addr; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
CLOCK_CYCLES(7); \
|
||||
return 0; \
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ static int opMOVZX_w_b_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = (uint16_t)temp;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -15,7 +15,7 @@ static int opMOVZX_w_b_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = (uint16_t)temp;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -26,7 +26,7 @@ static int opMOVZX_l_b_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -37,7 +37,7 @@ static int opMOVZX_l_b_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -48,7 +48,7 @@ static int opMOVZX_w_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -59,7 +59,7 @@ static int opMOVZX_w_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -70,7 +70,7 @@ static int opMOVZX_l_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -81,7 +81,7 @@ static int opMOVZX_l_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -93,9 +93,9 @@ static int opMOVSX_w_b_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = (uint16_t)temp;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[reg].w |= 0xff00;
|
||||
cpu_state.regs[cpu_reg].w |= 0xff00;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -106,9 +106,9 @@ static int opMOVSX_w_b_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = (uint16_t)temp;
|
||||
cpu_state.regs[cpu_reg].w = (uint16_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[reg].w |= 0xff00;
|
||||
cpu_state.regs[cpu_reg].w |= 0xff00;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -119,9 +119,9 @@ static int opMOVSX_l_b_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[reg].l |= 0xffffff00;
|
||||
cpu_state.regs[cpu_reg].l |= 0xffffff00;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -132,9 +132,9 @@ static int opMOVSX_l_b_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x80)
|
||||
cpu_state.regs[reg].l |= 0xffffff00;
|
||||
cpu_state.regs[cpu_reg].l |= 0xffffff00;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -145,9 +145,9 @@ static int opMOVSX_l_w_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
cpu_state.regs[reg].l |= 0xffff0000;
|
||||
cpu_state.regs[cpu_reg].l |= 0xffff0000;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
@ -158,9 +158,9 @@ static int opMOVSX_l_w_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = (uint32_t)temp;
|
||||
cpu_state.regs[cpu_reg].l = (uint32_t)temp;
|
||||
if (temp & 0x8000)
|
||||
cpu_state.regs[reg].l |= 0xffff0000;
|
||||
cpu_state.regs[cpu_reg].l |= 0xffff0000;
|
||||
|
||||
CLOCK_CYCLES(3);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -12,9 +12,9 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].w = templ & 0xffff;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xffff;
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 14 : 17);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
|
||||
return 0;
|
||||
}
|
||||
static int opIMUL_w_iw_a32(uint32_t fetchdat)
|
||||
|
|
@ -31,9 +31,9 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].w = templ & 0xffff;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xffff;
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 14 : 17);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -51,7 +51,7 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].l = temp64 & 0xffffffff;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
|
||||
|
||||
CLOCK_CYCLES(25);
|
||||
return 0;
|
||||
|
|
@ -70,7 +70,7 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].l = temp64 & 0xffffffff;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
|
||||
|
||||
CLOCK_CYCLES(25);
|
||||
return 0;
|
||||
|
|
@ -91,9 +91,9 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].w = templ & 0xffff;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xffff;
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 14 : 17);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
|
||||
return 0;
|
||||
}
|
||||
static int opIMUL_w_ib_a32(uint32_t fetchdat)
|
||||
|
|
@ -111,9 +111,9 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].w = templ & 0xffff;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xffff;
|
||||
|
||||
CLOCK_CYCLES((mod == 3) ? 14 : 17);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -131,7 +131,7 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].l = temp64 & 0xffffffff;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
|
||||
|
||||
CLOCK_CYCLES(20);
|
||||
return 0;
|
||||
|
|
@ -150,7 +150,7 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
|
|||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
cpu_state.regs[reg].l = temp64 & 0xffffffff;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
|
||||
|
||||
CLOCK_CYCLES(20);
|
||||
return 0;
|
||||
|
|
@ -163,9 +163,9 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[reg].w * (int32_t)(int16_t)geteaw();
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = templ & 0xFFFF;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
|
|
@ -178,9 +178,9 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
|
|||
int32_t templ;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[reg].w * (int32_t)(int16_t)geteaw();
|
||||
templ = (int32_t)(int16_t)cpu_state.regs[cpu_reg].w * (int32_t)(int16_t)geteaw();
|
||||
if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = templ & 0xFFFF;
|
||||
cpu_state.regs[cpu_reg].w = templ & 0xFFFF;
|
||||
flags_rebuild();
|
||||
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
|
|
@ -194,9 +194,9 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[reg].l * (int64_t)(int32_t)geteal();
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp64 & 0xFFFFFFFF;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
|
|
@ -209,9 +209,9 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
|
|||
int64_t temp64;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[reg].l * (int64_t)(int32_t)geteal();
|
||||
temp64 = (int64_t)(int32_t)cpu_state.regs[cpu_reg].l * (int64_t)(int32_t)geteal();
|
||||
if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp64 & 0xFFFFFFFF;
|
||||
cpu_state.regs[cpu_reg].l = temp64 & 0xFFFFFFFF;
|
||||
flags_rebuild();
|
||||
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
|
||||
else flags &= ~(C_FLAG | V_FLAG);
|
||||
|
|
|
|||
|
|
@ -8,9 +8,9 @@ static int opARPL_a16(uint32_t fetchdat)
|
|||
temp_seg = geteaw(); if (abrt) return 1;
|
||||
|
||||
flags_rebuild();
|
||||
if ((temp_seg & 3) < (cpu_state.regs[reg].w & 3))
|
||||
if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
|
||||
{
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[reg].w & 3);
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
|
||||
seteaw(temp_seg); if (abrt) return 1;
|
||||
flags |= Z_FLAG;
|
||||
}
|
||||
|
|
@ -30,9 +30,9 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
temp_seg = geteaw(); if (abrt) return 1;
|
||||
|
||||
flags_rebuild();
|
||||
if ((temp_seg & 3) < (cpu_state.regs[reg].w & 3))
|
||||
if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
|
||||
{
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[reg].w & 3);
|
||||
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
|
||||
seteaw(temp_seg); if (abrt) return 1;
|
||||
flags |= Z_FLAG;
|
||||
}
|
||||
|
|
@ -78,9 +78,9 @@ static int opARPL_a32(uint32_t fetchdat)
|
|||
flags |= Z_FLAG; \
|
||||
cpl_override = 1; \
|
||||
if (is32) \
|
||||
cpu_state.regs[reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
|
||||
cpu_state.regs[cpu_reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
|
||||
else \
|
||||
cpu_state.regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
|
||||
cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
|
||||
cpl_override = 0; \
|
||||
} \
|
||||
CLOCK_CYCLES(11); \
|
||||
|
|
@ -126,16 +126,16 @@ opLAR(l_a32, fetch_ea_32, 1)
|
|||
cpl_override = 1; \
|
||||
if (is32) \
|
||||
{ \
|
||||
cpu_state.regs[reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
|
||||
cpu_state.regs[reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
|
||||
cpu_state.regs[cpu_reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
|
||||
cpu_state.regs[cpu_reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
|
||||
if (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0x80) \
|
||||
{ \
|
||||
cpu_state.regs[reg].l <<= 12; \
|
||||
cpu_state.regs[reg].l |= 0xFFF; \
|
||||
cpu_state.regs[cpu_reg].l <<= 12; \
|
||||
cpu_state.regs[cpu_reg].l |= 0xFFF; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
cpu_state.regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
|
||||
cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
|
||||
cpl_override = 0; \
|
||||
} \
|
||||
CLOCK_CYCLES(10); \
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR b,CL*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL b,CL*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR b,CL*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
|
|
@ -62,23 +62,23 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL b,CL*/ \
|
||||
seteab(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR b,CL*/ \
|
||||
seteab(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR b,CL*/ \
|
||||
temp = (int8_t)temp >> c; \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -101,7 +101,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR w, c*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -115,7 +115,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL w, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
|
|
@ -131,7 +131,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR w, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
|
|
@ -147,23 +147,23 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL w, c*/ \
|
||||
seteaw(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR w, c*/ \
|
||||
seteaw(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR w, c*/ \
|
||||
temp = (int16_t)temp >> c; \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -186,7 +186,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR l, c*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -200,7 +200,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL l, c*/ \
|
||||
temp2 = CF_SET(); \
|
||||
|
|
@ -216,7 +216,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR l, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
|
|
@ -232,23 +232,23 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||
seteal(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR l, c*/ \
|
||||
seteal(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR l, c*/ \
|
||||
temp = (int32_t)temp >> c; \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -472,7 +472,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t tempw = geteaw(); if (abrt) return 1; \
|
||||
int tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
|
||||
uint32_t templ = (tempw << 16) | cpu_state.regs[reg].w; \
|
||||
uint32_t templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
|
||||
if (count <= 16) tempw = templ >> (16 - count); \
|
||||
else tempw = (templ << count) >> 16; \
|
||||
seteaw(tempw); if (abrt) return 1; \
|
||||
|
|
@ -486,7 +486,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t templ = geteal(); if (abrt) return 1; \
|
||||
int tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
|
||||
templ = (templ << count) | (cpu_state.regs[reg].l >> (32 - count)); \
|
||||
templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
|
||||
seteal(templ); if (abrt) return 1; \
|
||||
setznp32(templ); \
|
||||
flags_rebuild(); \
|
||||
|
|
@ -499,7 +499,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint16_t tempw = geteaw(); if (abrt) return 1; \
|
||||
int tempc = (tempw >> (count - 1)) & 1; \
|
||||
uint32_t templ = tempw | (cpu_state.regs[reg].w << 16); \
|
||||
uint32_t templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
|
||||
tempw = templ >> count; \
|
||||
seteaw(tempw); if (abrt) return 1; \
|
||||
setznp16(tempw); \
|
||||
|
|
@ -512,7 +512,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
{ \
|
||||
uint32_t templ = geteal(); if (abrt) return 1; \
|
||||
int tempc = (templ >> (count - 1)) & 1; \
|
||||
templ = (templ >> count) | (cpu_state.regs[reg].l << (32 - count)); \
|
||||
templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
|
||||
seteal(templ); if (abrt) return 1; \
|
||||
setznp32(templ); \
|
||||
flags_rebuild(); \
|
||||
|
|
|
|||
|
|
@ -231,8 +231,8 @@ static int opPOPW_a16(uint32_t fetchdat)
|
|||
else SP -= 2;
|
||||
}
|
||||
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((mod == 3) ? 4 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
}
|
||||
static int opPOPW_a32(uint32_t fetchdat)
|
||||
|
|
@ -249,8 +249,8 @@ static int opPOPW_a32(uint32_t fetchdat)
|
|||
else SP -= 2;
|
||||
}
|
||||
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((mod == 3) ? 4 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
}
|
||||
|
||||
|
|
@ -268,8 +268,8 @@ static int opPOPL_a16(uint32_t fetchdat)
|
|||
else SP -= 4;
|
||||
}
|
||||
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((mod == 3) ? 4 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
}
|
||||
static int opPOPL_a32(uint32_t fetchdat)
|
||||
|
|
@ -286,8 +286,8 @@ static int opPOPL_a32(uint32_t fetchdat)
|
|||
else SP -= 4;
|
||||
}
|
||||
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((mod == 3) ? 4 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
|
||||
return abrt;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ static int opXCHG_b_a16(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(getr8(reg)); if (abrt) return 1;
|
||||
setr8(reg, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteab(getr8(cpu_reg)); if (abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opXCHG_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -13,9 +13,9 @@ static int opXCHG_b_a32(uint32_t fetchdat)
|
|||
uint8_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
seteab(getr8(reg)); if (abrt) return 1;
|
||||
setr8(reg, temp);
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteab(getr8(cpu_reg)); if (abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -24,9 +24,9 @@ static int opXCHG_w_a16(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opXCHG_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -34,9 +34,9 @@ static int opXCHG_w_a32(uint32_t fetchdat)
|
|||
uint16_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
|
||||
cpu_state.regs[reg].w = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -45,9 +45,9 @@ static int opXCHG_l_a16(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opXCHG_l_a32(uint32_t fetchdat)
|
||||
|
|
@ -55,9 +55,9 @@ static int opXCHG_l_a32(uint32_t fetchdat)
|
|||
uint32_t temp;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
|
||||
cpu_state.regs[reg].l = temp;
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 5);
|
||||
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -284,7 +284,7 @@ void loadseg(uint16_t seg, x86seg *s)
|
|||
{
|
||||
if (addr>=ldt.limit)
|
||||
{
|
||||
pclog("Bigger than LDT limit %04X %04X %02X %02X %02X\n",seg,ldt.limit, opcode, opcode2, rmdat);
|
||||
pclog("Bigger than LDT limit %04X %04X %02X %02X %02X\n",seg,ldt.limit, opcode, opcode2, 0/*rmdat*/);
|
||||
// dumppic();
|
||||
// dumpregs();
|
||||
// exit(-1);
|
||||
|
|
@ -508,7 +508,7 @@ void loadcs(uint16_t seg)
|
|||
switch (segdat[2]&0xF00)
|
||||
{
|
||||
default:
|
||||
pclog("Bad CS %02X %02X %i special descriptor %03X %04X\n",opcode,rmdat,optype,segdat[2]&0xF00,seg);
|
||||
pclog("Bad CS %02X %02X %i special descriptor %03X %04X\n",opcode,0/*rmdat*/,optype,segdat[2]&0xF00,seg);
|
||||
x86gpf(NULL,seg&~3);
|
||||
return;
|
||||
}
|
||||
|
|
@ -743,7 +743,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
|
|||
return;
|
||||
|
||||
default:
|
||||
pclog("Bad JMP CS %02X %02X %i special descriptor %03X %04X\n",opcode,rmdat,optype,segdat[2]&0xF00,seg);
|
||||
pclog("Bad JMP CS %02X %02X %i special descriptor %03X %04X\n",opcode,0/*rmdat*/,optype,segdat[2]&0xF00,seg);
|
||||
x86gpf(NULL,0);
|
||||
return;
|
||||
// dumpregs();
|
||||
|
|
|
|||
Loading…
Reference in a new issue