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Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).

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This commit is contained in:
SarahW 2016-04-20 21:39:41 +01:00
commit c81a91fd72
52 changed files with 1494 additions and 1408 deletions
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56
src/386.c
View file

@ -73,17 +73,17 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
switch (mod)
{
case 0:
eaaddr = regs[sib & 7].l;
pc++;
eaaddr = cpu_state.regs[sib & 7].l;
cpu_state.pc++;
break;
case 1:
pc++;
eaaddr = ((uint32_t)(int8_t)getbyte()) + regs[sib & 7].l;
cpu_state.pc++;
eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
// pc++;
break;
case 2:
eaaddr = (fastreadl(cs + pc + 1)) + regs[sib & 7].l;
pc += 5;
eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
cpu_state.pc += 5;
break;
}
/*SIB byte present*/
@ -96,11 +96,11 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
ea_seg = &_ss;
}
if (((sib >> 3) & 7) != 4)
eaaddr += regs[(sib >> 3) & 7].l << (sib >> 6);
eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
}
else
{
eaaddr = regs[rm].l;
eaaddr = cpu_state.regs[rm].l;
if (mod)
{
if (rm == 5 && !ssegs)
@ -112,7 +112,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
if (mod == 1)
{
eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
pc++;
cpu_state.pc++;
}
else
{
@ -151,7 +151,7 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
eaaddr = 0;
break;
case 1:
eaaddr = (uint16_t)(int8_t)(rmdat >> 8); pc++;
eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
break;
case 2:
eaaddr = getword();
@ -176,15 +176,15 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
}
}
#define fetch_ea_16(rmdat) pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 0; }
#define fetch_ea_32(rmdat) pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 0
#define fetch_ea_16(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 0; }
#define fetch_ea_32(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 0
#include "x86_flags.h"
#define getbytef() ((uint8_t)(fetchdat)); pc++
#define getwordf() ((uint16_t)(fetchdat)); pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); pc+=2
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2
extern int xout;
int oldi;
@ -238,7 +238,7 @@ void exec386(int cycs)
// oldpc2=oldpc;
opcode_realstart:
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
oldcpl=CPL;
op32=use32;
@ -248,7 +248,7 @@ dontprint=0;
ssegs = 0;
opcodestart:
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
if (!abrt)
{
@ -258,13 +258,13 @@ opcodestart:
if (output == 3)
{
pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %f %02X%02X %02X%02X %02X%02X %02X\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0xB270+0x3F5], ram[0xB270+0x3F4], ram[0xB270+0x3F7], ram[0xB270+0x3F6], ram[0xB270+0x3F9], ram[0xB270+0x3F8], ram[0x4430+0x0D49]);
pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %f %02X%02X %02X%02X %02X%02X %02X\n",CS,cs,cpu_state.pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0xB270+0x3F5], ram[0xB270+0x3F4], ram[0xB270+0x3F7], ram[0xB270+0x3F6], ram[0xB270+0x3F9], ram[0xB270+0x3F8], ram[0x4430+0x0D49]);
}
pc++;
cpu_state.pc++;
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
}
if (!use32) pc &= 0xffff;
if (!use32) cpu_state.pc &= 0xffff;
if (abrt)
{
@ -287,7 +287,7 @@ opcodestart:
{
abrt = 0;
CS = oldcs;
pc = oldpc;
cpu_state.pc = oldpc;
pclog("Double fault %i\n", ins);
pmodeint(8, 0);
if (abrt)
@ -313,18 +313,18 @@ opcodestart:
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (1 << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
}
else if (nmi && nmi_enable)
{
oldpc = pc;
oldpc = cpu_state.pc;
oldcs = CS;
// pclog("NMI\n");
x86_int(2);
@ -348,13 +348,13 @@ opcodestart:
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (temp << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
oxpc=pc;
pc=readmemw(0,addr);
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
// if (temp==0x76) pclog("INT to %04X:%04X\n",CS,pc);
}

59
src/386_common.h
View file

@ -127,59 +127,62 @@ static inline uint32_t fastreadl(uint32_t a)
static inline uint8_t getbyte()
{
pc++;
return fastreadb(cs + (pc - 1));
cpu_state.pc++;
return fastreadb(cs + (cpu_state.pc - 1));
}
static inline uint16_t getword()
{
pc+=2;
return fastreadw(cs+(pc-2));
cpu_state.pc+=2;
return fastreadw(cs+(cpu_state.pc-2));
}
static inline uint32_t getlong()
{
pc+=4;
return fastreadl(cs+(pc-4));
cpu_state.pc+=4;
return fastreadl(cs+(cpu_state.pc-4));
}
static inline uint64_t getquad()
{
pc+=8;
return fastreadl(cs+(pc-8)) | ((uint64_t)fastreadl(cs+(pc-4)) << 32);
cpu_state.pc+=8;
return fastreadl(cs+(cpu_state.pc-8)) | ((uint64_t)fastreadl(cs+(cpu_state.pc-4)) << 32);
}
static inline uint8_t geteab()
{
if (mod==3)
return (rm&4)?regs[rm&3].b.h:regs[rm&3].b.l;
if (eal_r) return *(uint8_t *)eal_r;
return readmemb(easeg,eaaddr);
if (mod == 3)
return (rm & 4) ? cpu_state.regs[rm & 3].b.h : cpu_state.regs[rm&3].b.l;
if (eal_r)
return *(uint8_t *)eal_r;
return readmemb(easeg, eaaddr);
}
static inline uint16_t geteaw()
{
if (mod==3)
return regs[rm].w;
if (mod == 3)
return cpu_state.regs[rm].w;
// cycles-=3;
if (eal_r) return *(uint16_t *)eal_r;
return readmemw(easeg,eaaddr);
if (eal_r)
return *(uint16_t *)eal_r;
return readmemw(easeg, eaaddr);
}
static inline uint32_t geteal()
{
if (mod==3)
return regs[rm].l;
if (mod == 3)
return cpu_state.regs[rm].l;
// cycles-=3;
if (eal_r) return *eal_r;
return readmeml(easeg,eaaddr);
if (eal_r)
return *eal_r;
return readmeml(easeg, eaaddr);
}
static inline uint64_t geteaq()
{
return readmemq(easeg,eaaddr);
return readmemq(easeg, eaaddr);
}
static inline uint8_t geteab_mem()
@ -203,18 +206,18 @@ static inline void seteaq(uint64_t v)
writememql(easeg, eaaddr, v);
}
#define seteab(v) if (mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v); } else if (rm&4) regs[rm&3].b.h=v; else regs[rm].b.l=v
#define seteaw(v) if (mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v); } else regs[rm].w=v
#define seteal(v) if (mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v); } else regs[rm].l=v
#define seteab(v) if (mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v); } else if (rm&4) cpu_state.regs[rm&3].b.h=v; else cpu_state.regs[rm].b.l=v
#define seteaw(v) if (mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v); } else cpu_state.regs[rm].w=v
#define seteal(v) if (mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v); } else cpu_state.regs[rm].l=v
#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v);
#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v);
#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v);
#define getbytef() ((uint8_t)(fetchdat)); pc++
#define getwordf() ((uint16_t)(fetchdat)); pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); pc+=2
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2
#define rmdat rmdat32

186
src/386_dynarec.c
View file

@ -81,17 +81,17 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
switch (mod)
{
case 0:
eaaddr = regs[sib & 7].l;
pc++;
eaaddr = cpu_state.regs[sib & 7].l;
cpu_state.pc++;
break;
case 1:
pc++;
eaaddr = ((uint32_t)(int8_t)getbyte()) + regs[sib & 7].l;
// pc++;
cpu_state.pc++;
eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
// cpu_state.pc++;
break;
case 2:
eaaddr = (fastreadl(cs + pc + 1)) + regs[sib & 7].l;
pc += 5;
eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
cpu_state.pc += 5;
break;
}
/*SIB byte present*/
@ -104,11 +104,11 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
ea_seg = &_ss;
}
if (((sib >> 3) & 7) != 4)
eaaddr += regs[(sib >> 3) & 7].l << (sib >> 6);
eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
}
else
{
eaaddr = regs[rm].l;
eaaddr = cpu_state.regs[rm].l;
if (mod)
{
if (rm == 5 && !ssegs)
@ -120,7 +120,7 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
if (mod == 1)
{
eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
pc++;
cpu_state.pc++;
}
else
{
@ -159,7 +159,7 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
eaaddr = 0;
break;
case 1:
eaaddr = (uint16_t)(int8_t)(rmdat >> 8); pc++;
eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
break;
case 2:
eaaddr = getword();
@ -184,8 +184,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
}
}
#define fetch_ea_16(rmdat) pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
#define fetch_ea_32(rmdat) pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 1
#define fetch_ea_16(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
#define fetch_ea_32(rmdat) cpu_state.pc++; mod=(rmdat >> 6) & 3; reg=(rmdat >> 3) & 7; rm = rmdat & 7; if (mod != 3) { fetch_ea_32_long(rmdat); } if (abrt) return 1
#include "x86_flags.h"
@ -194,7 +194,7 @@ void x86_int(int num)
uint32_t addr;
// pclog("x86_int %02x %04x:%04x\n", num, CS,pc);
flags_rebuild();
pc=oldpc;
cpu_state.pc=oldpc;
if (msw&1)
{
pmodeint(num,0);
@ -205,22 +205,22 @@ void x86_int(int num)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,pc);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),pc);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
addr = (num << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
oxpc=pc;
pc=readmemw(0,addr);
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
cycles-=70;
@ -244,22 +244,22 @@ void x86_int_sw(int num)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,pc);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),pc);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
addr = (num << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
oxpc=pc;
pc=readmemw(0,addr);
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
cycles -= timing_int_rm;
}
@ -300,7 +300,7 @@ int rep386(int fv)
of = flags;
// if (inrecomp) pclog("REP32 %04X %04X ",use32,rep32);
startrep:
temp=opcode2=readmemb(cs,pc); pc++;
temp=opcode2=readmemb(cs,cpu_state.pc); cpu_state.pc++;
// if (firstrepcycle && temp==0xA5) pclog("REP MOVSW %06X:%04X %06X:%04X\n",ds,SI,es,DI);
// if (inrecomp) pclog("REP %02X %04X\n",temp,ipc);
c=(rep32&0x200)?ECX:CX;
@ -311,10 +311,10 @@ int rep386(int fv)
switch (temp|rep32)
{
case 0xC3: case 0x1C3: case 0x2C3: case 0x3C3:
pc--;
cpu_state.pc--;
break;
case 0x08:
pc=ipc+1;
cpu_state.pc=ipc+1;
break;
case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
ea_seg = &_es;
@ -354,7 +354,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26C: case 0x36C: /*REP INSB*/
@ -370,7 +370,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6D: /*REP INSW*/
@ -386,7 +386,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x16D: /*REP INSL*/
@ -401,7 +401,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26D: /*REP INSW*/
@ -416,7 +416,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x36D: /*REP INSL*/
@ -431,7 +431,7 @@ int rep386(int fv)
c--;
cycles-=15;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6E: case 0x16E: /*REP OUTSB*/
@ -447,7 +447,7 @@ int rep386(int fv)
c--;
cycles-=14;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26E: case 0x36E: /*REP OUTSB*/
@ -463,7 +463,7 @@ int rep386(int fv)
c--;
cycles-=14;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6F: /*REP OUTSW*/
@ -479,7 +479,7 @@ int rep386(int fv)
c--;
cycles-=14;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x16F: /*REP OUTSL*/
@ -494,7 +494,7 @@ int rep386(int fv)
c--;
cycles -= 14;
}
if (c > 0) { firstrepcycle = 0; pc = ipc; }
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
break;
case 0x26F: /*REP OUTSW*/
@ -509,7 +509,7 @@ int rep386(int fv)
c--;
cycles-=14;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x36F: /*REP OUTSL*/
@ -524,7 +524,7 @@ int rep386(int fv)
c--;
cycles -= 14;
}
if (c > 0) { firstrepcycle = 0; pc = ipc; }
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
break;
case 0x90: case 0x190: /*REP NOP*/
@ -547,7 +547,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2A4: case 0x3A4: /*REP MOVSB*/
@ -565,7 +565,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xA5: /*REP MOVSW*/
@ -583,7 +583,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1A5: /*REP MOVSL*/
@ -602,7 +602,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2A5: /*REP MOVSW*/
@ -621,7 +621,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3A5: /*REP MOVSL*/
@ -641,7 +641,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xA6: case 0x1A6: /*REP CMPSB*/
@ -659,7 +659,7 @@ int rep386(int fv)
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2A6: case 0x3A6: /*REP CMPSB*/
@ -677,7 +677,7 @@ int rep386(int fv)
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0xA7: /*REP CMPSW*/
@ -698,7 +698,7 @@ int rep386(int fv)
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x1A7: /*REP CMPSL*/
@ -716,7 +716,7 @@ int rep386(int fv)
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2A7: /*REP CMPSW*/
@ -734,7 +734,7 @@ int rep386(int fv)
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x3A7: /*REP CMPSL*/
@ -752,7 +752,7 @@ int rep386(int fv)
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
@ -771,7 +771,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AA: case 0x3AA: /*REP STOSB*/
@ -789,7 +789,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAB: /*REP STOSW*/
@ -807,7 +807,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AB: /*REP STOSW*/
@ -825,7 +825,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1AB: /*REP STOSL*/
@ -843,7 +843,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3AB: /*REP STOSL*/
@ -861,7 +861,7 @@ int rep386(int fv)
break;
}
ins--;
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAC: case 0x1AC: /*REP LODSB*/
@ -876,7 +876,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AC: case 0x3AC: /*REP LODSB*/
@ -891,7 +891,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAD: /*REP LODSW*/
@ -906,7 +906,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1AD: /*REP LODSL*/
@ -921,7 +921,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AD: /*REP LODSW*/
@ -936,7 +936,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3AD: /*REP LODSL*/
@ -951,7 +951,7 @@ int rep386(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAE: case 0x1AE: /*REP SCASB*/
@ -974,7 +974,7 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2AE: case 0x3AE: /*REP SCASB*/
@ -998,7 +998,7 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0xAF: /*REP SCASW*/
@ -1020,7 +1020,7 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x1AF: /*REP SCASL*/
@ -1042,7 +1042,7 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2AF: /*REP SCASW*/
@ -1064,7 +1064,7 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x3AF: /*REP SCASL*/
@ -1086,13 +1086,13 @@ int rep386(int fv)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { pc=ipc; firstrepcycle=0; }
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
default:
pc = ipc+1;
cpu_state.pc = ipc+1;
//pclog("Bad REP %02X %i\n", temp, rep32 >> 8);
break;
}
@ -1127,7 +1127,7 @@ int xout=0;
#define divexcp() { \
pclog("Divide exception at %04X(%06X):%04X\n",CS,cs,pc); \
pclog("Divide exception at %04X(%06X):%04X\n",CS,cs,cpu_state.pc); \
x86_int(0); \
}
@ -1220,7 +1220,7 @@ void exec386_dynarec(int cycs)
while (cycles>0)
{
oldcs = CS;
oldpc = pc;
oldpc = cpu_state.pc;
oldcpl = CPL;
op32 = use32;
@ -1235,7 +1235,7 @@ void exec386_dynarec(int cycs)
while (!cpu_block_end)
{
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
oldcpl=CPL;
op32=use32;
@ -1243,7 +1243,7 @@ void exec386_dynarec(int cycs)
ssegs = 0;
opcodestart:
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
// if (!fetchdat)
// fatal("Dead with cache off\n");
if (!abrt)
@ -1255,13 +1255,13 @@ void exec386_dynarec(int cycs)
// if (output == 3)
// pclog("int %04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %f %02X%02X %02X%02X\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0x8f13f], ram[0x8f13e], ram[0x8f141], ram[0x8f140]);
pc++;
cpu_state.pc++;
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
}
if (!use32) pc &= 0xffff;
if (!use32) cpu_state.pc &= 0xffff;
if (((cs + pc) >> 12) != pccache)
if (((cs + cpu_state.pc) >> 12) != pccache)
CPU_BLOCK_END();
/* if (ssegs)
@ -1286,7 +1286,7 @@ void exec386_dynarec(int cycs)
}
else
{
uint32_t phys_addr = get_phys(cs+pc);
uint32_t phys_addr = get_phys(cs+cpu_state.pc);
int hash = HASH(phys_addr);
codeblock_t *block = codeblock_hash[hash];
int valid_block = 0;
@ -1299,7 +1299,7 @@ void exec386_dynarec(int cycs)
/*Block must match current CS, PC, code segment size,
and physical address. The physical address check will
also catch any page faults at this stage*/
valid_block = (block->pc == cs + pc) && (block->_cs == cs) &&
valid_block = (block->pc == cs + cpu_state.pc) && (block->_cs == cs) &&
(block->use32 == use32) && (block->phys == phys_addr) && (block->stack32 == stack32);
if (!valid_block)
{
@ -1311,7 +1311,7 @@ void exec386_dynarec(int cycs)
codeblock_t *new_block = codeblock_tree_find(phys_addr);
if (new_block)
{
valid_block = (new_block->pc == cs + pc) && (new_block->_cs == cs) &&
valid_block = (new_block->pc == cs + cpu_state.pc) && (new_block->_cs == cs) &&
(new_block->use32 == use32) && (new_block->phys == phys_addr) && (new_block->stack32 == stack32);
if (valid_block)
block = new_block;
@ -1359,7 +1359,7 @@ void exec386_dynarec(int cycs)
inrecomp=1;
code();
inrecomp=0;
if (!use32) pc &= 0xffff;
if (!use32) cpu_state.pc &= 0xffff;
// cpu_recomp_ins += block->ins;
cpu_recomp_blocks++;
/* ins += codeblock_ins[index];
@ -1368,8 +1368,8 @@ inrecomp=0;
}
else if (!abrt)
{
uint32_t start_page = pc >> 12;
uint32_t start_pc = pc;
uint32_t start_page = cpu_state.pc >> 12;
uint32_t start_pc = cpu_state.pc;
// pclog("Hash %08x %i\n", codeblock_hash_pc[HASH(cs + pc)], codeblock_page_dirty[(cs + pc) >> 12]);
cpu_block_end = 0;
@ -1384,7 +1384,7 @@ inrecomp=0;
while (!cpu_block_end)
{
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
oldcpl=CPL;
op32=use32;
@ -1392,7 +1392,7 @@ inrecomp=0;
ssegs = 0;
opcodestart_compile:
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
// if (fetchdat == 0xffffffff)
// fatal("Dead ffffffff\n");
// if (!fetchdat)
@ -1406,9 +1406,9 @@ inrecomp=0;
// if (output == 3)
// pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %08x %08x\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, cs+pc, pccache);
pc++;
cpu_state.pc++;
codegen_generate_call(opcode, x86_opcodes[(opcode | op32) & 0x3ff], fetchdat, pc, pc-1);
codegen_generate_call(opcode, x86_opcodes[(opcode | op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
@ -1416,13 +1416,13 @@ inrecomp=0;
break;
}
if (!use32) pc &= 0xffff;
if (!use32) cpu_state.pc &= 0xffff;
/*Cap source code at 4000 bytes per block; this
will prevent any block from spanning more than
2 pages. In practice this limit will never be
hit, as host block size is only 2kB*/
if ((pc - start_pc) > 4000)
if ((cpu_state.pc - start_pc) > 4000)
CPU_BLOCK_END();
if (trap)
@ -1467,7 +1467,7 @@ inrecomp=0;
{
abrt = 0;
CS = oldcs;
pc = oldpc;
cpu_state.pc = oldpc;
pclog("Double fault %i\n", ins);
pmodeint(8, 0);
if (abrt)
@ -1493,12 +1493,12 @@ inrecomp=0;
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr = (1 << 2) + idt.base;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
}
@ -1518,13 +1518,13 @@ inrecomp=0;
{
writememw(ss,(SP-2)&0xFFFF,flags);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr=temp<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
oxpc=pc;
pc=readmemw(0,addr);
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
}
}

4
src/386_dynarec_ops.c
View file

@ -45,8 +45,8 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
}
}
#define fetch_ea_16(rmdat) pc++; if (mod != 3) fetch_ea_16_long(rmdat);
#define fetch_ea_32(rmdat) pc++; if (mod != 3) fetch_ea_32_long(rmdat);
#define fetch_ea_16(rmdat) cpu_state.pc++; if (mod != 3) fetch_ea_16_long(rmdat);
#define fetch_ea_32(rmdat) cpu_state.pc++; if (mod != 3) fetch_ea_32_long(rmdat);

12
src/386_ops.h
View file

@ -6,7 +6,7 @@
{ \
if ((cond)) \
{ \
pc = oldpc; \
cpu_state.pc = oldpc; \
x86illegal(); \
return 0; \
} \
@ -142,7 +142,7 @@ static inline uint32_t POP_L_seg(uint32_t seg)
static int ILLEGAL(uint32_t fetchdat)
{
pc = oldpc;
cpu_state.pc = oldpc;
// fatal("Illegal instruction %08X\n", fetchdat);
x86illegal();
@ -152,28 +152,28 @@ static int ILLEGAL(uint32_t fetchdat)
static int op0F_w_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
pc++;
cpu_state.pc++;
return x86_opcodes_0f[opcode](fetchdat >> 8);
}
static int op0F_l_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
pc++;
cpu_state.pc++;
return x86_opcodes_0f[opcode | 0x100](fetchdat >> 8);
}
static int op0F_w_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
pc++;
cpu_state.pc++;
return x86_opcodes_0f[opcode | 0x200](fetchdat >> 8);
}
static int op0F_l_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
pc++;
cpu_state.pc++;
return x86_opcodes_0f[opcode | 0x300](fetchdat >> 8);
}

315
src/808x.c
View file

@ -43,7 +43,7 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val);
#undef readmemw
uint8_t readmemb(uint32_t a)
{
if (a!=(cs+pc)) memcycs+=4;
if (a!=(cs+cpu_state.pc)) memcycs+=4;
if (readlookup2[(a)>>12]==-1) return readmembl(a);
else return *(uint8_t *)(readlookup2[(a) >> 12] + (a));
}
@ -56,7 +56,7 @@ uint8_t readmembf(uint32_t a)
uint16_t readmemw(uint32_t s, uint16_t a)
{
if (a!=(cs+pc)) memcycs+=(8>>is8086);
if (a!=(cs+cpu_state.pc)) memcycs+=(8>>is8086);
if ((readlookup2[((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)) return readmemwl(s,a);
else return *(uint16_t *)(readlookup2[(s + a) >> 12] + s + a);
}
@ -141,12 +141,12 @@ inline uint8_t FETCH()
cycles-=(4-(fetchcycles&3));
fetchclocks+=(4-(fetchcycles&3));
fetchcycles=4;
temp=readmembf(cs+pc);
prefetchpc=pc=pc+1;
temp=readmembf(cs+cpu_state.pc);
prefetchpc = cpu_state.pc = cpu_state.pc + 1;
// if (output) printf(" FETCH %04X:%04X %02X %04X %04X %i\n",CS,pc-1,temp,pc,prefetchpc,prefetchw);
if (is8086 && (pc&1))
if (is8086 && (cpu_state.pc&1))
{
prefetchqueue[0]=readmembf(cs+pc);
prefetchqueue[0]=readmembf(cs+cpu_state.pc);
// if (output) printf(" PREFETCHED from %04X:%04X %02X 8086\n",CS,prefetchpc,prefetchqueue[prefetchw]);
prefetchpc++;
prefetchw++;
@ -164,7 +164,7 @@ inline uint8_t FETCH()
// if (output) printf("PREFETCH %04X:%04X %02X %04X %04X %i\n",CS,pc,temp,pc,prefetchpc,prefetchw);
fetchcycles-=4;
// fetchclocks+=4;
pc++;
cpu_state.pc++;
}
// if (output) printf("%i\n",fetchcycles);
return temp;
@ -239,7 +239,7 @@ inline void FETCHCLEAR()
}
prefetchw=(is8086)?6:4;*/
// fetchcycles=0;
prefetchpc=pc;
prefetchpc=cpu_state.pc;
prefetchw=0;
memcycs=cycdiff-cycles;
fetchclocks=0;
@ -392,33 +392,35 @@ static void fetcheal()
static inline uint8_t geteab()
{
if (mod==3)
return (rm&4)?regs[rm&3].b.h:regs[rm&3].b.l;
if (mod == 3)
return (rm & 4) ? cpu_state.regs[rm & 3].b.h : cpu_state.regs[rm & 3].b.l;
return readmemb(easeg+eaaddr);
}
static inline uint16_t geteaw()
{
if (mod==3)
return regs[rm].w;
if (mod == 3)
return cpu_state.regs[rm].w;
// if (output==3) printf("GETEAW %04X:%08X\n",easeg,eaaddr);
return readmemw(easeg,eaaddr);
}
static inline uint16_t geteaw2()
{
if (mod==3)
return regs[rm].w;
if (mod == 3)
return cpu_state.regs[rm].w;
// printf("Getting addr from %04X:%04X %05X\n",easeg,eaaddr+2,easeg+eaaddr+2);
return readmemw(easeg,(eaaddr+2)&0xFFFF);
}
static inline void seteab(uint8_t val)
{
if (mod==3)
if (mod == 3)
{
if (rm&4) regs[rm&3].b.h=val;
else regs[rm&3].b.l=val;
if (rm & 4)
cpu_state.regs[rm & 3].b.h = val;
else
cpu_state.regs[rm & 3].b.l = val;
}
else
{
@ -428,8 +430,8 @@ static inline void seteab(uint8_t val)
static inline void seteaw(uint16_t val)
{
if (mod==3)
regs[rm].w=val;
if (mod == 3)
cpu_state.regs[rm].w = val;
else
{
writememw(easeg,eaaddr,val);
@ -437,10 +439,10 @@ static inline void seteaw(uint16_t val)
}
}
#define getr8(r) ((r&4)?regs[r&3].b.h:regs[r&3].b.l)
#define getr8(r) ((r & 4) ? cpu_state.regs[r & 3].b.h : cpu_state.regs[r & 3].b.l)
#define setr8(r,v) if (r&4) regs[r&3].b.h=v; \
else regs[r&3].b.l=v;
#define setr8(r,v) if (r & 4) cpu_state.regs[r & 3].b.h = v; \
else cpu_state.regs[r & 3].b.l = v;
/*Flags*/
@ -583,7 +585,7 @@ chdir(pcempath);
printf("EAX=%08X EBX=%08X ECX=%08X EDX=%08X\nEDI=%08X ESI=%08X EBP=%08X ESP=%08X\n",EAX,EBX,ECX,EDX,EDI,ESI,EBP,ESP);
else
printf("AX=%04X BX=%04X CX=%04X DX=%04X DI=%04X SI=%04X BP=%04X SP=%04X\n",AX,BX,CX,DX,DI,SI,BP,SP);
printf("PC=%04X CS=%04X DS=%04X ES=%04X SS=%04X FLAGS=%04X\n",pc,CS,DS,ES,SS,flags);
printf("PC=%04X CS=%04X DS=%04X ES=%04X SS=%04X FLAGS=%04X\n",cpu_state.pc,CS,DS,ES,SS,flags);
printf("%04X:%04X %04X:%04X\n",oldcs,oldpc, oldcs2, oldpc2);
printf("%i ins\n",ins);
if (is386)
@ -630,7 +632,7 @@ void resetx86()
stack32=0;
// i86_Reset();
// cs=0xFFFF0;
pc=0;
cpu_state.pc=0;
msw=0;
if (is486)
cr0 = 1 << 30;
@ -666,7 +668,7 @@ void softresetx86()
stack32=0;
// i86_Reset();
// cs=0xFFFF0;
pc=0;
cpu_state.pc=0;
msw=0;
cr0=0;
cr4 = 0;
@ -833,7 +835,7 @@ void rep(int fv)
switch (temp)
{
case 0x08:
pc=ipc+1;
cpu_state.pc=ipc+1;
cycles-=2;
FETCHCLEAR();
break;
@ -868,7 +870,7 @@ void rep(int fv)
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
break;
case 0xA4: /*REP MOVSB*/
@ -884,7 +886,7 @@ void rep(int fv)
clockhardware();
FETCHADD(17-memcycs);
}
if (IRQTEST && c>0) pc=ipc;
if (IRQTEST && c>0) cpu_state.pc=ipc;
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
// }
@ -902,7 +904,7 @@ void rep(int fv)
clockhardware();
FETCHADD(17 - memcycs);
}
if (IRQTEST && c>0) pc=ipc;
if (IRQTEST && c>0) cpu_state.pc=ipc;
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
// }
@ -924,7 +926,7 @@ void rep(int fv)
clockhardware();
FETCHADD(30 - memcycs);
}
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) pc=ipc;
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) cpu_state.pc=ipc;
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
break;
@ -944,7 +946,7 @@ void rep(int fv)
clockhardware();
FETCHADD(30 - memcycs);
}
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) pc=ipc;
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) cpu_state.pc=ipc;
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
// if (firstrepcycle) printf("REP CMPSW %06X:%04X %06X:%04X %04X %04X\n",ds,SI,es,DI,tempw,tempw2);
@ -961,7 +963,7 @@ void rep(int fv)
clockhardware();
FETCHADD(10 - memcycs);
}
if (IRQTEST && c>0) pc=ipc;
if (IRQTEST && c>0) cpu_state.pc=ipc;
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
break;
@ -977,7 +979,7 @@ void rep(int fv)
clockhardware();
FETCHADD(10 - memcycs);
}
if (IRQTEST && c>0) pc=ipc;
if (IRQTEST && c>0) cpu_state.pc=ipc;
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
// else firstrepcycle=1;
break;
@ -990,7 +992,7 @@ void rep(int fv)
c--;
cycles-=4;
}
if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
break;
case 0xAD: /*REP LODSW*/
@ -1002,7 +1004,7 @@ void rep(int fv)
c--;
cycles-=4;
}
if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
break;
case 0xAE: /*REP SCASB*/
@ -1020,7 +1022,7 @@ void rep(int fv)
cycles -= 15;
}
//if (output) printf("%i %i %i %i\n",c,(c>0),(fv==((flags&Z_FLAG)?1:0)),((c>0) && (fv==((flags&Z_FLAG)?1:0))));
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
// cycles-=120;
break;
@ -1036,11 +1038,11 @@ void rep(int fv)
c--;
cycles -= 15;
}
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
break;
default:
pc = ipc+1;
cpu_state.pc = ipc+1;
cycles-=20;
FETCHCLEAR();
// printf("Bad REP %02X\n",temp);
@ -1093,12 +1095,12 @@ void execx86(int cycs)
// if (output) printf("CLOCK %i %i\n",cycdiff,cycles);
fetchclocks=0;
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
opcodestart:
opcode=FETCH();
tempc=flags&C_FLAG;
trap=flags&T_FLAG;
pc--;
cpu_state.pc--;
// output=1;
// if (output) printf("%04X:%04X : %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %02X %04X\n",cs>>4,pc,AX,BX,CX,DX,cs>>4,ds>>4,es>>4,ss>>4,DI,SI,BP,SP,opcode,flags&~0x200,rmdat);
//#if 0
@ -1106,13 +1108,13 @@ void execx86(int cycs)
{
// if ((opcode!=0xF2 && opcode!=0xF3) || firstrepcycle)
// {
if (!skipnextprint) printf("%04X:%04X : %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %02X %04X %i %p %02X\n",cs,pc,AX,BX,CX,DX,CS,DS,ES,SS,DI,SI,BP,SP,opcode,flags, ins, ram, ram[0x1a925]);
if (!skipnextprint) printf("%04X:%04X : %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %02X %04X %i %p %02X\n",cs,cpu_state.pc,AX,BX,CX,DX,CS,DS,ES,SS,DI,SI,BP,SP,opcode,flags, ins, ram, ram[0x1a925]);
skipnextprint=0;
// ins++;
// }
}
//#endif
pc++;
cpu_state.pc++;
inhlt=0;
// if (ins==500000) { dumpregs(); exit(0); }*/
switch (opcode)
@ -1135,8 +1137,8 @@ void execx86(int cycs)
case 0x01: /*ADD 16,reg*/
fetchea();
tempw=geteaw();
setadd16(tempw,regs[reg].w);
tempw+=regs[reg].w;
setadd16(tempw, cpu_state.regs[reg].w);
tempw += cpu_state.regs[reg].w;
seteaw(tempw);
cycles-=((mod==3)?3:24);
break;
@ -1150,8 +1152,8 @@ void execx86(int cycs)
case 0x03: /*ADD reg,16*/
fetchea();
tempw=geteaw();
setadd16(regs[reg].w,tempw);
regs[reg].w+=tempw;
setadd16(cpu_state.regs[reg].w,tempw);
cpu_state.regs[reg].w+=tempw;
cycles-=((mod==3)?3:13);
break;
case 0x04: /*ADD AL,#8*/
@ -1193,7 +1195,7 @@ void execx86(int cycs)
case 0x09: /*OR 16,reg*/
fetchea();
tempw=geteaw();
tempw|=regs[reg].w;
tempw|=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
seteaw(tempw);
@ -1211,10 +1213,10 @@ void execx86(int cycs)
case 0x0B: /*OR reg,16*/
fetchea();
tempw=geteaw();
tempw|=regs[reg].w;
tempw|=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
regs[reg].w=tempw;
cpu_state.regs[reg].w=tempw;
cycles-=((mod==3)?3:13);
break;
case 0x0C: /*OR AL,#8*/
@ -1256,7 +1258,7 @@ void execx86(int cycs)
case 0x11: /*ADC 16,reg*/
fetchea();
tempw=geteaw();
tempw2=regs[reg].w;
tempw2=cpu_state.regs[reg].w;
setadc16(tempw,tempw2);
tempw+=tempw2+tempc;
seteaw(tempw);
@ -1272,8 +1274,8 @@ void execx86(int cycs)
case 0x13: /*ADC reg,16*/
fetchea();
tempw=geteaw();
setadc16(regs[reg].w,tempw);
regs[reg].w+=tempw+tempc;
setadc16(cpu_state.regs[reg].w,tempw);
cpu_state.regs[reg].w+=tempw+tempc;
cycles-=((mod==3)?3:13);
break;
case 0x14: /*ADC AL,#8*/
@ -1317,7 +1319,7 @@ void execx86(int cycs)
case 0x19: /*SBB 16,reg*/
fetchea();
tempw=geteaw();
tempw2=regs[reg].w;
tempw2=cpu_state.regs[reg].w;
// printf("%04X:%04X SBB %04X-%04X,%i\n",cs>>4,pc,tempw,tempw2,tempc);
setsbc16(tempw,tempw2);
tempw-=(tempw2+tempc);
@ -1334,11 +1336,11 @@ void execx86(int cycs)
case 0x1B: /*SBB reg,16*/
fetchea();
tempw=geteaw();
tempw2=regs[reg].w;
tempw2=cpu_state.regs[reg].w;
// printf("%04X:%04X SBB %04X-%04X,%i\n",cs>>4,pc,tempw,tempw2,tempc);
setsbc16(tempw2,tempw);
tempw2-=(tempw+tempc);
regs[reg].w=tempw2;
cpu_state.regs[reg].w=tempw2;
cycles-=((mod==3)?3:13);
break;
case 0x1C: /*SBB AL,#8*/
@ -1381,7 +1383,7 @@ void execx86(int cycs)
case 0x21: /*AND 16,reg*/
fetchea();
tempw=geteaw();
tempw&=regs[reg].w;
tempw&=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
seteaw(tempw);
@ -1399,10 +1401,10 @@ void execx86(int cycs)
case 0x23: /*AND reg,16*/
fetchea();
tempw=geteaw();
tempw&=regs[reg].w;
tempw&=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
regs[reg].w=tempw;
cpu_state.regs[reg].w=tempw;
cycles-=((mod==3)?3:13);
break;
case 0x24: /*AND AL,#8*/
@ -1459,9 +1461,9 @@ void execx86(int cycs)
case 0x29: /*SUB 16,reg*/
fetchea();
tempw=geteaw();
// printf("%04X:%04X %04X-%04X\n",cs>>4,pc,tempw,regs[reg].w);
setsub16(tempw,regs[reg].w);
tempw-=regs[reg].w;
// printf("%04X:%04X %04X-%04X\n",cs>>4,pc,tempw,cpu_state.regs[reg].w);
setsub16(tempw,cpu_state.regs[reg].w);
tempw-=cpu_state.regs[reg].w;
seteaw(tempw);
cycles-=((mod==3)?3:24);
break;
@ -1475,9 +1477,9 @@ void execx86(int cycs)
case 0x2B: /*SUB reg,16*/
fetchea();
tempw=geteaw();
// printf("%04X:%04X %04X-%04X\n",cs>>4,pc,regs[reg].w,tempw);
setsub16(regs[reg].w,tempw);
regs[reg].w-=tempw;
// printf("%04X:%04X %04X-%04X\n",cs>>4,pc,cpu_state.regs[reg].w,tempw);
setsub16(cpu_state.regs[reg].w,tempw);
cpu_state.regs[reg].w-=tempw;
cycles-=((mod==3)?3:13);
break;
case 0x2C: /*SUB AL,#8*/
@ -1533,7 +1535,7 @@ void execx86(int cycs)
case 0x31: /*XOR 16,reg*/
fetchea();
tempw=geteaw();
tempw^=regs[reg].w;
tempw^=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
seteaw(tempw);
@ -1551,10 +1553,10 @@ void execx86(int cycs)
case 0x33: /*XOR reg,16*/
fetchea();
tempw=geteaw();
tempw^=regs[reg].w;
tempw^=cpu_state.regs[reg].w;
setznp16(tempw);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
regs[reg].w=tempw;
cpu_state.regs[reg].w=tempw;
cycles-=((mod==3)?3:13);
break;
case 0x34: /*XOR AL,#8*/
@ -1602,8 +1604,8 @@ void execx86(int cycs)
case 0x39: /*CMP 16,reg*/
fetchea();
tempw=geteaw();
// if (output) printf("CMP %04X-%04X\n",tempw,regs[reg].w);
setsub16(tempw,regs[reg].w);
// if (output) printf("CMP %04X-%04X\n",tempw,cpu_state.regs[reg].w);
setsub16(tempw,cpu_state.regs[reg].w);
cycles-=((mod==3)?3:13);
break;
case 0x3A: /*CMP reg,8*/
@ -1616,8 +1618,8 @@ void execx86(int cycs)
case 0x3B: /*CMP reg,16*/
fetchea();
tempw=geteaw();
// printf("CMP %04X-%04X\n",regs[reg].w,tempw);
setsub16(regs[reg].w,tempw);
// printf("CMP %04X-%04X\n",cpu_state.regs[reg].w,tempw);
setsub16(cpu_state.regs[reg].w,tempw);
cycles-=((mod==3)?3:13);
break;
case 0x3C: /*CMP AL,#8*/
@ -1655,14 +1657,14 @@ void execx86(int cycs)
case 0x40: case 0x41: case 0x42: case 0x43: /*INC r16*/
case 0x44: case 0x45: case 0x46: case 0x47:
setadd16nc(regs[opcode&7].w,1);
regs[opcode&7].w++;
setadd16nc(cpu_state.regs[opcode&7].w,1);
cpu_state.regs[opcode&7].w++;
cycles-=3;
break;
case 0x48: case 0x49: case 0x4A: case 0x4B: /*DEC r16*/
case 0x4C: case 0x4D: case 0x4E: case 0x4F:
setsub16nc(regs[opcode&7].w,1);
regs[opcode&7].w--;
setsub16nc(cpu_state.regs[opcode&7].w,1);
cpu_state.regs[opcode&7].w--;
cycles-=3;
break;
@ -1670,14 +1672,14 @@ void execx86(int cycs)
case 0x54: case 0x55: case 0x56: case 0x57:
if (ssegs) ss=oldss;
SP-=2;
writememw(ss,SP,regs[opcode&7].w);
writememw(ss,SP,cpu_state.regs[opcode&7].w);
cycles-=15;
break;
case 0x58: case 0x59: case 0x5A: case 0x5B: /*POP r16*/
case 0x5C: case 0x5D: case 0x5E: case 0x5F:
if (ssegs) ss=oldss;
SP+=2;
regs[opcode&7].w=readmemw(ss,(SP-2)&0xFFFF);
cpu_state.regs[opcode&7].w=readmemw(ss,(SP-2)&0xFFFF);
cycles-=12;
break;
@ -1685,73 +1687,73 @@ void execx86(int cycs)
case 0x60: /*JO alias*/
case 0x70: /*JO*/
offset=(int8_t)FETCH();
if (flags&V_FLAG) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&V_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x61: /*JNO alias*/
case 0x71: /*JNO*/
offset=(int8_t)FETCH();
if (!(flags&V_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&V_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x62: /*JB alias*/
case 0x72: /*JB*/
offset=(int8_t)FETCH();
if (flags&C_FLAG) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&C_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x63: /*JNB alias*/
case 0x73: /*JNB*/
offset=(int8_t)FETCH();
if (!(flags&C_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&C_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x64: /*JE alias*/
case 0x74: /*JE*/
offset=(int8_t)FETCH();
if (flags&Z_FLAG) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&Z_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x65: /*JNE alias*/
case 0x75: /*JNE*/
offset=(int8_t)FETCH();
cycles-=4;
if (!(flags&Z_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
break;
case 0x66: /*JBE alias*/
case 0x76: /*JBE*/
offset=(int8_t)FETCH();
if (flags&(C_FLAG|Z_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&(C_FLAG|Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x67: /*JNBE alias*/
case 0x77: /*JNBE*/
offset=(int8_t)FETCH();
if (!(flags&(C_FLAG|Z_FLAG))) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&(C_FLAG|Z_FLAG))) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x68: /*JS alias*/
case 0x78: /*JS*/
offset=(int8_t)FETCH();
if (flags&N_FLAG) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&N_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x69: /*JNS alias*/
case 0x79: /*JNS*/
offset=(int8_t)FETCH();
if (!(flags&N_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&N_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6A: /*JP alias*/
case 0x7A: /*JP*/
offset=(int8_t)FETCH();
if (flags&P_FLAG) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (flags&P_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6B: /*JNP alias*/
case 0x7B: /*JNP*/
offset=(int8_t)FETCH();
if (!(flags&P_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!(flags&P_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6C: /*JL alias*/
@ -1759,7 +1761,7 @@ void execx86(int cycs)
offset=(int8_t)FETCH();
temp=(flags&N_FLAG)?1:0;
temp2=(flags&V_FLAG)?1:0;
if (temp!=temp2) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (temp!=temp2) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6D: /*JNL alias*/
@ -1767,7 +1769,7 @@ void execx86(int cycs)
offset=(int8_t)FETCH();
temp=(flags&N_FLAG)?1:0;
temp2=(flags&V_FLAG)?1:0;
if (temp==temp2) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (temp==temp2) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6E: /*JLE alias*/
@ -1775,7 +1777,7 @@ void execx86(int cycs)
offset=(int8_t)FETCH();
temp=(flags&N_FLAG)?1:0;
temp2=(flags&V_FLAG)?1:0;
if ((flags&Z_FLAG) || (temp!=temp2)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if ((flags&Z_FLAG) || (temp!=temp2)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6F: /*JNLE alias*/
@ -1783,7 +1785,7 @@ void execx86(int cycs)
offset=(int8_t)FETCH();
temp=(flags&N_FLAG)?1:0;
temp2=(flags&V_FLAG)?1:0;
if (!((flags&Z_FLAG) || (temp!=temp2))) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!((flags&Z_FLAG) || (temp!=temp2))) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
@ -1990,7 +1992,7 @@ void execx86(int cycs)
case 0x85: /*TEST w,reg*/
fetchea();
tempw=geteaw();
tempw2=regs[reg].w;
tempw2=cpu_state.regs[reg].w;
setznp16(tempw&tempw2);
flags&=~(C_FLAG|V_FLAG|A_FLAG);
cycles-=((mod==3)?3:13);
@ -2005,8 +2007,8 @@ void execx86(int cycs)
case 0x87: /*XCHG w,reg*/
fetchea();
tempw=geteaw();
seteaw(regs[reg].w);
regs[reg].w=tempw;
seteaw(cpu_state.regs[reg].w);
cpu_state.regs[reg].w=tempw;
cycles-=((mod==3)?4:25);
break;
@ -2017,7 +2019,7 @@ void execx86(int cycs)
break;
case 0x89: /*MOV w,reg*/
fetchea();
seteaw(regs[reg].w);
seteaw(cpu_state.regs[reg].w);
cycles-=((mod==3)?2:13);
break;
case 0x8A: /*MOV reg,b*/
@ -2029,7 +2031,7 @@ void execx86(int cycs)
case 0x8B: /*MOV reg,w*/
fetchea();
tempw=geteaw();
regs[reg].w=tempw;
cpu_state.regs[reg].w=tempw;
cycles-=((mod==3)?2:12);
break;
@ -2057,7 +2059,7 @@ void execx86(int cycs)
case 0x8D: /*LEA*/
fetchea();
regs[reg].w=eaaddr;
cpu_state.regs[reg].w=eaaddr;
cycles-=2;
break;
@ -2109,8 +2111,8 @@ void execx86(int cycs)
case 0x91: case 0x92: case 0x93: /*XCHG AX*/
case 0x94: case 0x95: case 0x96: case 0x97:
tempw=AX;
AX=regs[opcode&7].w;
regs[opcode&7].w=tempw;
AX=cpu_state.regs[opcode&7].w;
cpu_state.regs[opcode&7].w=tempw;
cycles-=3;
break;
@ -2126,9 +2128,9 @@ void execx86(int cycs)
tempw=getword();
tempw2=getword();
tempw3=CS;
tempw4=pc;
tempw4=cpu_state.pc;
if (ssegs) ss=oldss;
pc=tempw;
cpu_state.pc=tempw;
// printf("0x9a");
loadcs(tempw2);
writememw(ss,(SP-2)&0xFFFF,tempw3);
@ -2302,7 +2304,7 @@ void execx86(int cycs)
break;
case 0xB8: case 0xB9: case 0xBA: case 0xBB: /*MOV reg,#16*/
case 0xBC: case 0xBD: case 0xBE: case 0xBF:
regs[opcode&7].w=getword();
cpu_state.regs[opcode&7].w=getword();
cycles-=4;
break;
@ -2310,7 +2312,7 @@ void execx86(int cycs)
case 0xC2: /*RET*/
tempw=getword();
if (ssegs) ss=oldss;
pc=readmemw(ss,SP);
cpu_state.pc=readmemw(ss,SP);
// printf("C2\n");
// printf("RET to %04X\n",pc);
SP+=2+tempw;
@ -2320,7 +2322,7 @@ void execx86(int cycs)
case 0xC1: /*RET alias*/
case 0xC3: /*RET*/
if (ssegs) ss=oldss;
pc=readmemw(ss,SP);
cpu_state.pc=readmemw(ss,SP);
// printf("C3\n");
// if (output) printf("RET to %04X %05X\n",pc,ss+SP);
SP+=2;
@ -2329,14 +2331,14 @@ void execx86(int cycs)
break;
case 0xC4: /*LES*/
fetchea();
regs[reg].w=readmemw(easeg,eaaddr); //geteaw();
cpu_state.regs[reg].w=readmemw(easeg,eaaddr); //geteaw();
tempw=readmemw(easeg,(eaaddr+2)&0xFFFF); //geteaw2();
loadseg(tempw,&_es);
cycles-=24;
break;
case 0xC5: /*LDS*/
fetchea();
regs[reg].w=readmemw(easeg,eaaddr);
cpu_state.regs[reg].w=readmemw(easeg,eaaddr);
tempw=readmemw(easeg,(eaaddr+2)&0xFFFF);
loadseg(tempw,&_ds);
if (ssegs) oldds=ds;
@ -2359,7 +2361,7 @@ void execx86(int cycs)
case 0xCA: /*RETF*/
tempw=getword();
if (ssegs) ss=oldss;
pc=readmemw(ss,SP);
cpu_state.pc=readmemw(ss,SP);
// printf("CA\n");
loadcs(readmemw(ss,SP+2));
SP+=4;
@ -2370,7 +2372,7 @@ void execx86(int cycs)
case 0xC9: /*RETF alias*/
case 0xCB: /*RETF*/
if (ssegs) ss=oldss;
pc=readmemw(ss,SP);
cpu_state.pc=readmemw(ss,SP);
// printf("CB\n");
loadcs(readmemw(ss,SP+2));
SP+=4;
@ -2381,31 +2383,31 @@ void execx86(int cycs)
if (ssegs) ss=oldss;
writememw(ss,((SP-2)&0xFFFF),flags|0xF000);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),pc);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
addr=3<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
// printf("CC %04X:%04X ",CS,pc);
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
FETCHCLEAR();
// printf("%04X:%04X\n",CS,pc);
cycles-=72;
break;
case 0xCD: /*INT*/
lastpc=pc;
lastpc=cpu_state.pc;
lastcs=CS;
temp=FETCH();
if (ssegs) ss=oldss;
writememw(ss,((SP-2)&0xFFFF),flags|0xF000);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),pc);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
flags&=~T_FLAG;
SP-=6;
addr=temp<<2;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
FETCHCLEAR();
@ -2415,8 +2417,8 @@ void execx86(int cycs)
case 0xCF: /*IRET*/
if (ssegs) ss=oldss;
tempw=CS;
tempw2=pc;
pc=readmemw(ss,SP);
tempw2=cpu_state.pc;
cpu_state.pc=readmemw(ss,SP);
// printf("CF\n");
loadcs(readmemw(ss,((SP+2)&0xFFFF)));
flags=readmemw(ss,((SP+4)&0xFFFF))&0xFFF;
@ -2891,26 +2893,26 @@ void execx86(int cycs)
case 0xE0: /*LOOPNE*/
offset=(int8_t)FETCH();
CX--;
if (CX && !(flags&Z_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (CX && !(flags&Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=6;
break;
case 0xE1: /*LOOPE*/
offset=(int8_t)FETCH();
CX--;
if (CX && (flags&Z_FLAG)) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (CX && (flags&Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=6;
break;
case 0xE2: /*LOOP*/
// printf("LOOP start\n");
offset=(int8_t)FETCH();
CX--;
if (CX) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (CX) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=5;
// printf("LOOP end!\n");
break;
case 0xE3: /*JCXZ*/
offset=(int8_t)FETCH();
if (!CX) { pc+=offset; cycles-=12; FETCHCLEAR(); }
if (!CX) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=6;
break;
@ -2941,23 +2943,24 @@ void execx86(int cycs)
tempw=getword();
if (ssegs) ss=oldss;
// writememb(ss+((SP-1)&0xFFFF),pc>>8);
writememw(ss,((SP-2)&0xFFFF),pc);
writememw(ss,((SP-2)&0xFFFF),cpu_state.pc);
SP-=2;
pc+=tempw;
cpu_state.pc+=tempw;
cycles-=23;
FETCHCLEAR();
break;
case 0xE9: /*JMP rel 16*/
// printf("PC was %04X\n",pc);
pc+=getword();
// printf("PC now %04X\n",pc);
// pclog("PC was %04X\n",cpu_state.pc);
tempw = getword();
cpu_state.pc += tempw;
// pclog("PC now %04X\n",cpu_state.pc);
cycles-=15;
FETCHCLEAR();
break;
case 0xEA: /*JMP far*/
addr=getword();
tempw=getword();
pc=addr;
cpu_state.pc=addr;
// printf("EA\n");
loadcs(tempw);
// cs=loadcs(CS);
@ -2967,7 +2970,7 @@ void execx86(int cycs)
break;
case 0xEB: /*JMP rel*/
offset=(int8_t)FETCH();
pc+=offset;
cpu_state.pc+=offset;
cycles-=15;
FETCHCLEAR();
break;
@ -3011,7 +3014,7 @@ void execx86(int cycs)
exit(-1);
}*/
inhlt=1;
pc--;
cpu_state.pc--;
FETCHCLEAR();
cycles-=2;
break;
@ -3089,14 +3092,14 @@ void execx86(int cycs)
}
else
{
printf("DIVb BY 0 %04X:%04X\n",cs>>4,pc);
printf("DIVb BY 0 %04X:%04X\n",cs>>4,cpu_state.pc);
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,0);
cpu_state.pc=readmemw(0,0);
// printf("F6 30\n");
loadcs(readmemw(0,2));
FETCHCLEAR();
@ -3133,14 +3136,14 @@ void execx86(int cycs)
}
else
{
printf("IDIVb BY 0 %04X:%04X\n",cs>>4,pc);
printf("IDIVb BY 0 %04X:%04X\n",cs>>4,cpu_state.pc);
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,0);
cpu_state.pc=readmemw(0,0);
// printf("F6 38\n");
loadcs(readmemw(0,2));
FETCHCLEAR();
@ -3220,14 +3223,14 @@ void execx86(int cycs)
}
else
{
printf("DIVw BY 0 %04X:%04X\n",cs>>4,pc);
printf("DIVw BY 0 %04X:%04X\n",cs>>4,cpu_state.pc);
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,0);
cpu_state.pc=readmemw(0,0);
// printf("F7 30\n");
loadcs(readmemw(0,2));
FETCHCLEAR();
@ -3247,14 +3250,14 @@ void execx86(int cycs)
}
else
{
printf("IDIVw BY 0 %04X:%04X\n",cs>>4,pc);
printf("IDIVw BY 0 %04X:%04X\n",cs>>4,cpu_state.pc);
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,0);
cpu_state.pc=readmemw(0,0);
// printf("F7 38\n");
loadcs(readmemw(0,2));
FETCHCLEAR();
@ -3341,9 +3344,9 @@ void execx86(int cycs)
case 0x10: /*CALL*/
tempw=geteaw();
if (ssegs) ss=oldss;
writememw(ss,(SP-2)&0xFFFF,pc);
writememw(ss,(SP-2)&0xFFFF,cpu_state.pc);
SP-=2;
pc=tempw;
cpu_state.pc=tempw;
// printf("FF 10\n");
cycles-=((mod==3)?20:29);
FETCHCLEAR();
@ -3352,9 +3355,9 @@ void execx86(int cycs)
tempw=readmemw(easeg,eaaddr);
tempw2=readmemw(easeg,(eaaddr+2)&0xFFFF); //geteaw2();
tempw3=CS;
tempw4=pc;
tempw4=cpu_state.pc;
if (ssegs) ss=oldss;
pc=tempw;
cpu_state.pc=tempw;
// printf("FF 18\n");
loadcs(tempw2);
writememw(ss,(SP-2)&0xFFFF,tempw3);
@ -3364,13 +3367,13 @@ void execx86(int cycs)
FETCHCLEAR();
break;
case 0x20: /*JMP*/
pc=geteaw();
cpu_state.pc=geteaw();
// printf("FF 20\n");
cycles-=((mod==3)?11:18);
FETCHCLEAR();
break;
case 0x28: /*JMP far*/
pc=readmemw(easeg,eaaddr); //geteaw();
cpu_state.pc=readmemw(easeg,eaaddr); //geteaw();
// printf("FF 28\n");
loadcs(readmemw(easeg,(eaaddr+2)&0xFFFF)); //geteaw2();
// cs=loadcs(CS);
@ -3403,7 +3406,7 @@ void execx86(int cycs)
dumpregs();
exit(-1);*/
}
pc&=0xFFFF;
cpu_state.pc&=0xFFFF;
/* if ((CS & 0xf000) == 0xa000)
{
@ -3430,7 +3433,7 @@ void execx86(int cycs)
if ((cycdiff-cycles)<memcycs) cycles-=(memcycs-(cycdiff-cycles));
if (romset==ROM_IBMPC)
{
if ((cs+pc)==0xFE4A7) /*You didn't seriously think I was going to emulate the cassette, did you?*/
if ((cs+cpu_state.pc)==0xFE4A7) /*You didn't seriously think I was going to emulate the cassette, did you?*/
{
CX=1;
BX=0x500;
@ -3448,12 +3451,12 @@ void execx86(int cycs)
// printf("TRAP!!! %04X:%04X\n",CS,pc);
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr=1<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
FETCHCLEAR();
}
@ -3462,12 +3465,12 @@ void execx86(int cycs)
// output = 3;
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr=2<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
FETCHCLEAR();
nmi_enable = 0;
@ -3477,15 +3480,15 @@ void execx86(int cycs)
temp=picinterrupt();
if (temp!=0xFF)
{
if (inhlt) pc++;
if (inhlt) cpu_state.pc++;
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,pc);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
addr=temp<<2;
flags&=~I_FLAG;
flags&=~T_FLAG;
pc=readmemw(0,addr);
cpu_state.pc=readmemw(0,addr);
// printf("INT INT INT\n");
loadcs(readmemw(0,addr+2));
FETCHCLEAR();

330
src/codegen_ops_arith.h
View file

@ -6,11 +6,11 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -25,11 +25,11 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -44,11 +44,11 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -63,11 +63,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -84,12 +84,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
return 0; \
\
dst_reg = LOAD_REG_B(fetchdat & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 8); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -105,12 +105,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
return 0; \
\
dst_reg = LOAD_REG_W(fetchdat & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 16); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -126,12 +126,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
return 0; \
\
dst_reg = LOAD_REG_L(fetchdat & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 32); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -158,11 +158,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 8); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -187,11 +187,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 16); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -216,11 +216,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 32); \
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -251,11 +251,11 @@ static uint32_t ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -279,11 +279,11 @@ static uint32_t ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -307,11 +307,11 @@ static uint32_t ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -335,12 +335,12 @@ static uint32_t ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
}
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -363,12 +363,12 @@ static uint32_t ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
} \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -391,12 +391,12 @@ static uint32_t ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
}
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -409,11 +409,11 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -423,11 +423,11 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -437,12 +437,12 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -453,11 +453,11 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@ -467,11 +467,11 @@ static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@ -481,12 +481,12 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@ -497,11 +497,11 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -511,11 +511,11 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -525,12 +525,12 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@ -551,38 +551,38 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffffff00);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
}
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_B_RELEASE(host_reg);
else
@ -606,38 +606,38 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_W_RELEASE(host_reg);
else
@ -661,38 +661,38 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_L_RELEASE(host_reg);
else
@ -718,38 +718,38 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_W_RELEASE(host_reg);
else
@ -774,38 +774,38 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_L_RELEASE(host_reg);
else

18
src/codegen_ops_jump.h
View file

@ -5,7 +5,7 @@ static uint32_t ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
if (offset & 0x80)
offset |= 0xffffff00;
STORE_IMM_ADDR_L((uintptr_t)&pc, op_pc+1+offset);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+1+offset);
return -1;
}
@ -14,7 +14,7 @@ static uint32_t ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
{
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t)&pc, (op_pc+2+offset) & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
@ -23,7 +23,7 @@ static uint32_t ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
{
uint32_t offset = fastreadl(cs + op_pc);
STORE_IMM_ADDR_L((uintptr_t)&pc, op_pc+4+offset);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}
@ -88,7 +88,7 @@ static int BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not
{
int host_reg;
switch (codegen_flags_changed ? flags_op : FLAGS_UNKNOWN)
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -114,7 +114,7 @@ static int BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
host_reg = LOAD_VAR_L((uintptr_t)&flags_res);
host_reg = LOAD_VAR_L((uintptr_t)&cpu_state.flags_res);
if (not)
TEST_NONZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
else
@ -153,7 +153,7 @@ static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not
{
int host_reg;
switch (codegen_flags_changed ? flags_op : FLAGS_UNKNOWN)
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ADD8:
@ -163,7 +163,7 @@ static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not
case FLAGS_SAR8:
case FLAGS_INC8:
case FLAGS_DEC8:
host_reg = LOAD_VAR_L((uintptr_t)&flags_res);
host_reg = LOAD_VAR_L((uintptr_t)&cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x80);
if (not)
TEST_ZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
@ -179,7 +179,7 @@ static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not
case FLAGS_SAR16:
case FLAGS_INC16:
case FLAGS_DEC16:
host_reg = LOAD_VAR_L((uintptr_t)&flags_res);
host_reg = LOAD_VAR_L((uintptr_t)&cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x8000);
if (not)
TEST_ZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
@ -195,7 +195,7 @@ static int BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not
case FLAGS_SAR32:
case FLAGS_INC32:
case FLAGS_DEC32:
host_reg = LOAD_VAR_L((uintptr_t)&flags_res);
host_reg = LOAD_VAR_L((uintptr_t)&cpu_state.flags_res);
AND_HOST_REG_IMM(host_reg, 0x80000000);
if (not)
TEST_ZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);

120
src/codegen_ops_logic.h
View file

@ -7,10 +7,10 @@
return 0; \
\
dst_reg = LOAD_REG_B(fetchdat & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -25,10 +25,10 @@
return 0; \
\
dst_reg = LOAD_REG_W(fetchdat & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -43,10 +43,10 @@
return 0; \
\
dst_reg = LOAD_REG_L(fetchdat & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -70,9 +70,9 @@
} \
\
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -96,9 +96,9 @@
} \
\
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -122,9 +122,9 @@
} \
\
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@ -153,9 +153,9 @@ static uint32_t ropTEST_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
}
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
dst_reg = TEST_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -178,9 +178,9 @@ static uint32_t ropTEST_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
}
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
dst_reg = TEST_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -203,9 +203,9 @@ static uint32_t ropTEST_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
}
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
dst_reg = TEST_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, dst_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@ -217,8 +217,8 @@ static uint32_t ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_B(REG_AL);
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xff) | 0xffffff00);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
@ -228,8 +228,8 @@ static uint32_t ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_W(REG_AX);
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xffff) | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
@ -240,8 +240,8 @@ static uint32_t ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
AND_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
@ -252,8 +252,8 @@ static uint32_t ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_B(REG_AL);
OR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
@ -263,8 +263,8 @@ static uint32_t ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_W(REG_AX);
OR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
@ -275,8 +275,8 @@ static uint32_t ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
fetchdat = fastreadl(cs + op_pc);
OR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
@ -287,8 +287,8 @@ static uint32_t ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
int host_reg = LOAD_REG_B(REG_AL);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 1;
@ -298,8 +298,8 @@ static uint32_t ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
int host_reg = LOAD_REG_W(REG_AX);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
@ -310,8 +310,8 @@ static uint32_t ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
fetchdat = fastreadl(cs + op_pc);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 4;
@ -322,8 +322,8 @@ static uint32_t ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_B(REG_AL);
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
@ -333,8 +333,8 @@ static uint32_t ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg = LOAD_REG_W(REG_AX);
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
@ -345,8 +345,8 @@ static uint32_t ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
XOR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
@ -374,9 +374,9 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
MEM_LOAD_ADDR_EA_B(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
@ -391,13 +391,13 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
case 0x18: /*NEG b*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
host_reg = LOAD_REG_B(fetchdat & 7);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_op2, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, host_reg);
NEG_HOST_REG_B(host_reg);
STORE_IMM_ADDR_L((uintptr_t)&flags_op1, 0);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op1, 0);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
@ -425,9 +425,9 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 3;
@ -442,13 +442,13 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
case 0x18: /*NEG w*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
host_reg = LOAD_REG_W(fetchdat & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_op2, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, host_reg);
NEG_HOST_REG_W(host_reg);
STORE_IMM_ADDR_L((uintptr_t)&flags_op1, 0);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op1, 0);
STORE_REG_W_RELEASE(host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
@ -476,9 +476,9 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
}
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 5;
@ -493,13 +493,13 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
case 0x18: /*NEG l*/
if ((fetchdat & 0xc0) != 0xc0)
return 0;
STORE_IMM_ADDR_L((uintptr_t)&flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
host_reg = LOAD_REG_L(fetchdat & 7);
STORE_HOST_REG_ADDR((uintptr_t)&flags_op2, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, host_reg);
NEG_HOST_REG_L(host_reg);
STORE_IMM_ADDR_L((uintptr_t)&flags_op1, 0);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op1, 0);
STORE_REG_L_RELEASE(host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}

8
src/codegen_ops_misc.h
View file

@ -47,11 +47,11 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-2);
host_reg = LOAD_VAR_W((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR_W((uintptr_t)&pc, host_reg);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
STORE_HOST_REG_ADDR((uintptr_t)&pc, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x30: /*PUSH*/
@ -96,11 +96,11 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-4);
host_reg = LOAD_VAR_L((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR((uintptr_t)&pc, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
STORE_HOST_REG_ADDR((uintptr_t)&pc, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x30: /*PUSH*/

12
src/codegen_ops_shift.h
View file

@ -1,27 +1,27 @@
#define SHIFT(size, size2, count, res_store) \
STORE_IMM_ADDR_L((uint32_t)&flags_op2, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \
reg = LOAD_REG_ ## size(fetchdat & 7); \
res_store((uint32_t)&flags_op1, reg); \
res_store((uint32_t)&cpu_state.flags_op1, reg); \
\
switch (fetchdat & 0x38) \
{ \
case 0x20: case 0x30: /*SHL*/ \
SHL_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SHL ## size2); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \
break; \
\
case 0x28: /*SHR*/ \
SHR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SHR ## size2); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \
break; \
\
case 0x38: /*SAR*/ \
SAR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SAR ## size2); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \
break; \
} \
\
res_store((uint32_t)&flags_res, reg); \
res_store((uint32_t)&cpu_state.flags_res, reg); \
STORE_REG_ ## size ## _RELEASE(reg);
static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)

12
src/codegen_ops_stack.h
View file

@ -115,7 +115,7 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss);
STORE_HOST_REG_ADDR((uintptr_t)&pc, 0);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2);
return -1;
@ -127,7 +127,7 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss);
STORE_HOST_REG_ADDR((uintptr_t)&pc, 0);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4);
return -1;
@ -141,7 +141,7 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss);
STORE_HOST_REG_ADDR((uintptr_t)&pc, 0);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2+offset);
return -1;
@ -154,7 +154,7 @@ static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss);
STORE_HOST_REG_ADDR((uintptr_t)&pc, 0);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4+offset);
return -1;
@ -170,7 +170,7 @@ static uint32_t ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
host_reg = LOAD_REG_IMM(op_pc+2);
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
SP_MODIFY(-2);
STORE_IMM_ADDR_L((uintptr_t)&pc, (op_pc+2+offset) & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
@ -184,7 +184,7 @@ static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
host_reg = LOAD_REG_IMM(op_pc+4);
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
SP_MODIFY(-4);
STORE_IMM_ADDR_L((uintptr_t)&pc, op_pc+4+offset);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}

173
src/codegen_ops_x86-64.h
View file

@ -200,7 +200,7 @@ static int LOAD_REG_B(int reg)
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[host_reg & 3].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg & 3].b - (uint32_t)&EAX);
}
codegen_reg_loaded[reg & 3] = 1;
@ -220,7 +220,7 @@ static int LOAD_REG_W(int reg)
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
}
codegen_reg_loaded[reg & 7] = 1;
@ -237,7 +237,7 @@ static int LOAD_REG_L(int reg)
addbyte(0x44); /*MOVZX W[reg],host_reg*/
addbyte(0x8b);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
}
codegen_reg_loaded[reg & 7] = 1;
@ -307,7 +307,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (dest_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 3].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].w - (uint32_t)&EAX);
}
else
{
@ -326,7 +326,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0xc0 | (dest_reg & 7));
addbyte(0x88); /*MOVB regs[reg].b, AH*/
addbyte(0x65);
addbyte((uint32_t)&regs[guest_reg & 3].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
}
else
{
@ -336,7 +336,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0x44); /*MOVB regs[guest_reg].b, host_reg*/
addbyte(0x88);
addbyte(0x45 | ((host_reg & 3) << 3));
addbyte((uint32_t)&regs[guest_reg & 3].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
}
}
else
@ -352,7 +352,7 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0xc0 | (dest_reg & 7) | ((host_reg & 7) << 3));
addbyte(0x88); /*MOVB regs[guest_reg].b, host_reg*/
addbyte(0x45 | ((host_reg & 3) << 3));
addbyte((uint32_t)&regs[guest_reg & 3].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b - (uint32_t)&EAX);
}
}
}
@ -370,7 +370,7 @@ static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)&regs[guest_reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].w - (uint32_t)&EAX);
}
else
{
@ -381,7 +381,7 @@ static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
addbyte(0x66); /*MOVW regs[guest_reg].w, host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].w - (uint32_t)&EAX);
}
}
static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
@ -394,7 +394,7 @@ static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
addbyte(0x44); /*MOVL regs[guest_reg].l, host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].l - (uint32_t)&EAX);
}
else
{
@ -403,7 +403,7 @@ static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
addbyte(0xc0 | guest_reg | (host_reg << 3));
addbyte(0x89); /*MOVL regs[guest_reg].l, host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].l - (uint32_t)&EAX);
}
}
@ -415,14 +415,14 @@ static void STORE_REG_B_RELEASE(int host_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)&regs[host_reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].w - (uint32_t)&EAX);
}
else
{
addbyte(0x44); /*MOVB [reg],host_reg*/
addbyte(0x88);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)&regs[host_reg & 7].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].b - (uint32_t)&EAX);
}
}
static void STORE_REG_W_RELEASE(int host_reg)
@ -431,14 +431,14 @@ static void STORE_REG_W_RELEASE(int host_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)&regs[host_reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].w - (uint32_t)&EAX);
}
static void STORE_REG_L_RELEASE(int host_reg)
{
addbyte(0x44); /*MOVL [reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)&regs[host_reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg & 7].l - (uint32_t)&EAX);
}
static void STORE_IMM_REG_B(int reg, uint8_t val)
@ -460,7 +460,7 @@ static void STORE_IMM_REG_B(int reg, uint8_t val)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[reg & 3].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 3].w - (uint32_t)&EAX);
}
else
{
@ -470,7 +470,7 @@ static void STORE_IMM_REG_B(int reg, uint8_t val)
addbyte(0x44); /*MOVB reg, regs[reg].b*/
addbyte(0x88);
addbyte(0x45 | (reg << 3));
addbyte((uint32_t)&regs[reg & 7].b - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].b - (uint32_t)&EAX);
}
}
static void STORE_IMM_REG_W(int reg, uint16_t val)
@ -483,7 +483,7 @@ static void STORE_IMM_REG_W(int reg, uint16_t val)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | (reg << 3));
addbyte((uint32_t)&regs[reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
}
static void STORE_IMM_REG_L(int reg, uint32_t val)
{
@ -493,7 +493,7 @@ static void STORE_IMM_REG_L(int reg, uint32_t val)
addbyte(0x44); /*MOVL reg, regs[reg].l*/
addbyte(0x89);
addbyte(0x45 | (reg << 3));
addbyte((uint32_t)&regs[reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
}
static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
@ -1570,32 +1570,64 @@ static void STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX EBX, host_reg*/
addbyte(0x0f); /*MOVZX ECX, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (REG_ECX << 3) | (host_reg & 7));
addbyte(0x89); /*MOV addr, EBX*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(0x25);
addlong(addr);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
addbyte(0x89); /*MOV addr, ECX*/
addbyte(0x45 | (REG_ECX << 3));
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
}
else
{
addbyte(0x89); /*MOV addr, ECX*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(0x25);
addlong(addr);
}
}
static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
{
addbyte(0x66);
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
addbyte(0x66); /*MOVW [addr],host_reg*/
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89);
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
}
else
{
addbyte(0x66);
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
}
}
static void STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
{
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL [addr],host_reg*/
addbyte(0x45 | ((host_reg & 7) << 3));
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
}
else
{
if (host_reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOVL addr,host_reg*/
addbyte(0x04 | ((host_reg & 7) << 3));
addbyte(0x25);
addlong(addr);
}
}
static void AND_HOST_REG_B(int dst_reg, int src_reg)
@ -2750,11 +2782,10 @@ static void TEST_ZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(11+5+(taken_cycles ? 8 : 0));
addbyte(7+5+(taken_cycles ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -2775,11 +2806,10 @@ static void TEST_ZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(11+5+(taken_cycles ? 8 : 0));
addbyte(7+5+(taken_cycles ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -2802,11 +2832,10 @@ static void TEST_NONZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(11+5+(taken_cycles ? 8 : 0));
addbyte(7+5+(taken_cycles ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -2827,11 +2856,10 @@ static void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | (host_reg & 7));
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(11+5+(taken_cycles ? 8 : 0));
addbyte(7+5+(taken_cycles ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -2847,12 +2875,11 @@ static void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
if (codegen_flags_changed && flags_op != FLAGS_UNKNOWN)
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x3c);
addbyte(0x25);
addlong((uintptr_t)&flags_res);
addbyte(0x7d);
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
addbyte(0);
addbyte(0x74); /*JZ +*/
}
@ -2864,7 +2891,7 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
}
if (not)
addbyte(12+2+2+11+5+(timing_bt ? 8 : 0));
addbyte(12+2+2+7+5+(timing_bt ? 8 : 0));
else
addbyte(12+2+2);
CALL_FUNC(CF_SET);
@ -2874,11 +2901,10 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(11+5+(timing_bt ? 8 : 0));
addbyte(7+5+(timing_bt ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{
@ -2912,11 +2938,10 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(11+5+(timing_bt ? 8 : 0));
addbyte(7+5+(timing_bt ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{
@ -2932,12 +2957,11 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
if (codegen_flags_changed && flags_op != FLAGS_UNKNOWN)
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x3c);
addbyte(0x25);
addlong((uintptr_t)&flags_res);
addbyte(0x7d);
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
addbyte(0);
addbyte(0x74); /*JZ +*/
}
@ -2949,7 +2973,7 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
}
if (not)
addbyte(12+2+3+12+2+3+2+2+11+5+(timing_bt ? 8 : 0));
addbyte(12+2+3+12+2+3+2+2+7+5+(timing_bt ? 8 : 0));
else
addbyte(12+2+3+12+2+3+2+2);
@ -2971,11 +2995,10 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(11+5+(timing_bt ? 8 : 0));
addbyte(7+5+(timing_bt ? 8 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x04);
addbyte(0x25);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{

246
src/codegen_ops_x86.h
View file

@ -52,10 +52,20 @@ static void STORE_IMM_ADDR_W(uintptr_t addr, uint16_t val)
}
static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
{
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x05);
addlong(addr);
addlong(val);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x45);
addbyte(addr - (uint32_t)&cpu_state);
addlong(val);
}
else
{
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x05);
addlong(addr);
addlong(val);
}
}
static void STORE_IMM_REG_B(int reg, uint8_t val)
@ -63,9 +73,9 @@ static void STORE_IMM_REG_B(int reg, uint8_t val)
addbyte(0xC6); /*MOVB [addr],val*/
addbyte(0x45);
if (reg & 4)
addbyte((uint32_t)&regs[reg & 3].b.h - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 3].b.h - (uint32_t)&EAX);
else
addbyte((uint32_t)&regs[reg & 3].b.l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 3].b.l - (uint32_t)&EAX);
addbyte(val);
}
static void STORE_IMM_REG_W(int reg, uint16_t val)
@ -73,14 +83,14 @@ static void STORE_IMM_REG_W(int reg, uint16_t val)
addbyte(0x66); /*MOVW [addr],val*/
addbyte(0xC7);
addbyte(0x45);
addbyte((uint32_t)&regs[reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
addword(val);
}
static void STORE_IMM_REG_L(int reg, uint32_t val)
{
addbyte(0xC7); /*MOVL [addr],val*/
addbyte(0x45);
addbyte((uint32_t)&regs[reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
addlong(val);
}
@ -93,9 +103,9 @@ static int LOAD_REG_B(int reg)
addbyte(0xb6);
addbyte(0x45 | (host_reg << 3));
if (reg & 4)
addbyte((uint32_t)&regs[reg & 3].b.h - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 3].b.h - (uint32_t)&EAX);
else
addbyte((uint32_t)&regs[reg & 3].b.l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 3].b.l - (uint32_t)&EAX);
return host_reg;
}
@ -107,7 +117,7 @@ static int LOAD_REG_W(int reg)
addbyte(0x0f); /*MOVZX W[reg],host_reg*/
addbyte(0xb7);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].w - (uint32_t)&EAX);
return host_reg;
}
@ -118,7 +128,7 @@ static int LOAD_REG_L(int reg)
addbyte(0x8b); /*MOVL host_reg,[reg]*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[reg & 7].l - (uint32_t)&EAX);
return host_reg;
}
@ -175,9 +185,9 @@ static void STORE_REG_B_RELEASE(int host_reg)
addbyte(0x88); /*MOVB [reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
if (host_reg_mapping[host_reg] & 4)
addbyte((uint32_t)&regs[host_reg_mapping[host_reg] & 3].b.h - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg_mapping[host_reg] & 3].b.h - (uint32_t)&EAX);
else
addbyte((uint32_t)&regs[host_reg_mapping[host_reg] & 3].b.l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg_mapping[host_reg] & 3].b.l - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
static void STORE_REG_W_RELEASE(int host_reg)
@ -185,14 +195,14 @@ static void STORE_REG_W_RELEASE(int host_reg)
addbyte(0x66); /*MOVW [reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[host_reg_mapping[host_reg]].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg_mapping[host_reg]].w - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
static void STORE_REG_L_RELEASE(int host_reg)
{
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[host_reg_mapping[host_reg]].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[host_reg_mapping[host_reg]].l - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
@ -201,9 +211,9 @@ static void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0x88); /*MOVB [guest_reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
if (guest_reg & 4)
addbyte((uint32_t)&regs[guest_reg & 3].b.h - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b.h - (uint32_t)&EAX);
else
addbyte((uint32_t)&regs[guest_reg & 3].b.l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 3].b.l - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
@ -211,14 +221,14 @@ static void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
addbyte(0x66); /*MOVW [guest_reg],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 7].w - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].w - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
static void STORE_REG_TARGET_L_RELEASE(int host_reg, int guest_reg)
{
addbyte(0x89); /*MOVL [guest_reg],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)&regs[guest_reg & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[guest_reg & 7].l - (uint32_t)&EAX);
host_reg_mapping[host_reg] = -1;
}
@ -229,16 +239,35 @@ static void RELEASE_REG(int host_reg)
static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
{
addbyte(0x66); /*MOVL [reg],host_reg*/
addbyte(0x89);
addbyte(0x05 | (host_reg << 3));
addlong(addr);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
addbyte(0x66); /*MOVW [addr],host_reg*/
addbyte(0x89);
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
}
else
{
addbyte(0x66); /*MOVL [reg],host_reg*/
addbyte(0x89);
addbyte(0x05 | (host_reg << 3));
addlong(addr);
}
}
static void STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
{
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x05 | (host_reg << 3));
addlong(addr);
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
{
addbyte(0x89); /*MOVL [addr],host_reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
}
else
{
addbyte(0x89); /*MOVL [reg],host_reg*/
addbyte(0x05 | (host_reg << 3));
addlong(addr);
}
}
#define STORE_HOST_REG_ADDR_BL STORE_HOST_REG_ADDR
#define STORE_HOST_REG_ADDR_WL STORE_HOST_REG_ADDR
@ -1214,13 +1243,13 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
{
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint32_t)&regs[sib & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[sib & 7].l - (uint32_t)&EAX);
}
break;
case 1:
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint32_t)&regs[sib & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[sib & 7].l - (uint32_t)&EAX);
addbyte(0x83); /*ADDL EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t)(rmdat >> 16));
@ -1232,7 +1261,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
addlong(new_eaaddr);
addbyte(0x03); /*ADDL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint32_t)&regs[sib & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[sib & 7].l - (uint32_t)&EAX);
(*op_pc) += 4;
break;
}
@ -1259,20 +1288,20 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
case 0:
addbyte(0x03); /*ADDL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint32_t)&regs[(sib >> 3) & 7].l - (uint32_t)&EAX);
addbyte((uint32_t)&cpu_state.regs[(sib >> 3) & 7].l - (uint32_t)&EAX);
break;
case 1:
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI, reg*/
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&cpu_state.regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI, reg*/
addbyte(0x01); addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
addbyte(0x01); addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
case 2:
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI, reg*/
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&cpu_state.regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI, reg*/
addbyte(0xC1); addbyte(0xE0 | REG_EDI); addbyte(2); /*SHL EDI, 2*/
addbyte(0x01); addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
case 3:
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI reg*/
addbyte(0x8B); addbyte(0x45 | (REG_EDI << 3)); addbyte((uint32_t)&cpu_state.regs[(sib >> 3) & 7].l - (uint32_t)&EAX); /*MOVL EDI reg*/
addbyte(0xC1); addbyte(0xE0 | REG_EDI); addbyte(3); /*SHL EDI, 3*/
addbyte(0x01); addbyte(0xc0 | REG_EAX | (REG_EDI << 3)); /*ADDL EAX, EDI*/
break;
@ -1291,8 +1320,8 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
addbyte(0x8b); /*MOVL EAX, regs[rm].l*/
addbyte(0x45);
addbyte((uint32_t)&regs[rm].l - (uint32_t)&EAX);
eaaddr = regs[rm].l;
addbyte((uint32_t)&cpu_state.regs[rm].l - (uint32_t)&EAX);
eaaddr = cpu_state.regs[rm].l;
if (mod)
{
if (rm == 5 && !op_ssegs)
@ -1430,10 +1459,10 @@ static void TEST_ZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(10+5+(taken_cycles ? 7 : 0));
addbyte(7+5+(taken_cycles ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -1451,10 +1480,10 @@ static void TEST_ZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x75); /*JNZ +*/
addbyte(10+5+(taken_cycles ? 7 : 0));
addbyte(7+5+(taken_cycles ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -1474,10 +1503,10 @@ static void TEST_NONZERO_JUMP_W(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(10+5+(taken_cycles ? 7 : 0));
addbyte(7+5+(taken_cycles ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -1495,10 +1524,10 @@ static void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
addbyte(0xc0 | 0x38 | host_reg);
addbyte(0);
addbyte(0x74); /*JZ +*/
addbyte(10+5+(taken_cycles ? 7 : 0));
addbyte(7+5+(taken_cycles ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(new_pc);
if (taken_cycles)
{
@ -1513,14 +1542,15 @@ static void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_cycles)
static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
switch (codegen_flags_changed ? flags_op : FLAGS_UNKNOWN)
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_SUB8:
addbyte(0xa0); /*MOV AL, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x76); /*JBE*/
else
@ -1528,23 +1558,25 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0xa1);
addlong((uint32_t)&flags_op1);
addbyte(0x8b);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x76); /*JBE*/
else
addbyte(0x77); /*JNBE*/
break;
case FLAGS_SUB32:
addbyte(0xa1); /*MOV EAX, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x76); /*JBE*/
else
@ -1552,11 +1584,11 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
default:
if (codegen_flags_changed && flags_op != FLAGS_UNKNOWN)
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x05 | 0x38);
addlong((uintptr_t)&flags_res);
addbyte(0x7d);
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
addbyte(0);
addbyte(0x74); /*JZ +*/
}
@ -1568,7 +1600,7 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
}
if (not)
addbyte(5+2+2+10+5+(timing_bt ? 7 : 0));
addbyte(5+2+2+7+5+(timing_bt ? 7 : 0));
else
addbyte(5+2+2);
CALL_FUNC(CF_SET);
@ -1580,10 +1612,10 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x74); /*JZ +*/
break;
}
addbyte(10+5+(timing_bt ? 7 : 0));
addbyte(7+5+(timing_bt ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{
@ -1598,14 +1630,15 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
switch (codegen_flags_changed ? flags_op : FLAGS_UNKNOWN)
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_SUB8:
addbyte(0xa0); /*MOV AL, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7c); /*JL*/
else
@ -1613,23 +1646,25 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0xa1);
addlong((uint32_t)&flags_op1);
addbyte(0x8b);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7c); /*JL*/
else
addbyte(0x7d); /*JNL*/
break;
case FLAGS_SUB32:
addbyte(0xa1); /*MOV EAX, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7c); /*JL*/
else
@ -1657,10 +1692,10 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
addbyte(0x74); /*JZ +*/
break;
}
addbyte(10+5+(timing_bt ? 7 : 0));
addbyte(7+5+(timing_bt ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{
@ -1675,14 +1710,15 @@ static int BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset, int not
static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
switch (codegen_flags_changed ? flags_op : FLAGS_UNKNOWN)
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_SUB8:
addbyte(0xa0); /*MOV AL, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8a); /*MOV AL, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3a); /*CMP AL, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7e); /*JLE*/
else
@ -1690,23 +1726,25 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
case FLAGS_SUB16:
addbyte(0x66); /*MOV AX, flags_op1*/
addbyte(0xa1);
addlong((uint32_t)&flags_op1);
addbyte(0x8b);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x66); /*CMP AX, flags_op2*/
addbyte(0x3b);
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7e); /*JLE*/
else
addbyte(0x7f); /*JNLE*/
break;
case FLAGS_SUB32:
addbyte(0xa1); /*MOV EAX, flags_op1*/
addlong((uint32_t)&flags_op1);
addbyte(0x8b); /*MOV EAX, flags_op1*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op1 - (uintptr_t)&cpu_state);
addbyte(0x3b); /*CMP EAX, flags_op2*/
addbyte(0x05);
addlong((uint32_t)&flags_op2);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.flags_op2 - (uintptr_t)&cpu_state);
if (not)
addbyte(0x7e); /*JLE*/
else
@ -1714,11 +1752,11 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
default:
if (codegen_flags_changed && flags_op != FLAGS_UNKNOWN)
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
addbyte(0x05 | 0x38);
addlong((uintptr_t)&flags_res);
addbyte(0x7d);
addbyte((uintptr_t)&cpu_state.flags_res - (uintptr_t)&cpu_state);
addbyte(0);
addbyte(0x74); /*JZ +*/
}
@ -1730,7 +1768,7 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x75); /*JNZ +*/
}
if (not)
addbyte(5+2+3+5+2+3+2+2+10+5+(timing_bt ? 7 : 0));
addbyte(5+2+3+5+2+3+2+2+7+5+(timing_bt ? 7 : 0));
else
addbyte(5+2+3+5+2+3+2+2);
@ -1754,10 +1792,10 @@ static int BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
addbyte(0x74); /*JZ +*/
break;
}
addbyte(10+5+(timing_bt ? 7 : 0));
addbyte(7+5+(timing_bt ? 7 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x05);
addlong((uintptr_t)&pc);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc+pc_offset+offset);
if (timing_bt)
{

19
src/codegen_x86-64.c
View file

@ -204,7 +204,7 @@ void codegen_block_init(uint32_t phys_addr)
page_t *page = &pages[phys_addr >> 12];
if (!page->block)
mem_flush_write_page(phys_addr, cs+pc);
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
block_current = (block_current + 1) & BLOCK_MASK;
block = &codeblock[block_current];
@ -220,7 +220,7 @@ void codegen_block_init(uint32_t phys_addr)
block_num = HASH(phys_addr);
codeblock_hash[block_num] = &codeblock[block_current];
block->ins = 0;
block->pc = cs + pc;
block->pc = cs + cpu_state.pc;
block->_cs = cs;
block->pnt = block_current;
block->phys = phys_addr;
@ -570,7 +570,7 @@ void codegen_debug()
{
if (output)
{
pclog("At %04x(%08x):%04x %04x(%08x):%04x es=%08x EAX=%08x BX=%04x ECX=%08x BP=%04x EDX=%08x EDI=%08x\n", CS, cs, pc, SS, ss, ESP, es,EAX, BX,ECX,BP, EDX,EDI);
pclog("At %04x(%08x):%04x %04x(%08x):%04x es=%08x EAX=%08x BX=%04x ECX=%08x BP=%04x EDX=%08x EDI=%08x\n", CS, cs, cpu_state.pc, SS, ss, ESP, es,EAX, BX,ECX,BP, EDX,EDI);
}
}
@ -1102,12 +1102,12 @@ generate_call:
if (new_pc)
{
if (new_pc != -1)
STORE_IMM_ADDR_L((uintptr_t)&pc, new_pc);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, new_pc);
codegen_block_ins++;
block->ins++;
codegen_block_full_ins++;
codegen_endpc = (cs + pc) + 8;
codegen_endpc = (cs + cpu_state.pc) + 8;
return;
}
@ -1188,10 +1188,9 @@ generate_call:
// }
addbyte(0xC7); /*MOVL $new_pc,(pc)*/
addbyte(0x04);
addbyte(0x25);
addlong((uint32_t)&pc);
addbyte(0xC7); /*MOVL [pc],new_pc*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x04);
@ -1222,7 +1221,7 @@ generate_call:
// call(block, codegen_debug);
codegen_endpc = (cs + pc) + 8;
codegen_endpc = (cs + cpu_state.pc) + 8;
}
void codegen_check_abrt()

56
src/codegen_x86.c
View file

@ -204,7 +204,7 @@ void codegen_block_init(uint32_t phys_addr)
page_t *page = &pages[phys_addr >> 12];
if (!page->block)
mem_flush_write_page(phys_addr, cs+pc);
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
block_current = (block_current + 1) & BLOCK_MASK;
block = &codeblock[block_current];
@ -220,7 +220,7 @@ void codegen_block_init(uint32_t phys_addr)
block_num = HASH(phys_addr);
codeblock_hash[block_num] = &codeblock[block_current];
block->ins = 0;
block->pc = cs + pc;
block->pc = cs + cpu_state.pc;
block->_cs = cs;
block->pnt = block_current;
block->phys = phys_addr;
@ -531,7 +531,7 @@ void codegen_debug()
{
if (output)
{
pclog("At %04x(%08x):%04x %04x(%08x):%04x es=%08x EAX=%08x BX=%04x ECX=%08x BP=%04x EDX=%08x EDI=%08x\n", CS, cs, pc, SS, ss, ESP, es,EAX, BX,ECX,BP, EDX,EDI);
pclog("At %04x(%08x):%04x %04x(%08x):%04x es=%08x EAX=%08x BX=%04x ECX=%08x BP=%04x EDX=%08x EDI=%08x\n", CS, cs, cpu_state.pc, SS, ss, ESP, es,EAX, BX,ECX,BP, EDX,EDI);
}
}
@ -611,8 +611,9 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
else
{
addbyte(0xa1); /*MOVL regs[sib&7].l, %eax*/
addlong((uint32_t)&regs[sib & 7].l);
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
}
break;
case 1:
@ -620,8 +621,8 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x05);
addlong((uint32_t)&regs[sib & 7].l);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
(*op_pc)++;
break;
case 2:
@ -629,8 +630,8 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x05);
addlong((uint32_t)&regs[sib & 7].l);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.regs[sib & 7].l - (uintptr_t)&cpu_state);
(*op_pc) += 4;
break;
}
@ -647,21 +648,21 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
{
case 0:
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x05);
addlong((uint32_t)&regs[(sib >> 3) & 7].l);
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state);
break;
case 1:
addbyte(0x8B); addbyte(0x1D); addlong((uint32_t)&regs[(sib >> 3) & 7].l); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 2:
addbyte(0x8B); addbyte(0x1D); addlong((uint32_t)&regs[(sib >> 3) & 7].l); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(2); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 3:
addbyte(0x8B); addbyte(0x1D); addlong((uint32_t)&regs[(sib >> 3) & 7].l); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uintptr_t)&cpu_state.regs[(sib >> 3) & 7].l - (uintptr_t)&cpu_state); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(3); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
@ -682,9 +683,12 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
(*op_pc) += 4;
return op_ea_seg;
}
addbyte(0xa1); /*MOVL regs[rm].l, %eax*/
addlong((uint32_t)&regs[rm].l);
eaaddr = regs[rm].l;
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.regs[rm].l - (uintptr_t)&cpu_state);
// addbyte(0xa1); /*MOVL regs[rm].l, %eax*/
// addlong((uint32_t)&cpu_state.regs[rm].l);
eaaddr = cpu_state.regs[rm].l;
if (mod)
{
if (rm == 5 && !op_ssegs)
@ -905,12 +909,12 @@ generate_call:
if (new_pc)
{
if (new_pc != -1)
STORE_IMM_ADDR_L((uintptr_t)&pc, new_pc);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, new_pc);
codegen_block_ins++;
block->ins++;
codegen_block_full_ins++;
codegen_endpc = (cs + pc) + 8;
codegen_endpc = (cs + cpu_state.pc) + 8;
return;
}
@ -981,11 +985,11 @@ generate_call:
addlong((uint32_t)op_ea_seg);
// }
addbyte(0xC7); /*MOVL $new_pc,(pc)*/
addbyte(0x05);
addlong((uint32_t)&pc);
addbyte(0xC7); /*MOVL pc,new_pc*/
addbyte(0x45);
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x05);
addlong((uint32_t)&oldpc);
@ -1019,15 +1023,15 @@ generate_call:
// addbyte(0xE8); /*CALL*/
// addlong(((uint8_t *)codegen_debug - (uint8_t *)(&block->data[block_pos + 4])));
codegen_endpc = (cs + pc) + 8;
codegen_endpc = (cs + cpu_state.pc) + 8;
}
void codegen_check_abrt()
{
codeblock_t *block = &codeblock[block_current];
// pclog("Generate check abrt at %08X\n", &codeblock[block_current][block_pos]);
addbyte(0xf7); addbyte(0x05); /*TESTL $-1, (abrt)*/
addlong((uint32_t)&abrt); addlong(0xffffffff);
addbyte(0x83); addbyte(0x3d); /*CMP abrt, 0*/
addlong((uint32_t)&abrt); addbyte(0);
addbyte(0x0F); addbyte(0x85); /*JNZ 0*/
addlong((uint32_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(&block->data[block_pos + 4]));
}

64
src/ibm.h
View file

@ -64,30 +64,30 @@ extern int memwaitstate;
/*Processor*/
#define EAX regs[0].l
#define ECX regs[1].l
#define EDX regs[2].l
#define EBX regs[3].l
#define ESP regs[4].l
#define EBP regs[5].l
#define ESI regs[6].l
#define EDI regs[7].l
#define AX regs[0].w
#define CX regs[1].w
#define DX regs[2].w
#define BX regs[3].w
#define SP regs[4].w
#define BP regs[5].w
#define SI regs[6].w
#define DI regs[7].w
#define AL regs[0].b.l
#define AH regs[0].b.h
#define CL regs[1].b.l
#define CH regs[1].b.h
#define DL regs[2].b.l
#define DH regs[2].b.h
#define BL regs[3].b.l
#define BH regs[3].b.h
#define EAX cpu_state.regs[0].l
#define ECX cpu_state.regs[1].l
#define EDX cpu_state.regs[2].l
#define EBX cpu_state.regs[3].l
#define ESP cpu_state.regs[4].l
#define EBP cpu_state.regs[5].l
#define ESI cpu_state.regs[6].l
#define EDI cpu_state.regs[7].l
#define AX cpu_state.regs[0].w
#define CX cpu_state.regs[1].w
#define DX cpu_state.regs[2].w
#define BX cpu_state.regs[3].w
#define SP cpu_state.regs[4].w
#define BP cpu_state.regs[5].w
#define SI cpu_state.regs[6].w
#define DI cpu_state.regs[7].w
#define AL cpu_state.regs[0].b.l
#define AH cpu_state.regs[0].b.h
#define CL cpu_state.regs[1].b.l
#define CH cpu_state.regs[1].b.h
#define DL cpu_state.regs[2].b.l
#define DH cpu_state.regs[2].b.h
#define BL cpu_state.regs[3].b.l
#define BH cpu_state.regs[3].b.h
typedef union
{
@ -99,9 +99,21 @@ typedef union
} b;
} x86reg;
x86reg regs[8];
struct
{
x86reg regs[8];
int flags_op;
uint32_t flags_res;
uint32_t flags_op1, flags_op2;
uint32_t pc;
} cpu_state;
/*x86reg regs[8];*/
uint16_t flags,eflags;
uint32_t /*cs,ds,es,ss,*/oldds,oldss,pc,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
uint32_t /*cs,ds,es,ss,*/oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
//uint16_t msw;
extern int ins,output;

2
src/mcr.c
View file

@ -15,7 +15,7 @@ void resetmcr()
void writemcr(uint16_t addr, uint8_t val)
{
printf("Write MCR %04X %02X %04X:%04X\n",addr,val,CS,pc);
printf("Write MCR %04X %02X %04X:%04X\n",addr,val,CS,cpu_state.pc);
switch (addr)
{
case 0x22:

16
src/mem.c
View file

@ -1039,7 +1039,7 @@ uint8_t readmemb386l(uint32_t seg, uint32_t addr)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! rb %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! rb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return -1;
}
mem_logical_addr = addr = addr + seg;
@ -1066,7 +1066,7 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! wb %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! wb %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
@ -1107,7 +1107,7 @@ uint16_t readmemwl(uint32_t seg, uint32_t addr)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! rw %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! rw %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return -1;
}
if (cr0>>31)
@ -1155,7 +1155,7 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! ww %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! ww %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (page_lookup[addr2>>12])
@ -1205,7 +1205,7 @@ uint32_t readmemll(uint32_t seg, uint32_t addr)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return -1;
}
@ -1245,7 +1245,7 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (page_lookup[addr2>>12])
@ -1302,7 +1302,7 @@ uint64_t readmemql(uint32_t seg, uint32_t addr)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! rl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return -1;
}
@ -1339,7 +1339,7 @@ void writememql(uint32_t seg, uint32_t addr, uint64_t val)
if (seg==-1)
{
x86gpf("NULL segment", 0);
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,pc,opcode,addr);
printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (page_lookup[addr2>>12])

28
src/scat.c
View file

@ -196,7 +196,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
scat_regs[scat_index] = val;
if (scat_shadow_update)
scat_shadow_state_update();
pclog("Write SCAT Register %02X to %02X at %04X:%04X\n", scat_index, val, CS, pc);
pclog("Write SCAT Register %02X to %02X at %04X:%04X\n", scat_index, val, CS, cpu_state.pc);
break;
case 0x92:
@ -215,7 +215,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
}
@ -223,7 +223,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
@ -252,7 +252,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
@ -260,7 +260,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
}
@ -268,7 +268,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
@ -297,7 +297,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, pc);
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
@ -319,7 +319,7 @@ uint8_t scat_read(uint16_t port, void *priv)
val = scat_regs[scat_index];
break;
}
pclog("Read SCAT Register %02X at %04X:%04X\n", scat_index, CS, pc);
pclog("Read SCAT Register %02X at %04X:%04X\n", scat_index, CS, cpu_state.pc);
break;
case 0x92:
@ -329,7 +329,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@ -337,7 +337,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@ -345,7 +345,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;
@ -353,7 +353,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@ -361,7 +361,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@ -369,7 +369,7 @@ uint8_t scat_read(uint16_t port, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, pc);
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;

6
src/sound_pas16.c
View file

@ -261,7 +261,7 @@ static uint8_t pas16_in(uint16_t port, void *p)
temp = 0x20 | 0x10 | 0x01; /*AT bus, XT/AT timing*/
break;
}
/* if (port != 0x388 && port != 0x389 && port != 0xb8b) */pclog("pas16_in : port %04X return %02X %04X:%04X\n", port, temp, CS,pc);
/* if (port != 0x388 && port != 0x389 && port != 0xb8b) */pclog("pas16_in : port %04X return %02X %04X:%04X\n", port, temp, CS,cpu_state.pc);
/* if (CS == 0x1FF4 && pc == 0x0585)
{
if (output)
@ -274,7 +274,7 @@ static uint8_t pas16_in(uint16_t port, void *p)
static void pas16_out(uint16_t port, uint8_t val, void *p)
{
pas16_t *pas16 = (pas16_t *)p;
/* if (port != 0x388 && port != 0x389) */pclog("pas16_out : port %04X val %02X %04X:%04X\n", port, val, CS,pc);
/* if (port != 0x388 && port != 0x389) */pclog("pas16_out : port %04X val %02X %04X:%04X\n", port, val, CS,cpu_state.pc);
/* if (CS == 0x369 && pc == 0x2AC5)
fatal("here\n");*/
switch ((port - pas16->base) + 0x388)
@ -377,7 +377,7 @@ static void pas16_out(uint16_t port, uint8_t val, void *p)
default:
pclog("pas16_out : unknown %04X\n", port);
}
if (pc == 0x80048CF3)
if (cpu_state.pc == 0x80048CF3)
{
if (output)
fatal("here\n");

2
src/vid_ati18800.c
View file

@ -119,7 +119,7 @@ uint8_t ati18800_in(uint16_t addr, void *p)
temp = svga_in(addr, svga);
break;
}
if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,pc);
if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,cpu_state.pc);
return temp;
}

2
src/vid_ati28800.c
View file

@ -127,7 +127,7 @@ uint8_t ati28800_in(uint16_t addr, void *p)
temp = svga_in(addr, svga);
break;
}
if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,pc);
if (addr != 0x3da) pclog("%02X %04X:%04X\n", temp, CS,cpu_state.pc);
return temp;
}

2
src/vid_ega.c
View file

@ -124,7 +124,7 @@ void ega_out(uint16_t addr, uint8_t val, void *p)
}
break;
case 0x3d4:
pclog("Write 3d4 %02X %04X:%04X\n", val, CS, pc);
pclog("Write 3d4 %02X %04X:%04X\n", val, CS, cpu_state.pc);
ega->crtcreg = val & 31;
return;
case 0x3d5:

14
src/x86.h
View file

@ -24,14 +24,14 @@ int timetolive,keyboardtimer;
#define setznp168 setznp16
#define getr8(r) ((r&4)?regs[r&3].b.h:regs[r&3].b.l)
#define getr16(r) regs[r].w
#define getr32(r) regs[r].l
#define getr8(r) ((r&4)?cpu_state.regs[r&3].b.h:cpu_state.regs[r&3].b.l)
#define getr16(r) cpu_state.regs[r].w
#define getr32(r) cpu_state.regs[r].l
#define setr8(r,v) if (r&4) regs[r&3].b.h=v; \
else regs[r&3].b.l=v;
#define setr16(r,v) regs[r].w=v
#define setr32(r,v) regs[r].l=v
#define setr8(r,v) if (r&4) cpu_state.regs[r&3].b.h=v; \
else cpu_state.regs[r&3].b.l=v;
#define setr16(r,v) cpu_state.regs[r].w=v
#define setr32(r,v) cpu_state.regs[r].l=v
uint8_t znptable8[256];
uint16_t znptable16[65536];

212
src/x86_flags.h
View file

@ -35,13 +35,9 @@ enum
FLAGS_DEC32,
};
int flags_op;
uint32_t flags_res;
uint32_t flags_op1, flags_op2;
static inline int ZF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -67,7 +63,7 @@ static inline int ZF_SET()
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
return !flags_res;
return !cpu_state.flags_res;
case FLAGS_UNKNOWN:
return flags & Z_FLAG;
@ -76,7 +72,7 @@ static inline int ZF_SET()
static inline int NF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ZN8:
case FLAGS_ADD8:
@ -86,7 +82,7 @@ static inline int NF_SET()
case FLAGS_SAR8:
case FLAGS_INC8:
case FLAGS_DEC8:
return flags_res & 0x80;
return cpu_state.flags_res & 0x80;
case FLAGS_ZN16:
case FLAGS_ADD16:
@ -96,7 +92,7 @@ static inline int NF_SET()
case FLAGS_SAR16:
case FLAGS_INC16:
case FLAGS_DEC16:
return flags_res & 0x8000;
return cpu_state.flags_res & 0x8000;
case FLAGS_ZN32:
case FLAGS_ADD32:
@ -106,7 +102,7 @@ static inline int NF_SET()
case FLAGS_SAR32:
case FLAGS_INC32:
case FLAGS_DEC32:
return flags_res & 0x80000000;
return cpu_state.flags_res & 0x80000000;
case FLAGS_UNKNOWN:
return flags & N_FLAG;
@ -115,7 +111,7 @@ static inline int NF_SET()
static inline int PF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -141,7 +137,7 @@ static inline int PF_SET()
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
return znptable8[flags_res & 0xff] & P_FLAG;
return znptable8[cpu_state.flags_res & 0xff] & P_FLAG;
case FLAGS_UNKNOWN:
return flags & P_FLAG;
@ -150,7 +146,7 @@ static inline int PF_SET()
static inline int VF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -162,37 +158,37 @@ static inline int VF_SET()
case FLAGS_ADD8:
case FLAGS_INC8:
return !((flags_op1 ^ flags_op2) & 0x80) && ((flags_op1 ^ flags_res) & 0x80);
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_ADD16:
case FLAGS_INC16:
return !((flags_op1 ^ flags_op2) & 0x8000) && ((flags_op1 ^ flags_res) & 0x8000);
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x8000) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_ADD32:
case FLAGS_INC32:
return !((flags_op1 ^ flags_op2) & 0x80000000) && ((flags_op1 ^ flags_res) & 0x80000000);
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80000000) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_SUB8:
case FLAGS_DEC8:
return ((flags_op1 ^ flags_op2) & (flags_op1 ^ flags_res) & 0x80);
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_SUB16:
case FLAGS_DEC16:
return ((flags_op1 ^ flags_op2) & (flags_op1 ^ flags_res) & 0x8000);
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_SUB32:
case FLAGS_DEC32:
return ((flags_op1 ^ flags_op2) & (flags_op1 ^ flags_res) & 0x80000000);
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_SHL8:
return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x80);
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x80);
case FLAGS_SHL16:
return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x8000);
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x8000);
case FLAGS_SHL32:
return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x80000000);
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x80000000);
case FLAGS_SHR8:
return ((flags_op2 == 1) && (flags_op1 & 0x80));
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80));
case FLAGS_SHR16:
return ((flags_op2 == 1) && (flags_op1 & 0x8000));
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x8000));
case FLAGS_SHR32:
return ((flags_op2 == 1) && (flags_op1 & 0x80000000));
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80000000));
case FLAGS_UNKNOWN:
return flags & V_FLAG;
@ -201,7 +197,7 @@ static inline int VF_SET()
static inline int AF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -223,7 +219,7 @@ static inline int AF_SET()
case FLAGS_INC8:
case FLAGS_INC16:
case FLAGS_INC32:
return ((flags_op1 & 0xF) + (flags_op2 & 0xF)) & 0x10;
return ((cpu_state.flags_op1 & 0xF) + (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_SUB8:
case FLAGS_SUB16:
@ -231,7 +227,7 @@ static inline int AF_SET()
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
return ((flags_op1 & 0xF) - (flags_op2 & 0xF)) & 0x10;
return ((cpu_state.flags_op1 & 0xF) - (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_UNKNOWN:
return flags & A_FLAG;
@ -240,38 +236,38 @@ static inline int AF_SET()
static inline int CF_SET()
{
switch (flags_op)
switch (cpu_state.flags_op)
{
case FLAGS_ADD8:
return (flags_op1 + flags_op2) & 0x100;
return (cpu_state.flags_op1 + cpu_state.flags_op2) & 0x100;
case FLAGS_ADD16:
return (flags_op1 + flags_op2) & 0x10000;
return (cpu_state.flags_op1 + cpu_state.flags_op2) & 0x10000;
case FLAGS_ADD32:
return (flags_res < flags_op1);
return (cpu_state.flags_res < cpu_state.flags_op1);
case FLAGS_SUB8:
case FLAGS_SUB16:
case FLAGS_SUB32:
return (flags_op1 < flags_op2);
return (cpu_state.flags_op1 < cpu_state.flags_op2);
case FLAGS_SHL8:
return (flags_op1 << (flags_op2 - 1)) & 0x80;
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80;
case FLAGS_SHL16:
return (flags_op1 << (flags_op2 - 1)) & 0x8000;
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x8000;
case FLAGS_SHL32:
return (flags_op1 << (flags_op2 - 1)) & 0x80000000;
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80000000;
case FLAGS_SHR8:
case FLAGS_SHR16:
case FLAGS_SHR32:
return (flags_op1 >> (flags_op2 - 1)) & 1;
return (cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR8:
return ((int8_t)flags_op1 >> (flags_op2 - 1)) & 1;
return ((int8_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR16:
return ((int16_t)flags_op1 >> (flags_op2 - 1)) & 1;
return ((int16_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR32:
return ((int32_t)flags_op1 >> (flags_op2 - 1)) & 1;
return ((int32_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_ZN8:
case FLAGS_ZN16:
@ -298,7 +294,7 @@ static inline int CF_SET()
static inline void flags_rebuild()
{
if (flags_op != FLAGS_UNKNOWN)
if (cpu_state.flags_op != FLAGS_UNKNOWN)
{
uint16_t tempf = 0;
if (CF_SET()) tempf |= C_FLAG;
@ -308,18 +304,18 @@ static inline void flags_rebuild()
if (NF_SET()) tempf |= N_FLAG;
if (VF_SET()) tempf |= V_FLAG;
flags = (flags & ~0x8d5) | tempf;
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
}
}
static inline void flags_extract()
{
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
}
static inline void flags_rebuild_c()
{
if (flags_op != FLAGS_UNKNOWN)
if (cpu_state.flags_op != FLAGS_UNKNOWN)
{
if (CF_SET())
flags |= C_FLAG;
@ -330,123 +326,123 @@ static inline void flags_rebuild_c()
static inline void setznp8(uint8_t val)
{
flags_op = FLAGS_ZN8;
flags_res = val;
cpu_state.flags_op = FLAGS_ZN8;
cpu_state.flags_res = val;
}
static inline void setznp16(uint16_t val)
{
flags_op = FLAGS_ZN16;
flags_res = val;
cpu_state.flags_op = FLAGS_ZN16;
cpu_state.flags_res = val;
}
static inline void setznp32(uint32_t val)
{
flags_op = FLAGS_ZN32;
flags_res = val;
cpu_state.flags_op = FLAGS_ZN32;
cpu_state.flags_res = val;
}
#define set_flags_shift(op, orig, shift, res) \
flags_op = op; \
flags_res = res; \
flags_op1 = orig; \
flags_op2 = shift;
cpu_state.flags_op = op; \
cpu_state.flags_res = res; \
cpu_state.flags_op1 = orig; \
cpu_state.flags_op2 = shift;
static inline void setadd8(uint8_t a, uint8_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = (a + b) & 0xff;
flags_op = FLAGS_ADD8;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a + b) & 0xff;
cpu_state.flags_op = FLAGS_ADD8;
}
static inline void setadd16(uint16_t a, uint16_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = (a + b) & 0xffff;
flags_op = FLAGS_ADD16;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a + b) & 0xffff;
cpu_state.flags_op = FLAGS_ADD16;
}
static inline void setadd32(uint32_t a, uint32_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = a + b;
flags_op = FLAGS_ADD32;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = a + b;
cpu_state.flags_op = FLAGS_ADD32;
}
static inline void setadd8nc(uint8_t a, uint8_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = (a + b) & 0xff;
flags_op = FLAGS_INC8;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a + b) & 0xff;
cpu_state.flags_op = FLAGS_INC8;
}
static inline void setadd16nc(uint16_t a, uint16_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = (a + b) & 0xffff;
flags_op = FLAGS_INC16;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a + b) & 0xffff;
cpu_state.flags_op = FLAGS_INC16;
}
static inline void setadd32nc(uint32_t a, uint32_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = a + b;
flags_op = FLAGS_INC32;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = a + b;
cpu_state.flags_op = FLAGS_INC32;
}
static inline void setsub8(uint8_t a, uint8_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = (a - b) & 0xff;
flags_op = FLAGS_SUB8;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a - b) & 0xff;
cpu_state.flags_op = FLAGS_SUB8;
}
static inline void setsub16(uint16_t a, uint16_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = (a - b) & 0xffff;
flags_op = FLAGS_SUB16;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a - b) & 0xffff;
cpu_state.flags_op = FLAGS_SUB16;
}
static inline void setsub32(uint32_t a, uint32_t b)
{
flags_op1 = a;
flags_op2 = b;
flags_res = a - b;
flags_op = FLAGS_SUB32;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = a - b;
cpu_state.flags_op = FLAGS_SUB32;
}
static inline void setsub8nc(uint8_t a, uint8_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = (a - b) & 0xff;
flags_op = FLAGS_DEC8;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a - b) & 0xff;
cpu_state.flags_op = FLAGS_DEC8;
}
static inline void setsub16nc(uint16_t a, uint16_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = (a - b) & 0xffff;
flags_op = FLAGS_DEC16;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = (a - b) & 0xffff;
cpu_state.flags_op = FLAGS_DEC16;
}
static inline void setsub32nc(uint32_t a, uint32_t b)
{
flags_rebuild_c();
flags_op1 = a;
flags_op2 = b;
flags_res = a - b;
flags_op = FLAGS_DEC32;
cpu_state.flags_op1 = a;
cpu_state.flags_op2 = b;
cpu_state.flags_res = a - b;
cpu_state.flags_op = FLAGS_DEC32;
}
static inline void setadc8(uint8_t a, uint8_t b)
{
uint16_t c=(uint16_t)a+(uint16_t)b+tempc;
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable8[c&0xFF];
if (c&0x100) flags|=C_FLAG;
@ -456,7 +452,7 @@ static inline void setadc8(uint8_t a, uint8_t b)
static inline void setadc16(uint16_t a, uint16_t b)
{
uint32_t c=(uint32_t)a+(uint32_t)b+tempc;
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable16[c&0xFFFF];
if (c&0x10000) flags|=C_FLAG;
@ -467,7 +463,7 @@ static inline void setadc16(uint16_t a, uint16_t b)
static inline void setsbc8(uint8_t a, uint8_t b)
{
uint16_t c=(uint16_t)a-(((uint16_t)b)+tempc);
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=znptable8[c&0xFF];
if (c&0x100) flags|=C_FLAG;
@ -477,7 +473,7 @@ static inline void setsbc8(uint8_t a, uint8_t b)
static inline void setsbc16(uint16_t a, uint16_t b)
{
uint32_t c=(uint32_t)a-(((uint32_t)b)+tempc);
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=(znptable16[c&0xFFFF]&~4);
flags|=(znptable8[c&0xFF]&4);
@ -489,7 +485,7 @@ static inline void setsbc16(uint16_t a, uint16_t b)
static inline void setadc32(uint32_t a, uint32_t b)
{
uint32_t c=(uint32_t)a+(uint32_t)b+tempc;
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=((c&0x80000000)?N_FLAG:((!c)?Z_FLAG:0));
flags|=(znptable8[c&0xFF]&P_FLAG);
@ -500,7 +496,7 @@ static inline void setadc32(uint32_t a, uint32_t b)
static inline void setsbc32(uint32_t a, uint32_t b)
{
uint32_t c=(uint32_t)a-(((uint32_t)b)+tempc);
flags_op = FLAGS_UNKNOWN;
cpu_state.flags_op = FLAGS_UNKNOWN;
flags&=~0x8D5;
flags|=((c&0x80000000)?N_FLAG:((!c)?Z_FLAG:0));
flags|=(znptable8[c&0xFF]&P_FLAG);

72
src/x86_ops_arith.h
View file

@ -50,16 +50,16 @@
fetch_ea_16(fetchdat); \
if (mod == 3) \
{ \
uint16_t dst = regs[rm].w; \
uint16_t src = regs[reg].w; \
uint16_t dst = cpu_state.regs[rm].w; \
uint16_t src = cpu_state.regs[reg].w; \
setflags ## 16 flagops; \
regs[rm].w = operation; \
cpu_state.regs[rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
} \
else \
{ \
uint16_t dst = geteaw(); if (abrt) return 1; \
uint16_t src = regs[reg].w; \
uint16_t src = cpu_state.regs[reg].w; \
seteaw(operation); if (abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
@ -72,16 +72,16 @@
fetch_ea_32(fetchdat); \
if (mod == 3) \
{ \
uint16_t dst = regs[rm].w; \
uint16_t src = regs[reg].w; \
uint16_t dst = cpu_state.regs[rm].w; \
uint16_t src = cpu_state.regs[reg].w; \
setflags ## 16 flagops; \
regs[rm].w = operation; \
cpu_state.regs[rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
} \
else \
{ \
uint16_t dst = geteaw(); if (abrt) return 1; \
uint16_t src = regs[reg].w; \
uint16_t src = cpu_state.regs[reg].w; \
seteaw(operation); if (abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
@ -95,16 +95,16 @@
fetch_ea_16(fetchdat); \
if (mod == 3) \
{ \
uint32_t dst = regs[rm].l; \
uint32_t src = regs[reg].l; \
uint32_t dst = cpu_state.regs[rm].l; \
uint32_t src = cpu_state.regs[reg].l; \
setflags ## 32 flagops; \
regs[rm].l = operation; \
cpu_state.regs[rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
} \
else \
{ \
uint32_t dst = geteal(); if (abrt) return 1; \
uint32_t src = regs[reg].l; \
uint32_t src = cpu_state.regs[reg].l; \
seteal(operation); if (abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
@ -117,16 +117,16 @@
fetch_ea_32(fetchdat); \
if (mod == 3) \
{ \
uint32_t dst = regs[rm].l; \
uint32_t src = regs[reg].l; \
uint32_t dst = cpu_state.regs[rm].l; \
uint32_t src = cpu_state.regs[reg].l; \
setflags ## 32 flagops; \
regs[rm].l = operation; \
cpu_state.regs[rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
} \
else \
{ \
uint32_t dst = geteal(); if (abrt) return 1; \
uint32_t src = regs[reg].l; \
uint32_t src = cpu_state.regs[reg].l; \
seteal(operation); if (abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
@ -164,10 +164,10 @@
uint16_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
dst = regs[reg].w; \
dst = cpu_state.regs[reg].w; \
src = geteaw(); if (abrt) return 1; \
setflags ## 16 flagops; \
regs[reg].w = operation; \
cpu_state.regs[reg].w = operation; \
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
return 0; \
} \
@ -176,10 +176,10 @@
uint16_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
dst = regs[reg].w; \
dst = cpu_state.regs[reg].w; \
src = geteaw(); if (abrt) return 1; \
setflags ## 16 flagops; \
regs[reg].w = operation; \
cpu_state.regs[reg].w = operation; \
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
return 0; \
} \
@ -189,10 +189,10 @@
uint32_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
dst = regs[reg].l; \
dst = cpu_state.regs[reg].l; \
src = geteal(); if (abrt) return 1; \
setflags ## 32 flagops; \
regs[reg].l = operation; \
cpu_state.regs[reg].l = operation; \
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
return 0; \
} \
@ -201,10 +201,10 @@
uint32_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
dst = regs[reg].l; \
dst = cpu_state.regs[reg].l; \
src = geteal(); if (abrt) return 1; \
setflags ## 32 flagops; \
regs[reg].l = operation; \
cpu_state.regs[reg].l = operation; \
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
return 0; \
} \
@ -276,7 +276,7 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
uint16_t dst;
fetch_ea_16(fetchdat);
dst = geteaw(); if (abrt) return 1;
setsub16(dst, regs[reg].w);
setsub16(dst, cpu_state.regs[reg].w);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
return 0;
@ -286,7 +286,7 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
uint16_t dst;
fetch_ea_32(fetchdat);
dst = geteaw(); if (abrt) return 1;
setsub16(dst, regs[reg].w);
setsub16(dst, cpu_state.regs[reg].w);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
return 0;
@ -297,7 +297,7 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
uint32_t dst;
fetch_ea_16(fetchdat);
dst = geteal(); if (abrt) return 1;
setsub32(dst, regs[reg].l);
setsub32(dst, cpu_state.regs[reg].l);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
return 0;
@ -307,7 +307,7 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
uint32_t dst;
fetch_ea_32(fetchdat);
dst = geteal(); if (abrt) return 1;
setsub32(dst, regs[reg].l);
setsub32(dst, cpu_state.regs[reg].l);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
return 0;
@ -337,7 +337,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
uint16_t src;
fetch_ea_16(fetchdat);
src = geteaw(); if (abrt) return 1;
setsub16(regs[reg].w, src);
setsub16(cpu_state.regs[reg].w, src);
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
return 0;
}
@ -346,7 +346,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
uint16_t src;
fetch_ea_32(fetchdat);
src = geteaw(); if (abrt) return 1;
setsub16(regs[reg].w, src);
setsub16(cpu_state.regs[reg].w, src);
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
return 0;
}
@ -356,7 +356,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
uint32_t src;
fetch_ea_16(fetchdat);
src = geteal(); if (abrt) return 1;
setsub32(regs[reg].l, src);
setsub32(cpu_state.regs[reg].l, src);
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
return 0;
}
@ -365,7 +365,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
uint32_t src;
fetch_ea_32(fetchdat);
src = geteal(); if (abrt) return 1;
setsub32(regs[reg].l, src);
setsub32(cpu_state.regs[reg].l, src);
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
return 0;
}
@ -422,7 +422,7 @@ static int opTEST_w_a16(uint32_t fetchdat)
uint16_t temp, temp2;
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
temp2 = regs[reg].w;
temp2 = cpu_state.regs[reg].w;
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
@ -433,7 +433,7 @@ static int opTEST_w_a32(uint32_t fetchdat)
uint16_t temp, temp2;
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
temp2 = regs[reg].w;
temp2 = cpu_state.regs[reg].w;
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
@ -445,7 +445,7 @@ static int opTEST_l_a16(uint32_t fetchdat)
uint32_t temp, temp2;
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
temp2 = regs[reg].l;
temp2 = cpu_state.regs[reg].l;
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
@ -456,7 +456,7 @@ static int opTEST_l_a32(uint32_t fetchdat)
uint32_t temp, temp2;
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
temp2 = regs[reg].l;
temp2 = cpu_state.regs[reg].l;
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);

60
src/x86_ops_atomic.h
View file

@ -3,7 +3,7 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat)
uint8_t temp, temp2 = AL;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -21,7 +21,7 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat)
uint8_t temp, temp2 = AL;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -40,13 +40,13 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat)
uint16_t temp, temp2 = AX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
if (AX == temp) seteaw(regs[reg].w);
if (AX == temp) seteaw(cpu_state.regs[reg].w);
else AX = temp;
if (abrt) return 1;
setsub16(temp2, temp);
@ -58,13 +58,13 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat)
uint16_t temp, temp2 = AX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
if (AX == temp) seteaw(regs[reg].w);
if (AX == temp) seteaw(cpu_state.regs[reg].w);
else AX = temp;
if (abrt) return 1;
setsub16(temp2, temp);
@ -77,13 +77,13 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat)
uint32_t temp, temp2 = EAX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
if (EAX == temp) seteal(regs[reg].l);
if (EAX == temp) seteal(cpu_state.regs[reg].l);
else EAX = temp;
if (abrt) return 1;
setsub32(temp2, temp);
@ -95,13 +95,13 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat)
uint32_t temp, temp2 = EAX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
if (EAX == temp) seteal(regs[reg].l);
if (EAX == temp) seteal(cpu_state.regs[reg].l);
else EAX = temp;
if (abrt) return 1;
setsub32(temp2, temp);
@ -114,7 +114,7 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 0;
}
@ -145,7 +145,7 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 0;
}
@ -177,7 +177,7 @@ static int opXADD_b_a16(uint32_t fetchdat)
uint8_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -194,7 +194,7 @@ static int opXADD_b_a32(uint32_t fetchdat)
uint8_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -212,15 +212,15 @@ static int opXADD_w_a16(uint32_t fetchdat)
uint16_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(temp + regs[reg].w); if (abrt) return 1;
setadd16(temp, regs[reg].w);
regs[reg].w = temp;
seteaw(temp + cpu_state.regs[reg].w); if (abrt) return 1;
setadd16(temp, cpu_state.regs[reg].w);
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 4);
return 0;
}
@ -229,15 +229,15 @@ static int opXADD_w_a32(uint32_t fetchdat)
uint16_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(temp + regs[reg].w); if (abrt) return 1;
setadd16(temp, regs[reg].w);
regs[reg].w = temp;
seteaw(temp + cpu_state.regs[reg].w); if (abrt) return 1;
setadd16(temp, cpu_state.regs[reg].w);
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 4);
return 0;
}
@ -247,15 +247,15 @@ static int opXADD_l_a16(uint32_t fetchdat)
uint32_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(temp + regs[reg].l); if (abrt) return 1;
setadd32(temp, regs[reg].l);
regs[reg].l = temp;
seteal(temp + cpu_state.regs[reg].l); if (abrt) return 1;
setadd32(temp, cpu_state.regs[reg].l);
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 4);
return 0;
}
@ -264,15 +264,15 @@ static int opXADD_l_a32(uint32_t fetchdat)
uint32_t temp;
if (!is486)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(temp + regs[reg].l); if (abrt) return 1;
setadd32(temp, regs[reg].l);
regs[reg].l = temp;
seteal(temp + cpu_state.regs[reg].l); if (abrt) return 1;
setadd32(temp, cpu_state.regs[reg].l);
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 4);
return 0;
}

56
src/x86_ops_bit.h
View file

@ -4,11 +4,11 @@ static int opBT_w_r_a16(uint32_t fetchdat)
uint16_t temp;
fetch_ea_16(fetchdat);
eaaddr += ((regs[reg].w / 16) * 2); eal_r = 0;
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = 0;
temp = geteaw(); if (abrt) return 1;
flags_rebuild();
if (temp & (1 << (regs[reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
return 0;
@ -18,11 +18,11 @@ static int opBT_w_r_a32(uint32_t fetchdat)
uint16_t temp;
fetch_ea_32(fetchdat);
eaaddr += ((regs[reg].w / 16) * 2); eal_r = 0;
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = 0;
temp = geteaw(); if (abrt) return 1;
flags_rebuild();
if (temp & (1 << (regs[reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[reg].w & 15))) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
return 0;
@ -32,11 +32,11 @@ static int opBT_l_r_a16(uint32_t fetchdat)
uint32_t temp;
fetch_ea_16(fetchdat);
eaaddr += ((regs[reg].l / 32) * 4); eal_r = 0;
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = 0;
temp = geteal(); if (abrt) return 1;
flags_rebuild();
if (temp & (1 << (regs[reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
return 0;
@ -46,11 +46,11 @@ static int opBT_l_r_a32(uint32_t fetchdat)
uint32_t temp;
fetch_ea_32(fetchdat);
eaaddr += ((regs[reg].l / 32) * 4); eal_r = 0;
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = 0;
temp = geteal(); if (abrt) return 1;
flags_rebuild();
if (temp & (1 << (regs[reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
if (temp & (1 << (cpu_state.regs[reg].l & 31))) flags |= C_FLAG;
else flags &= ~C_FLAG;
CLOCK_CYCLES(3);
return 0;
@ -63,10 +63,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
uint16_t temp; \
\
fetch_ea_16(fetchdat); \
eaaddr += ((regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
temp = geteaw(); if (abrt) return 1; \
tempc = (temp & (1 << (regs[reg].w & 15))) ? 1 : 0; \
temp operation (1 << (regs[reg].w & 15)); \
tempc = (temp & (1 << (cpu_state.regs[reg].w & 15))) ? 1 : 0; \
temp operation (1 << (cpu_state.regs[reg].w & 15)); \
seteaw(temp); if (abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
@ -81,10 +81,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
uint16_t temp; \
\
fetch_ea_32(fetchdat); \
eaaddr += ((regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
eaaddr += ((cpu_state.regs[reg].w / 16) * 2); eal_r = eal_w = 0; \
temp = geteaw(); if (abrt) return 1; \
tempc = (temp & (1 << (regs[reg].w & 15))) ? 1 : 0; \
temp operation (1 << (regs[reg].w & 15)); \
tempc = (temp & (1 << (cpu_state.regs[reg].w & 15))) ? 1 : 0; \
temp operation (1 << (cpu_state.regs[reg].w & 15)); \
seteaw(temp); if (abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
@ -99,10 +99,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
uint32_t temp; \
\
fetch_ea_16(fetchdat); \
eaaddr += ((regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
temp = geteal(); if (abrt) return 1; \
tempc = (temp & (1 << (regs[reg].l & 31))) ? 1 : 0; \
temp operation (1 << (regs[reg].l & 31)); \
tempc = (temp & (1 << (cpu_state.regs[reg].l & 31))) ? 1 : 0; \
temp operation (1 << (cpu_state.regs[reg].l & 31)); \
seteal(temp); if (abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
@ -117,10 +117,10 @@ static int opBT_l_r_a32(uint32_t fetchdat)
uint32_t temp; \
\
fetch_ea_32(fetchdat); \
eaaddr += ((regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
eaaddr += ((cpu_state.regs[reg].l / 32) * 4); eal_r = eal_w = 0; \
temp = geteal(); if (abrt) return 1; \
tempc = (temp & (1 << (regs[reg].l & 31))) ? 1 : 0; \
temp operation (1 << (regs[reg].l & 31)); \
tempc = (temp & (1 << (cpu_state.regs[reg].l & 31))) ? 1 : 0; \
temp operation (1 << (cpu_state.regs[reg].l & 31)); \
seteal(temp); if (abrt) return 1; \
flags_rebuild(); \
if (tempc) flags |= C_FLAG; \
@ -164,7 +164,7 @@ static int opBA_w_a16(uint32_t fetchdat)
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -204,7 +204,7 @@ static int opBA_w_a32(uint32_t fetchdat)
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -245,7 +245,7 @@ static int opBA_l_a16(uint32_t fetchdat)
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -285,7 +285,7 @@ static int opBA_l_a32(uint32_t fetchdat)
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}

16
src/x86_ops_bitscan.h
View file

@ -24,7 +24,7 @@ static int opBSF_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
BS_common(0, 16, 1, regs[reg].w, (is486) ? 1 : 3);
BS_common(0, 16, 1, cpu_state.regs[reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -36,7 +36,7 @@ static int opBSF_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
BS_common(0, 16, 1, regs[reg].w, (is486) ? 1 : 3);
BS_common(0, 16, 1, cpu_state.regs[reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -48,7 +48,7 @@ static int opBSF_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
BS_common(0, 32, 1, regs[reg].l, (is486) ? 1 : 3);
BS_common(0, 32, 1, cpu_state.regs[reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -60,7 +60,7 @@ static int opBSF_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
BS_common(0, 32, 1, regs[reg].l, (is486) ? 1 : 3);
BS_common(0, 32, 1, cpu_state.regs[reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -73,7 +73,7 @@ static int opBSR_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
BS_common(15, -1, -1, regs[reg].w, 3);
BS_common(15, -1, -1, cpu_state.regs[reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -85,7 +85,7 @@ static int opBSR_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
BS_common(15, -1, -1, regs[reg].w, 3);
BS_common(15, -1, -1, cpu_state.regs[reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -97,7 +97,7 @@ static int opBSR_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
BS_common(31, -1, -1, regs[reg].l, 3);
BS_common(31, -1, -1, cpu_state.regs[reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;
@ -109,7 +109,7 @@ static int opBSR_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
BS_common(31, -1, -1, regs[reg].l, 3);
BS_common(31, -1, -1, cpu_state.regs[reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
return 0;

52
src/x86_ops_call.h
View file

@ -1,8 +1,8 @@
#define CALL_FAR_w(new_seg, new_pc) \
old_cs = CS; \
old_pc = pc; \
oxpc = pc; \
pc = new_pc; \
old_pc = cpu_state.pc; \
oxpc = cpu_state.pc; \
cpu_state.pc = new_pc; \
optype = CALL; \
cgate16 = cgate32 = 0; \
if (msw & 1) loadcscall(new_seg); \
@ -29,9 +29,9 @@
#define CALL_FAR_l(new_seg, new_pc) \
old_cs = CS; \
old_pc = pc; \
oxpc = pc; \
pc = new_pc; \
old_pc = cpu_state.pc; \
oxpc = cpu_state.pc; \
cpu_state.pc = new_pc; \
optype = CALL; \
cgate16 = cgate32 = 0; \
if (msw & 1) loadcscall(new_seg); \
@ -110,8 +110,8 @@ static int opFF_w_a16(uint32_t fetchdat)
break;
case 0x10: /*CALL*/
new_pc = geteaw(); if (abrt) return 1;
PUSH_W(pc);
pc = new_pc;
PUSH_W(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
@ -125,16 +125,16 @@ static int opFF_w_a16(uint32_t fetchdat)
break;
case 0x20: /*JMP*/
new_pc = geteaw(); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
break;
case 0x28: /*JMP far*/
oxpc = pc;
oxpc = cpu_state.pc;
new_pc = readmemw(easeg, eaaddr);
new_cs = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
CPU_BLOCK_END();
break;
@ -175,8 +175,8 @@ static int opFF_w_a32(uint32_t fetchdat)
break;
case 0x10: /*CALL*/
new_pc = geteaw(); if (abrt) return 1;
PUSH_W(pc);
pc = new_pc;
PUSH_W(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
@ -190,16 +190,16 @@ static int opFF_w_a32(uint32_t fetchdat)
break;
case 0x20: /*JMP*/
new_pc = geteaw(); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
break;
case 0x28: /*JMP far*/
oxpc = pc;
oxpc = cpu_state.pc;
new_pc = readmemw(easeg, eaaddr);
new_cs = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
CPU_BLOCK_END();
break;
@ -241,8 +241,8 @@ static int opFF_l_a16(uint32_t fetchdat)
break;
case 0x10: /*CALL*/
new_pc = geteal(); if (abrt) return 1;
PUSH_L(pc);
pc = new_pc;
PUSH_L(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
@ -256,16 +256,16 @@ static int opFF_l_a16(uint32_t fetchdat)
break;
case 0x20: /*JMP*/
new_pc = geteal(); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
break;
case 0x28: /*JMP far*/
oxpc = pc;
oxpc = cpu_state.pc;
new_pc = readmeml(easeg, eaaddr);
new_cs = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
CPU_BLOCK_END();
break;
@ -306,8 +306,8 @@ static int opFF_l_a32(uint32_t fetchdat)
break;
case 0x10: /*CALL*/
new_pc = geteal(); if (abrt) return 1;
PUSH_L(pc); if (abrt) return 1;
pc = new_pc;
PUSH_L(cpu_state.pc); if (abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
@ -321,16 +321,16 @@ static int opFF_l_a32(uint32_t fetchdat)
break;
case 0x20: /*JMP*/
new_pc = geteal(); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((mod == 3) ? 7 : 10);
break;
case 0x28: /*JMP far*/
oxpc = pc;
oxpc = cpu_state.pc;
new_pc = readmeml(easeg, eaaddr);
new_cs = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
pc = new_pc;
cpu_state.pc = new_pc;
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
CPU_BLOCK_END();
break;

2
src/x86_ops_int.h
View file

@ -67,7 +67,7 @@ static int opINTO(uint32_t fetchdat)
}
if (VF_SET())
{
oldpc = pc;
oldpc = cpu_state.pc;
x86_int_sw(4);
return 1;
}

52
src/x86_ops_jump.h
View file

@ -22,7 +22,7 @@
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
pc += offset; \
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
return 1; \
@ -36,7 +36,7 @@
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
pc += offset; \
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
return 1; \
@ -50,7 +50,7 @@
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
pc += offset; \
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
return 1; \
@ -84,7 +84,7 @@ static int opLOOPNE_w(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (CX && !ZF_SET())
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -97,7 +97,7 @@ static int opLOOPNE_l(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (ECX && !ZF_SET())
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -111,7 +111,7 @@ static int opLOOPE_w(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (CX && ZF_SET())
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -124,7 +124,7 @@ static int opLOOPE_l(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (ECX && ZF_SET())
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -138,7 +138,7 @@ static int opLOOP_w(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (CX)
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -151,7 +151,7 @@ static int opLOOP_l(uint32_t fetchdat)
CLOCK_CYCLES((is486) ? 7 : 11);
if (ECX)
{
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
return 1;
}
@ -164,7 +164,7 @@ static int opJCXZ(uint32_t fetchdat)
CLOCK_CYCLES(5);
if (!CX)
{
pc += offset;
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
return 1;
@ -177,7 +177,7 @@ static int opJECXZ(uint32_t fetchdat)
CLOCK_CYCLES(5);
if (!ECX)
{
pc += offset;
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
return 1;
@ -189,7 +189,7 @@ static int opJECXZ(uint32_t fetchdat)
static int opJMP_r8(uint32_t fetchdat)
{
int8_t offset = (int8_t)getbytef();
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
return 0;
@ -197,7 +197,7 @@ static int opJMP_r8(uint32_t fetchdat)
static int opJMP_r16(uint32_t fetchdat)
{
int16_t offset = (int16_t)getwordf();
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
return 0;
@ -205,7 +205,7 @@ static int opJMP_r16(uint32_t fetchdat)
static int opJMP_r32(uint32_t fetchdat)
{
int32_t offset = (int32_t)getlong(); if (abrt) return 1;
pc += offset;
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
return 0;
@ -215,8 +215,8 @@ static int opJMP_far_a16(uint32_t fetchdat)
{
uint16_t addr = getwordf();
uint16_t seg = getword(); if (abrt) return 1;
uint32_t oxpc = pc;
pc = addr;
uint32_t oxpc = cpu_state.pc;
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
return 0;
@ -225,8 +225,8 @@ static int opJMP_far_a32(uint32_t fetchdat)
{
uint32_t addr = getlong();
uint16_t seg = getword(); if (abrt) return 1;
uint32_t oxpc = pc;
pc = addr;
uint32_t oxpc = cpu_state.pc;
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
return 0;
@ -235,8 +235,8 @@ static int opJMP_far_a32(uint32_t fetchdat)
static int opCALL_r16(uint32_t fetchdat)
{
int16_t addr = (int16_t)getwordf();
PUSH_W(pc);
pc += addr;
PUSH_W(cpu_state.pc);
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
return 0;
@ -244,8 +244,8 @@ static int opCALL_r16(uint32_t fetchdat)
static int opCALL_r32(uint32_t fetchdat)
{
int32_t addr = getlong(); if (abrt) return 1;
PUSH_L(pc);
pc += addr;
PUSH_L(cpu_state.pc);
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
return 0;
@ -256,7 +256,7 @@ static int opRET_w(uint32_t fetchdat)
uint16_t ret;
ret = POP_W(); if (abrt) return 1;
pc = ret;
cpu_state.pc = ret;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
@ -267,7 +267,7 @@ static int opRET_l(uint32_t fetchdat)
uint32_t ret;
ret = POP_L(); if (abrt) return 1;
pc = ret;
cpu_state.pc = ret;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
@ -282,7 +282,7 @@ static int opRET_w_imm(uint32_t fetchdat)
ret = POP_W(); if (abrt) return 1;
if (stack32) ESP += offset;
else SP += offset;
pc = ret;
cpu_state.pc = ret;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
@ -296,7 +296,7 @@ static int opRET_l_imm(uint32_t fetchdat)
ret = POP_L(); if (abrt) return 1;
if (stack32) ESP += offset;
else SP += offset;
pc = ret;
cpu_state.pc = ret;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);

28
src/x86_ops_misc.h
View file

@ -50,7 +50,7 @@ static int opF6_a16(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*TEST b,#8*/
src = readmemb(cs, pc); pc++; if (abrt) return 1;
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
setznp8(src & dst);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
@ -140,7 +140,7 @@ static int opF6_a32(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*TEST b,#8*/
src = readmemb(cs, pc); pc++; if (abrt) return 1;
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
setznp8(src & dst);
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
@ -530,7 +530,7 @@ static int opHLT(uint32_t fetchdat)
if (!((flags&I_FLAG) && pic_intpending))
{
CLOCK_CYCLES_ALWAYS(100);
pc--;
cpu_state.pc--;
}
else
CLOCK_CYCLES(5);
@ -543,9 +543,9 @@ static int opHLT(uint32_t fetchdat)
static int opLOCK(uint32_t fetchdat)
{
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
if (abrt) return 0;
pc++;
cpu_state.pc++;
CLOCK_CYCLES(4);
return x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
@ -562,7 +562,7 @@ static int opBOUND_w_a16(uint32_t fetchdat)
low = geteaw();
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
if (((int16_t)regs[reg].w < low) || ((int16_t)regs[reg].w > high))
if (((int16_t)cpu_state.regs[reg].w < low) || ((int16_t)cpu_state.regs[reg].w > high))
{
x86_int(5);
return 1;
@ -580,7 +580,7 @@ static int opBOUND_w_a32(uint32_t fetchdat)
low = geteaw();
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
if (((int16_t)regs[reg].w < low) || ((int16_t)regs[reg].w > high))
if (((int16_t)cpu_state.regs[reg].w < low) || ((int16_t)cpu_state.regs[reg].w > high))
{
x86_int(5);
return 1;
@ -599,7 +599,7 @@ static int opBOUND_l_a16(uint32_t fetchdat)
low = geteal();
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
if (((int32_t)regs[reg].l < low) || ((int32_t)regs[reg].l > high))
if (((int32_t)cpu_state.regs[reg].l < low) || ((int32_t)cpu_state.regs[reg].l > high))
{
x86_int(5);
return 1;
@ -617,7 +617,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
low = geteal();
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
if (((int32_t)regs[reg].l < low) || ((int32_t)regs[reg].l > high))
if (((int32_t)cpu_state.regs[reg].l < low) || ((int32_t)cpu_state.regs[reg].l > high))
{
x86_int(5);
return 1;
@ -670,7 +670,7 @@ static int opLOADALL(uint32_t fetchdat)
{
flags = (readmemw(0, 0x818) & 0xffd5) | 2;
flags_extract();
pc = readmemw(0, 0x81A);
cpu_state.pc = readmemw(0, 0x81A);
DS = readmemw(0, 0x81E);
SS = readmemw(0, 0x820);
CS = readmemw(0, 0x822);
@ -727,7 +727,7 @@ static int opLOADALL386(uint32_t fetchdat)
flags = readmemw(0, la_addr + 4);
eflags = readmemw(0, la_addr + 6);
flags_extract();
pc = readmeml(0, la_addr + 8);
cpu_state.pc = readmeml(0, la_addr + 8);
EDI = readmeml(0, la_addr + 0xC);
ESI = readmeml(0, la_addr + 0x10);
EBP = readmeml(0, la_addr + 0x14);
@ -772,7 +772,7 @@ static int opCPUID(uint32_t fetchdat)
CLOCK_CYCLES(9);
return 0;
}
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -785,7 +785,7 @@ static int opRDMSR(uint32_t fetchdat)
CLOCK_CYCLES(9);
return 0;
}
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}
@ -798,7 +798,7 @@ static int opWRMSR(uint32_t fetchdat)
CLOCK_CYCLES(9);
return 0;
}
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}

4
src/x86_ops_mmx.h
View file

@ -18,7 +18,7 @@
#define MMX_ENTER() \
if (!cpu_hasMMX) \
{ \
pc = oldpc; \
cpu_state.pc = oldpc; \
x86illegal(); \
return 1; \
} \
@ -33,7 +33,7 @@ static int opEMMS(uint32_t fetchdat)
{
if (!cpu_hasMMX)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}

8
src/x86_ops_mmx_mov.h
View file

@ -5,7 +5,7 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
MM[reg].l[0] = regs[rm].l;
MM[reg].l[0] = cpu_state.regs[rm].l;
MM[reg].l[1] = 0;
CLOCK_CYCLES(1);
}
@ -28,7 +28,7 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
MM[reg].l[0] = regs[rm].l;
MM[reg].l[0] = cpu_state.regs[rm].l;
MM[reg].l[1] = 0;
CLOCK_CYCLES(1);
}
@ -52,7 +52,7 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
regs[rm].l = MM[reg].l[0];
cpu_state.regs[rm].l = MM[reg].l[0];
CLOCK_CYCLES(1);
}
else
@ -70,7 +70,7 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
regs[rm].l = MM[reg].l[0];
cpu_state.regs[rm].l = MM[reg].l[0];
CLOCK_CYCLES(1);
}
else

12
src/x86_ops_mmx_shift.h
View file

@ -16,7 +16,7 @@ static int opPSxxW_imm(uint32_t fetchdat)
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
pc += 2;
cpu_state.pc += 2;
MMX_ENTER();
switch (op)
@ -53,7 +53,7 @@ static int opPSxxW_imm(uint32_t fetchdat)
break;
default:
pclog("Bad PSxxW (0F 71) instruction %02X\n", op);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 0;
}
@ -193,7 +193,7 @@ static int opPSxxD_imm(uint32_t fetchdat)
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
pc += 2;
cpu_state.pc += 2;
MMX_ENTER();
switch (op)
@ -224,7 +224,7 @@ static int opPSxxD_imm(uint32_t fetchdat)
break;
default:
pclog("Bad PSxxD (0F 72) instruction %02X\n", op);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 0;
}
@ -352,7 +352,7 @@ static int opPSxxQ_imm(uint32_t fetchdat)
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
pc += 2;
cpu_state.pc += 2;
MMX_ENTER();
switch (op)
@ -376,7 +376,7 @@ static int opPSxxQ_imm(uint32_t fetchdat)
break;
default:
pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 0;
}

42
src/x86_ops_mov.h
View file

@ -157,7 +157,7 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
{
uint8_t temp;
fetch_ea_16(fetchdat);
temp = readmemb(cs,pc); pc++; if (abrt) return 1;
temp = readmemb(cs,cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
seteab(temp);
CLOCK_CYCLES(timing_rr);
@ -308,7 +308,7 @@ static int opLEA_w_a16(uint32_t fetchdat)
{
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
regs[reg].w = eaaddr;
cpu_state.regs[reg].w = eaaddr;
CLOCK_CYCLES(timing_rr);
return 0;
}
@ -316,7 +316,7 @@ static int opLEA_w_a32(uint32_t fetchdat)
{
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
regs[reg].w = eaaddr;
cpu_state.regs[reg].w = eaaddr;
CLOCK_CYCLES(timing_rr);
return 0;
}
@ -325,7 +325,7 @@ static int opLEA_l_a16(uint32_t fetchdat)
{
fetch_ea_16(fetchdat);
ILLEGAL_ON(mod == 3);
regs[reg].l = eaaddr & 0xffff;
cpu_state.regs[reg].l = eaaddr & 0xffff;
CLOCK_CYCLES(timing_rr);
return 0;
}
@ -333,7 +333,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
{
fetch_ea_32(fetchdat);
ILLEGAL_ON(mod == 3);
regs[reg].l = eaaddr;
cpu_state.regs[reg].l = eaaddr;
CLOCK_CYCLES(timing_rr);
return 0;
}
@ -394,13 +394,13 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
regs[rm].w = regs[reg].w;
cpu_state.regs[rm].w = cpu_state.regs[reg].w;
CLOCK_CYCLES(timing_rr);
}
else
{
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
seteaw(regs[reg].w);
seteaw(cpu_state.regs[reg].w);
CLOCK_CYCLES(is486 ? 1 : 2);
}
return abrt;
@ -410,13 +410,13 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
regs[rm].w = regs[reg].w;
cpu_state.regs[rm].w = cpu_state.regs[reg].w;
CLOCK_CYCLES(timing_rr);
}
else
{
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
seteaw(regs[reg].w);
seteaw(cpu_state.regs[reg].w);
CLOCK_CYCLES(is486 ? 1 : 2);
}
return abrt;
@ -426,13 +426,13 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
regs[rm].l = regs[reg].l;
cpu_state.regs[rm].l = cpu_state.regs[reg].l;
CLOCK_CYCLES(timing_rr);
}
else
{
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
seteal(regs[reg].l);
seteal(cpu_state.regs[reg].l);
CLOCK_CYCLES(is486 ? 1 : 2);
}
return abrt;
@ -442,13 +442,13 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
regs[rm].l = regs[reg].l;
cpu_state.regs[rm].l = cpu_state.regs[reg].l;
CLOCK_CYCLES(timing_rr);
}
else
{
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
seteal(regs[reg].l);
seteal(cpu_state.regs[reg].l);
CLOCK_CYCLES(is486 ? 1 : 2);
}
return abrt;
@ -495,7 +495,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
regs[reg].w = regs[rm].w;
cpu_state.regs[reg].w = cpu_state.regs[rm].w;
CLOCK_CYCLES(timing_rr);
}
else
@ -503,7 +503,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
uint16_t temp;
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
temp = geteaw(); if (abrt) return 1;
regs[reg].w = temp;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
}
return 0;
@ -513,7 +513,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
regs[reg].w = regs[rm].w;
cpu_state.regs[reg].w = cpu_state.regs[rm].w;
CLOCK_CYCLES(timing_rr);
}
else
@ -521,7 +521,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
uint16_t temp;
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
temp = geteaw(); if (abrt) return 1;
regs[reg].w = temp;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
}
return 0;
@ -531,7 +531,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (mod == 3)
{
regs[reg].l = regs[rm].l;
cpu_state.regs[reg].l = cpu_state.regs[rm].l;
CLOCK_CYCLES(timing_rr);
}
else
@ -539,7 +539,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
uint32_t temp;
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
temp = geteal(); if (abrt) return 1;
regs[reg].l = temp;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
}
return 0;
@ -549,7 +549,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (mod == 3)
{
regs[reg].l = regs[rm].l;
cpu_state.regs[reg].l = cpu_state.regs[rm].l;
CLOCK_CYCLES(timing_rr);
}
else
@ -557,7 +557,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
uint32_t temp;
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
temp = geteal(); if (abrt) return 1;
regs[reg].l = temp;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES(is486 ? 1 : 4);
}
return 0;

76
src/x86_ops_mov_ctrl.h
View file

@ -10,24 +10,25 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
switch (reg)
{
case 0:
regs[rm].l = cr0;
if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
regs[rm].l = cr2;
cpu_state.regs[rm].l = cr2;
break;
case 3:
regs[rm].l = cr3;
cpu_state.regs[rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
regs[rm].l = cr4;
cpu_state.regs[rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -46,24 +47,25 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
switch (reg)
{
case 0:
regs[rm].l = cr0;
if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
regs[rm].l = cr2;
cpu_state.regs[rm].l = cr2;
break;
case 3:
regs[rm].l = cr3;
cpu_state.regs[rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
regs[rm].l = cr4;
cpu_state.regs[rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -80,7 +82,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
regs[rm].l = dr[reg];
cpu_state.regs[rm].l = dr[reg];
CLOCK_CYCLES(6);
return 0;
}
@ -93,7 +95,7 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
regs[rm].l = dr[reg];
cpu_state.regs[rm].l = dr[reg];
CLOCK_CYCLES(6);
return 0;
}
@ -110,28 +112,31 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
switch (reg)
{
case 0:
if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
cr0 = regs[rm].l;
if (cpu_16bitbus) cr0 |= 0x10;
if (!(cr0 & 0x80000000)) mmu_perm=4;
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = regs[rm].l;
cr2 = cpu_state.regs[rm].l;
break;
case 3:
cr3 = regs[rm].l;
cr3 = cpu_state.regs[rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -150,28 +155,31 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
switch (reg)
{
case 0:
if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
cr0 = regs[rm].l;
if (cpu_16bitbus) cr0 |= 0x10;
if (!(cr0 & 0x80000000)) mmu_perm=4;
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = regs[rm].l;
cr2 = cpu_state.regs[rm].l;
break;
case 3:
cr3 = regs[rm].l;
cr3 = cpu_state.regs[rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -188,7 +196,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = regs[rm].l;
dr[reg] = cpu_state.regs[rm].l;
CLOCK_CYCLES(6);
return 0;
}
@ -201,7 +209,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = regs[rm].l;
dr[reg] = cpu_state.regs[rm].l;
CLOCK_CYCLES(6);
return 0;
}
@ -215,7 +223,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
regs[rm].l = 0;
cpu_state.regs[rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}
@ -228,7 +236,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
regs[rm].l = 0;
cpu_state.regs[rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}

60
src/x86_ops_mov_seg.h
View file

@ -64,27 +64,27 @@ static int opMOV_l_seg_a16(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
if (mod == 3) regs[rm].l = ES;
if (mod == 3) cpu_state.regs[rm].l = ES;
else seteaw(ES);
break;
case 0x08: /*CS*/
if (mod == 3) regs[rm].l = CS;
if (mod == 3) cpu_state.regs[rm].l = CS;
else seteaw(CS);
break;
case 0x18: /*DS*/
if (mod == 3) regs[rm].l = DS;
if (mod == 3) cpu_state.regs[rm].l = DS;
else seteaw(DS);
break;
case 0x10: /*SS*/
if (mod == 3) regs[rm].l = SS;
if (mod == 3) cpu_state.regs[rm].l = SS;
else seteaw(SS);
break;
case 0x20: /*FS*/
if (mod == 3) regs[rm].l = FS;
if (mod == 3) cpu_state.regs[rm].l = FS;
else seteaw(FS);
break;
case 0x28: /*GS*/
if (mod == 3) regs[rm].l = GS;
if (mod == 3) cpu_state.regs[rm].l = GS;
else seteaw(GS);
break;
}
@ -99,27 +99,27 @@ static int opMOV_l_seg_a32(uint32_t fetchdat)
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
if (mod == 3) regs[rm].l = ES;
if (mod == 3) cpu_state.regs[rm].l = ES;
else seteaw(ES);
break;
case 0x08: /*CS*/
if (mod == 3) regs[rm].l = CS;
if (mod == 3) cpu_state.regs[rm].l = CS;
else seteaw(CS);
break;
case 0x18: /*DS*/
if (mod == 3) regs[rm].l = DS;
if (mod == 3) cpu_state.regs[rm].l = DS;
else seteaw(DS);
break;
case 0x10: /*SS*/
if (mod == 3) regs[rm].l = SS;
if (mod == 3) cpu_state.regs[rm].l = SS;
else seteaw(SS);
break;
case 0x20: /*FS*/
if (mod == 3) regs[rm].l = FS;
if (mod == 3) cpu_state.regs[rm].l = FS;
else seteaw(FS);
break;
case 0x28: /*GS*/
if (mod == 3) regs[rm].l = GS;
if (mod == 3) cpu_state.regs[rm].l = GS;
else seteaw(GS);
break;
}
@ -147,12 +147,12 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
case 0x10: /*SS*/
loadseg(new_seg, &_ss);
if (abrt) return 1;
oldpc = pc;
oldpc = cpu_state.pc;
op32 = use32;
ssegs = 0;
ea_seg = &_ds;
fetchdat = fastreadl(cs + pc);
pc++;
fetchdat = fastreadl(cs + cpu_state.pc);
cpu_state.pc++;
if (abrt) return 1;
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
return 1;
@ -186,12 +186,12 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
case 0x10: /*SS*/
loadseg(new_seg, &_ss);
if (abrt) return 1;
oldpc = pc;
oldpc = cpu_state.pc;
op32 = use32;
ssegs = 0;
ea_seg = &_ds;
fetchdat = fastreadl(cs + pc);
pc++;
fetchdat = fastreadl(cs + cpu_state.pc);
cpu_state.pc++;
if (abrt) return 1;
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
return 1;
@ -217,7 +217,7 @@ static int opLDS_w_a16(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
regs[reg].w = addr;
cpu_state.regs[reg].w = addr;
CLOCK_CYCLES(7);
return 0;
@ -231,7 +231,7 @@ static int opLDS_w_a32(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
regs[reg].w = addr;
cpu_state.regs[reg].w = addr;
CLOCK_CYCLES(7);
return 0;
@ -246,7 +246,7 @@ static int opLDS_l_a16(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
regs[reg].l = addr;
cpu_state.regs[reg].l = addr;
CLOCK_CYCLES(7);
return 0;
@ -261,7 +261,7 @@ static int opLDS_l_a32(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ds); if (abrt) return 1;
regs[reg].l = addr;
cpu_state.regs[reg].l = addr;
CLOCK_CYCLES(7);
return 0;
@ -276,7 +276,7 @@ static int opLSS_w_a16(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
regs[reg].w = addr;
cpu_state.regs[reg].w = addr;
CLOCK_CYCLES(7);
return 1;
@ -290,7 +290,7 @@ static int opLSS_w_a32(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
regs[reg].w = addr;
cpu_state.regs[reg].w = addr;
CLOCK_CYCLES(7);
return 1;
@ -305,7 +305,7 @@ static int opLSS_l_a16(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
regs[reg].l = addr;
cpu_state.regs[reg].l = addr;
CLOCK_CYCLES(7);
return 1;
@ -320,7 +320,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr);
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
loadseg(seg, &_ss); if (abrt) return 1;
regs[reg].l = addr;
cpu_state.regs[reg].l = addr;
CLOCK_CYCLES(7);
return 1;
@ -336,7 +336,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
regs[reg].w = addr; \
cpu_state.regs[reg].w = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -351,7 +351,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
addr = readmemw(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
regs[reg].w = addr; \
cpu_state.regs[reg].w = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -367,7 +367,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
regs[reg].l = addr; \
cpu_state.regs[reg].l = addr; \
\
CLOCK_CYCLES(7); \
return 0; \
@ -383,7 +383,7 @@ static int opLSS_l_a32(uint32_t fetchdat)
addr = readmeml(easeg, eaaddr); \
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
loadseg(seg, &sel); if (abrt) return 1; \
regs[reg].l = addr; \
cpu_state.regs[reg].l = addr; \
\
CLOCK_CYCLES(7); \
return 0; \

40
src/x86_ops_movx.h
View file

@ -4,7 +4,7 @@ static int opMOVZX_w_b_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].w = (uint16_t)temp;
cpu_state.regs[reg].w = (uint16_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -15,7 +15,7 @@ static int opMOVZX_w_b_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].w = (uint16_t)temp;
cpu_state.regs[reg].w = (uint16_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -26,7 +26,7 @@ static int opMOVZX_l_b_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -37,7 +37,7 @@ static int opMOVZX_l_b_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -48,7 +48,7 @@ static int opMOVZX_w_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].w = temp;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES(3);
return 0;
@ -59,7 +59,7 @@ static int opMOVZX_w_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].w = temp;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES(3);
return 0;
@ -70,7 +70,7 @@ static int opMOVZX_l_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -81,7 +81,7 @@ static int opMOVZX_l_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
CLOCK_CYCLES(3);
return 0;
@ -93,9 +93,9 @@ static int opMOVSX_w_b_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].w = (uint16_t)temp;
cpu_state.regs[reg].w = (uint16_t)temp;
if (temp & 0x80)
regs[reg].w |= 0xff00;
cpu_state.regs[reg].w |= 0xff00;
CLOCK_CYCLES(3);
return 0;
@ -106,9 +106,9 @@ static int opMOVSX_w_b_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].w = (uint16_t)temp;
cpu_state.regs[reg].w = (uint16_t)temp;
if (temp & 0x80)
regs[reg].w |= 0xff00;
cpu_state.regs[reg].w |= 0xff00;
CLOCK_CYCLES(3);
return 0;
@ -119,9 +119,9 @@ static int opMOVSX_l_b_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
if (temp & 0x80)
regs[reg].l |= 0xffffff00;
cpu_state.regs[reg].l |= 0xffffff00;
CLOCK_CYCLES(3);
return 0;
@ -132,9 +132,9 @@ static int opMOVSX_l_b_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteab(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
if (temp & 0x80)
regs[reg].l |= 0xffffff00;
cpu_state.regs[reg].l |= 0xffffff00;
CLOCK_CYCLES(3);
return 0;
@ -145,9 +145,9 @@ static int opMOVSX_l_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
if (temp & 0x8000)
regs[reg].l |= 0xffff0000;
cpu_state.regs[reg].l |= 0xffff0000;
CLOCK_CYCLES(3);
return 0;
@ -158,9 +158,9 @@ static int opMOVSX_l_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
regs[reg].l = (uint32_t)temp;
cpu_state.regs[reg].l = (uint32_t)temp;
if (temp & 0x8000)
regs[reg].l |= 0xffff0000;
cpu_state.regs[reg].l |= 0xffff0000;
CLOCK_CYCLES(3);
return 0;

2
src/x86_ops_msr.h
View file

@ -2,7 +2,7 @@ static int opRDTSC(uint32_t fetchdat)
{
if (!cpu_hasrdtsc)
{
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
return 1;
}

32
src/x86_ops_mul.h
View file

@ -12,7 +12,7 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].w = templ & 0xffff;
cpu_state.regs[reg].w = templ & 0xffff;
CLOCK_CYCLES((mod == 3) ? 14 : 17);
return 0;
@ -31,7 +31,7 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].w = templ & 0xffff;
cpu_state.regs[reg].w = templ & 0xffff;
CLOCK_CYCLES((mod == 3) ? 14 : 17);
return 0;
@ -51,7 +51,7 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].l = temp64 & 0xffffffff;
cpu_state.regs[reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
return 0;
@ -70,7 +70,7 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].l = temp64 & 0xffffffff;
cpu_state.regs[reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
return 0;
@ -91,7 +91,7 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].w = templ & 0xffff;
cpu_state.regs[reg].w = templ & 0xffff;
CLOCK_CYCLES((mod == 3) ? 14 : 17);
return 0;
@ -111,7 +111,7 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].w = templ & 0xffff;
cpu_state.regs[reg].w = templ & 0xffff;
CLOCK_CYCLES((mod == 3) ? 14 : 17);
return 0;
@ -131,7 +131,7 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].l = temp64 & 0xffffffff;
cpu_state.regs[reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
return 0;
@ -150,7 +150,7 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
regs[reg].l = temp64 & 0xffffffff;
cpu_state.regs[reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
return 0;
@ -163,9 +163,9 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
int32_t templ;
fetch_ea_16(fetchdat);
templ = (int32_t)(int16_t)regs[reg].w * (int32_t)(int16_t)geteaw();
templ = (int32_t)(int16_t)cpu_state.regs[reg].w * (int32_t)(int16_t)geteaw();
if (abrt) return 1;
regs[reg].w = templ & 0xFFFF;
cpu_state.regs[reg].w = templ & 0xFFFF;
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
@ -178,9 +178,9 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
int32_t templ;
fetch_ea_32(fetchdat);
templ = (int32_t)(int16_t)regs[reg].w * (int32_t)(int16_t)geteaw();
templ = (int32_t)(int16_t)cpu_state.regs[reg].w * (int32_t)(int16_t)geteaw();
if (abrt) return 1;
regs[reg].w = templ & 0xFFFF;
cpu_state.regs[reg].w = templ & 0xFFFF;
flags_rebuild();
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
@ -194,9 +194,9 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
int64_t temp64;
fetch_ea_16(fetchdat);
temp64 = (int64_t)(int32_t)regs[reg].l * (int64_t)(int32_t)geteal();
temp64 = (int64_t)(int32_t)cpu_state.regs[reg].l * (int64_t)(int32_t)geteal();
if (abrt) return 1;
regs[reg].l = temp64 & 0xFFFFFFFF;
cpu_state.regs[reg].l = temp64 & 0xFFFFFFFF;
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
@ -209,9 +209,9 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
int64_t temp64;
fetch_ea_32(fetchdat);
temp64 = (int64_t)(int32_t)regs[reg].l * (int64_t)(int32_t)geteal();
temp64 = (int64_t)(int32_t)cpu_state.regs[reg].l * (int64_t)(int32_t)geteal();
if (abrt) return 1;
regs[reg].l = temp64 & 0xFFFFFFFF;
cpu_state.regs[reg].l = temp64 & 0xFFFFFFFF;
flags_rebuild();
if ((temp64 >> 31) != 0 && (temp64 >> 31) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);

26
src/x86_ops_pmode.h
View file

@ -8,9 +8,9 @@ static int opARPL_a16(uint32_t fetchdat)
temp_seg = geteaw(); if (abrt) return 1;
flags_rebuild();
if ((temp_seg & 3) < (regs[reg].w & 3))
if ((temp_seg & 3) < (cpu_state.regs[reg].w & 3))
{
temp_seg = (temp_seg & 0xfffc) | (regs[reg].w & 3);
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[reg].w & 3);
seteaw(temp_seg); if (abrt) return 1;
flags |= Z_FLAG;
}
@ -30,9 +30,9 @@ static int opARPL_a32(uint32_t fetchdat)
temp_seg = geteaw(); if (abrt) return 1;
flags_rebuild();
if ((temp_seg & 3) < (regs[reg].w & 3))
if ((temp_seg & 3) < (cpu_state.regs[reg].w & 3))
{
temp_seg = (temp_seg & 0xfffc) | (regs[reg].w & 3);
temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[reg].w & 3);
seteaw(temp_seg); if (abrt) return 1;
flags |= Z_FLAG;
}
@ -78,9 +78,9 @@ static int opARPL_a32(uint32_t fetchdat)
flags |= Z_FLAG; \
cpl_override = 1; \
if (is32) \
regs[reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
cpu_state.regs[reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
else \
regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
cpu_state.regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
cpl_override = 0; \
} \
CLOCK_CYCLES(11); \
@ -126,16 +126,16 @@ opLAR(l_a32, fetch_ea_32, 1)
cpl_override = 1; \
if (is32) \
{ \
regs[reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
regs[reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
cpu_state.regs[reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
cpu_state.regs[reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
if (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0x80) \
{ \
regs[reg].l <<= 12; \
regs[reg].l |= 0xFFF; \
cpu_state.regs[reg].l <<= 12; \
cpu_state.regs[reg].l |= 0xFFF; \
} \
} \
else \
regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
cpu_state.regs[reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
cpl_override = 0; \
} \
CLOCK_CYCLES(10); \
@ -255,7 +255,7 @@ static int op0F00_common(uint32_t fetchdat)
default:
pclog("Bad 0F 00 opcode %02X\n", rmdat & 0x38);
pc -= 3;
cpu_state.pc -= 3;
x86illegal();
break;
}
@ -368,7 +368,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
default:
pclog("Bad 0F 01 opcode %02X\n", rmdat & 0x38);
pc -= 3;
cpu_state.pc -= 3;
x86illegal();
break;
}

24
src/x86_ops_prefix.h
View file

@ -1,9 +1,9 @@
#define op_seg(name, seg) \
static int op ## name ## _w_a16(uint32_t fetchdat) \
{ \
fetchdat = fastreadl(cs + pc); \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (abrt) return 1; \
pc++; \
cpu_state.pc++; \
\
ea_seg = &seg; \
ssegs = 1; \
@ -14,9 +14,9 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
\
static int op ## name ## _l_a16(uint32_t fetchdat) \
{ \
fetchdat = fastreadl(cs + pc); \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (abrt) return 1; \
pc++; \
cpu_state.pc++; \
\
ea_seg = &seg; \
ssegs = 1; \
@ -27,9 +27,9 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
\
static int op ## name ## _w_a32(uint32_t fetchdat) \
{ \
fetchdat = fastreadl(cs + pc); \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (abrt) return 1; \
pc++; \
cpu_state.pc++; \
\
ea_seg = &seg; \
ssegs = 1; \
@ -40,9 +40,9 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
\
static int op ## name ## _l_a32(uint32_t fetchdat) \
{ \
fetchdat = fastreadl(cs + pc); \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (abrt) return 1; \
pc++; \
cpu_state.pc++; \
\
ea_seg = &seg; \
ssegs = 1; \
@ -60,9 +60,9 @@ op_seg(SS, _ss)
static int op_66(uint32_t fetchdat) /*Data size select*/
{
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
if (abrt) return 1;
pc++;
cpu_state.pc++;
op32 = ((use32 & 0x100) ^ 0x100) | (op32 & 0x200);
CLOCK_CYCLES(2);
@ -70,9 +70,9 @@ static int op_66(uint32_t fetchdat) /*Data size select*/
}
static int op_67(uint32_t fetchdat) /*Address size select*/
{
fetchdat = fastreadl(cs + pc);
fetchdat = fastreadl(cs + cpu_state.pc);
if (abrt) return 1;
pc++;
cpu_state.pc++;
op32 = ((use32 & 0x200) ^ 0x200) | (op32 & 0x100);
CLOCK_CYCLES(2);

30
src/x86_ops_ret.h
View file

@ -4,15 +4,15 @@
pmoderetf(0, stack_offset); \
return 1; \
} \
oxpc = pc; \
oxpc = cpu_state.pc; \
if (stack32) \
{ \
pc = readmemw(ss, ESP); \
cpu_state.pc = readmemw(ss, ESP); \
loadcs(readmemw(ss, ESP + 2)); \
} \
else \
{ \
pc = readmemw(ss, SP); \
cpu_state.pc = readmemw(ss, SP); \
loadcs(readmemw(ss, SP + 2)); \
} \
if (abrt) return 1; \
@ -26,15 +26,15 @@
pmoderetf(1, stack_offset); \
return 1; \
} \
oxpc = pc; \
oxpc = cpu_state.pc; \
if (stack32) \
{ \
pc = readmeml(ss, ESP); \
cpu_state.pc = readmeml(ss, ESP); \
loadcs(readmeml(ss, ESP + 4) & 0xffff); \
} \
else \
{ \
pc = readmeml(ss, SP); \
cpu_state.pc = readmeml(ss, SP); \
loadcs(readmeml(ss, SP + 4) & 0xffff); \
} \
if (abrt) return 1; \
@ -86,17 +86,17 @@ static int opIRET_286(uint32_t fetchdat)
else
{
uint16_t new_cs;
oxpc = pc;
oxpc = cpu_state.pc;
if (stack32)
{
pc = readmemw(ss, ESP);
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (flags & 0x7000) | (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
}
else
{
pc = readmemw(ss, SP);
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (flags & 0x7000) | (readmemw(ss, ((SP + 4) & 0xffff)) & 0x0fd5) | 2;
SP += 6;
@ -126,17 +126,17 @@ static int opIRET(uint32_t fetchdat)
else
{
uint16_t new_cs;
oxpc = pc;
oxpc = cpu_state.pc;
if (stack32)
{
pc = readmemw(ss, ESP);
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
}
else
{
pc = readmemw(ss, SP);
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
SP += 6;
@ -166,10 +166,10 @@ static int opIRETD(uint32_t fetchdat)
else
{
uint16_t new_cs;
oxpc = pc;
oxpc = cpu_state.pc;
if (stack32)
{
pc = readmeml(ss, ESP);
cpu_state.pc = readmeml(ss, ESP);
new_cs = readmemw(ss, ESP + 4);
flags = (readmemw(ss, ESP + 8) & 0xffd5) | 2;
eflags = readmemw(ss, ESP + 10);
@ -177,7 +177,7 @@ static int opIRETD(uint32_t fetchdat)
}
else
{
pc = readmeml(ss, SP);
cpu_state.pc = readmeml(ss, SP);
new_cs = readmemw(ss, ((SP + 4) & 0xffff));
flags = (readmemw(ss,(SP + 8) & 0xffff) & 0xffd5) | 2;
eflags = readmemw(ss, (SP + 10) & 0xffff);

20
src/x86_ops_shift.h
View file

@ -260,7 +260,7 @@ static int opC0_a16(uint32_t fetchdat)
uint8_t temp, temp2;
fetch_ea_16(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteab(); if (abrt) return 1;
OP_SHIFT_b(c);
return 0;
@ -272,7 +272,7 @@ static int opC0_a32(uint32_t fetchdat)
uint8_t temp, temp2;
fetch_ea_32(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteab(); if (abrt) return 1;
OP_SHIFT_b(c);
return 0;
@ -284,7 +284,7 @@ static int opC1_w_a16(uint32_t fetchdat)
uint16_t temp, temp2;
fetch_ea_16(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteaw(); if (abrt) return 1;
OP_SHIFT_w(c);
return 0;
@ -296,7 +296,7 @@ static int opC1_w_a32(uint32_t fetchdat)
uint16_t temp, temp2;
fetch_ea_32(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteaw(); if (abrt) return 1;
OP_SHIFT_w(c);
return 0;
@ -308,7 +308,7 @@ static int opC1_l_a16(uint32_t fetchdat)
uint32_t temp, temp2;
fetch_ea_16(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteal(); if (abrt) return 1;
OP_SHIFT_l(c);
return 0;
@ -320,7 +320,7 @@ static int opC1_l_a32(uint32_t fetchdat)
uint32_t temp, temp2;
fetch_ea_32(fetchdat);
c = readmemb(cs, pc) & 31; pc++;
c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
temp = geteal(); if (abrt) return 1;
OP_SHIFT_l(c);
return 0;
@ -472,7 +472,7 @@ static int opD3_l_a32(uint32_t fetchdat)
{ \
uint16_t tempw = geteaw(); if (abrt) return 1; \
int tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
uint32_t templ = (tempw << 16) | regs[reg].w; \
uint32_t templ = (tempw << 16) | cpu_state.regs[reg].w; \
if (count <= 16) tempw = templ >> (16 - count); \
else tempw = (templ << count) >> 16; \
seteaw(tempw); if (abrt) return 1; \
@ -486,7 +486,7 @@ static int opD3_l_a32(uint32_t fetchdat)
{ \
uint32_t templ = geteal(); if (abrt) return 1; \
int tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
templ = (templ << count) | (regs[reg].l >> (32 - count)); \
templ = (templ << count) | (cpu_state.regs[reg].l >> (32 - count)); \
seteal(templ); if (abrt) return 1; \
setznp32(templ); \
flags_rebuild(); \
@ -499,7 +499,7 @@ static int opD3_l_a32(uint32_t fetchdat)
{ \
uint16_t tempw = geteaw(); if (abrt) return 1; \
int tempc = (tempw >> (count - 1)) & 1; \
uint32_t templ = tempw | (regs[reg].w << 16); \
uint32_t templ = tempw | (cpu_state.regs[reg].w << 16); \
tempw = templ >> count; \
seteaw(tempw); if (abrt) return 1; \
setznp16(tempw); \
@ -512,7 +512,7 @@ static int opD3_l_a32(uint32_t fetchdat)
{ \
uint32_t templ = geteal(); if (abrt) return 1; \
int tempc = (templ >> (count - 1)) & 1; \
templ = (templ >> count) | (regs[reg].l << (32 - count)); \
templ = (templ >> count) | (cpu_state.regs[reg].l << (32 - count)); \
seteal(templ); if (abrt) return 1; \
setznp32(templ); \
flags_rebuild(); \

16
src/x86_ops_stack.h
View file

@ -295,7 +295,7 @@ static int opPOPL_a32(uint32_t fetchdat)
static int opENTER_w(uint32_t fetchdat)
{
uint16_t offset = getwordf();
int count = (fetchdat >> 16) & 0xff; pc++;
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
PUSH_W(BP); if (abrt) return 1;
@ -328,7 +328,7 @@ static int opENTER_w(uint32_t fetchdat)
static int opENTER_l(uint32_t fetchdat)
{
uint16_t offset = getwordf();
int count = (fetchdat >> 16) & 0xff; pc++;
int count = (fetchdat >> 16) & 0xff; cpu_state.pc++;
uint32_t tempEBP = EBP, tempESP = ESP, frame_ptr;
PUSH_L(EBP); if (abrt) return 1;
@ -444,12 +444,12 @@ static int opPOP_SS_w(uint32_t fetchdat)
loadseg(temp_seg, &_ss); if (abrt) ESP = temp_esp;
CLOCK_CYCLES(is486 ? 3 : 7);
oldpc = pc;
oldpc = cpu_state.pc;
op32 = use32;
ssegs = 0;
ea_seg = &_ds;
fetchdat = fastreadl(cs + pc);
pc++;
fetchdat = fastreadl(cs + cpu_state.pc);
cpu_state.pc++;
if (abrt) return 1;
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
@ -463,12 +463,12 @@ static int opPOP_SS_l(uint32_t fetchdat)
loadseg(temp_seg & 0xffff, &_ss); if (abrt) ESP = temp_esp;
CLOCK_CYCLES(is486 ? 3 : 7);
oldpc = pc;
oldpc = cpu_state.pc;
op32 = use32;
ssegs = 0;
ea_seg = &_ds;
fetchdat = fastreadl(cs + pc);
pc++;
fetchdat = fastreadl(cs + cpu_state.pc);
cpu_state.pc++;
if (abrt) return 1;
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);

16
src/x86_ops_xchg.h
View file

@ -24,8 +24,8 @@ static int opXCHG_w_a16(uint32_t fetchdat)
uint16_t temp;
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(regs[reg].w); if (abrt) return 1;
regs[reg].w = temp;
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
return 0;
}
@ -34,8 +34,8 @@ static int opXCHG_w_a32(uint32_t fetchdat)
uint16_t temp;
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(regs[reg].w); if (abrt) return 1;
regs[reg].w = temp;
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
return 0;
}
@ -45,8 +45,8 @@ static int opXCHG_l_a16(uint32_t fetchdat)
uint32_t temp;
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(regs[reg].l); if (abrt) return 1;
regs[reg].l = temp;
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
return 0;
}
@ -55,8 +55,8 @@ static int opXCHG_l_a32(uint32_t fetchdat)
uint32_t temp;
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(regs[reg].l); if (abrt) return 1;
regs[reg].l = temp;
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
return 0;
}

62
src/x86seg.c
View file

@ -76,7 +76,7 @@ void x86_doabrt(int x86_abrt)
{
// ingpf = 1;
CS = oldcs;
pc = oldpc;
cpu_state.pc = oldpc;
_cs.access = oldcpl << 5;
// pclog("x86_doabrt - %02X %08X %04X:%08X %i\n", x86_abrt, abrt_error, CS, pc, ins);
@ -97,21 +97,21 @@ void x86_doabrt(int x86_abrt)
{
writememw(ss,ESP-2,flags);
writememw(ss,ESP-4,CS);
writememw(ss,ESP-6,pc);
writememw(ss,ESP-6,cpu_state.pc);
ESP-=6;
}
else
{
writememw(ss,((SP-2)&0xFFFF),flags);
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),pc);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
SP-=6;
}
flags&=~I_FLAG;
flags&=~T_FLAG;
oxpc=pc;
pc=readmemw(0,addr);
oxpc=cpu_state.pc;
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
return;
}
@ -357,7 +357,7 @@ void loadseg(uint16_t seg, x86seg *s)
// pclog("Load seg %04X %i %i %04X:%08X\n",seg,dpl,CS&3,CS,pc);
if ((seg&3)>dpl || (CPL)>dpl)
{
pclog("Data seg fail - %04X:%08X %04X %i %04X\n",CS,pc,seg,dpl,segdat[2]);
pclog("Data seg fail - %04X:%08X %04X %i %04X\n",CS,cpu_state.pc,seg,dpl,segdat[2]);
x86gpf(NULL,seg&~3);
// x86abort("Data segment load - level too low!\n",seg&0xFFFC);
return;
@ -637,7 +637,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
cgate32=(type&0x800);
cgate16=!cgate32;
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
count=segdat[2]&31;
if ((DPL < CPL) || (DPL < (seg&3)))
{
@ -712,7 +712,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
do_seg_load(&_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
use32=(segdat[3]&0x40)?0x300:0;
pc=newpc;
cpu_state.pc=newpc;
#ifdef CS_ACCESSED
cpl_override = 1;
@ -732,7 +732,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
case 0x900: /*386 Task gate*/
// pclog("Task gate\n");
pc=oxpc;
cpu_state.pc=oxpc;
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
flags &= ~NT_FLAG;
@ -954,11 +954,11 @@ void loadcscall(uint16_t seg)
{
case 0x400: /*Call gate*/
case 0xC00: /*386 Call gate*/
if (output) pclog("Callgate %08X\n", pc);
if (output) pclog("Callgate %08X\n", cpu_state.pc);
cgate32=(type&0x800);
cgate16=!cgate32;
oldcs=CS;
oldpc=pc;
oldpc=cpu_state.pc;
count=segdat[2]&31;
if ((DPL < CPL) || (DPL < (seg&3)))
{
@ -1124,7 +1124,7 @@ void loadcscall(uint16_t seg)
do_seg_load(&_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
use32=(segdat[3]&0x40)?0x300:0;
pc=newpc;
cpu_state.pc=newpc;
if (output) pclog("Set access 2\n");
@ -1228,7 +1228,7 @@ void loadcscall(uint16_t seg)
do_seg_load(&_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
use32=(segdat[3]&0x40)?0x300:0;
pc=newpc;
cpu_state.pc=newpc;
#ifdef CS_ACCESSED
cpl_override = 1;
@ -1284,7 +1284,7 @@ void pmoderetf(int is32, uint16_t off)
uint32_t addr, oaddr;
uint16_t segdat[4],segdat2[4],seg,newss;
uint32_t oldsp=ESP;
if (output) pclog("RETF %i %04X:%04X %08X %04X\n",is32,CS,pc,cr0,eflags);
if (output) pclog("RETF %i %04X:%04X %08X %04X\n",is32,CS,cpu_state.pc,cr0,eflags);
if (is32)
{
newpc=POPL();
@ -1300,7 +1300,7 @@ void pmoderetf(int is32, uint16_t off)
if (output) pclog("Return to %04X:%08X\n",seg,newpc);
if ((seg&3)<CPL)
{
pclog("RETF RPL<CPL %04X %i %i %04X:%08X\n",seg,CPL,ins,CS,pc);
pclog("RETF RPL<CPL %04X %i %i %04X:%08X\n",seg,CPL,ins,CS,cpu_state.pc);
// output=3;
// timetolive=100;
// dumpregs();
@ -1394,7 +1394,7 @@ void pmoderetf(int is32, uint16_t off)
cpl_override = 0;
#endif
pc=newpc;
cpu_state.pc=newpc;
if (segdat[2] & 0x400)
segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
CS = seg;
@ -1548,7 +1548,7 @@ void pmoderetf(int is32, uint16_t off)
if (segdat[2]&0x400)
segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
pc=newpc;
cpu_state.pc=newpc;
CS=seg;
do_seg_load(&_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
@ -1815,7 +1815,7 @@ void pmodeint(int num, int soft)
// if (soft) pclog("Pushl CS %08X\n", CS);
PUSHL(CS);
// if (soft) pclog("Pushl PC %08X\n", pc);
PUSHL(pc); if (abrt) return;
PUSHL(cpu_state.pc); if (abrt) return;
// if (output) pclog("32Stack %04X:%08X\n",SS,ESP);
}
else
@ -1827,7 +1827,7 @@ void pmodeint(int num, int soft)
// if (soft) pclog("Pushw CS %04X\n", CS);
PUSHW(CS);
// if (soft) pclog("Pushw pc %04X\n", pc);
PUSHW(pc); if (abrt) return;
PUSHW(cpu_state.pc); if (abrt) return;
// if (output) pclog("16Stack %04X:%08X\n",SS,ESP);
}
cpl_override=0;
@ -1862,7 +1862,7 @@ void pmodeint(int num, int soft)
// if (soft) pclog("Pushlc CS %08X\n", CS);
PUSHL(CS);
// if (soft) pclog("Pushlc PC %08X\n", pc);
PUSHL(pc); if (abrt) return;
PUSHL(cpu_state.pc); if (abrt) return;
}
else
{
@ -1870,7 +1870,7 @@ void pmodeint(int num, int soft)
// if (soft) pclog("Pushwc CS %04X\n", CS);
PUSHW(CS);
// if (soft) pclog("Pushwc PC %04X\n", pc);
PUSHW(pc); if (abrt) return;
PUSHW(cpu_state.pc); if (abrt) return;
}
new_cpl = CS & 3;
break;
@ -1884,8 +1884,8 @@ void pmodeint(int num, int soft)
_cs.access = (_cs.access & ~(3 << 5)) | (new_cpl << 5);
// pclog("New CS = %04X\n",CS);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
if (type>0x800) pc=segdat[0]|(segdat[3]<<16);
else pc=segdat[0];
if (type>0x800) cpu_state.pc=segdat[0]|(segdat[3]<<16);
else cpu_state.pc=segdat[0];
use32=(segdat2[3]&0x40)?0x300:0;
// pclog("Int gate done!\n");
@ -1975,7 +1975,7 @@ void pmodeiret(int is32)
x86gpf(NULL,0);
return;
}
oxpc=pc;
oxpc=cpu_state.pc;
if (is32)
{
newpc=POPL();
@ -1988,7 +1988,7 @@ void pmodeiret(int is32)
seg=POPW();
tempflags=POPW(); if (abrt) return;
}
pc=newpc;
cpu_state.pc=newpc;
_cs.base=seg<<4;
_cs.limit=0xFFFF;
_cs.limit_low = 0;
@ -2037,7 +2037,7 @@ void pmodeiret(int is32)
cpl_override=0;
return;
}
oxpc=pc;
oxpc=cpu_state.pc;
flagmask=0xFFFF;
if (CPL) flagmask&=~0x3000;
if (IOPL<CPL) flagmask&=~0x200;
@ -2073,7 +2073,7 @@ void pmodeiret(int is32)
// pclog("V86 IRET %04X:%08X\n",SS,ESP);
// output=3;
pc=newpc;
cpu_state.pc=newpc;
_cs.base=seg<<4;
_cs.limit=0xFFFF;
_cs.limit_low = 0;
@ -2322,7 +2322,7 @@ void pmodeiret(int is32)
check_seg_valid(&_gs);
cycles -= timing_iret_pm_outer;
}
pc=newpc;
cpu_state.pc=newpc;
flags=(flags&~flagmask)|(tempflags&flagmask&0xFFD5)|2;
if (is32) eflags=tempflags>>16;
// pclog("done\n");
@ -2394,7 +2394,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
// if (output) pclog("Write PC %08X %08X\n",tr.base,pc);
cpu_386_flags_rebuild();
writememl(tr.base,0x1C,cr3);
writememl(tr.base,0x20,pc);
writememl(tr.base,0x20,cpu_state.pc);
writememl(tr.base,0x24,flags|(eflags<<16));
writememl(tr.base,0x28,EAX);
@ -2439,7 +2439,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
pc=new_pc;
cpu_state.pc=new_pc;
// if (output) pclog("New pc %08X\n",new_pc);
flags=new_flags;
eflags=new_flags>>16;
@ -2553,7 +2553,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if (output) pclog("Load GS %04X\n",new_gs);
loadseg(new_gs,&_gs);
if (output) pclog("Resuming at %04X:%08X\n",CS,pc);
if (output) pclog("Resuming at %04X:%08X\n",CS,cpu_state.pc);
}
else
{

48
src/x87_ops_arith.h
View file

@ -110,7 +110,7 @@ opFPU(il, uint32_t, 32, t, geteal, (double)(int32_t)t)
static int opFADD(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FADD\n");
ST(0) = ST(0) + ST(fetchdat & 7);
tag[TOP] &= ~TAG_UINT64;
@ -120,7 +120,7 @@ static int opFADD(uint32_t fetchdat)
static int opFADDr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FADD\n");
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -130,7 +130,7 @@ static int opFADDr(uint32_t fetchdat)
static int opFADDP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FADDP\n");
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -142,7 +142,7 @@ static int opFADDP(uint32_t fetchdat)
static int opFCOM(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FCOM\n");
npxs &= ~(C0|C2|C3);
if (ST(0) == ST(fetchdat & 7)) npxs |= C3;
@ -154,7 +154,7 @@ static int opFCOM(uint32_t fetchdat)
static int opFCOMP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FCOMP\n");
npxs &= ~(C0|C2|C3);
npxs |= x87_compare(ST(0), ST(fetchdat & 7));
@ -166,7 +166,7 @@ static int opFCOMP(uint32_t fetchdat)
static int opFCOMPP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FCOMPP\n");
npxs &= ~(C0|C2|C3);
if (*(uint64_t *)&ST(0) == ((uint64_t)1 << 63) && *(uint64_t *)&ST(1) == 0)
@ -182,7 +182,7 @@ static int opFCOMPP(uint32_t fetchdat)
static int opFUCOMPP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FUCOMPP\n", easeg, eaaddr);
npxs &= ~(C0|C2|C3);
npxs |= x87_ucompare(ST(0), ST(1));
@ -195,7 +195,7 @@ static int opFUCOMPP(uint32_t fetchdat)
static int opFDIV(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIV\n");
x87_div(ST(0), ST(0), ST(fetchdat & 7));
tag[TOP] &= ~TAG_UINT64;
@ -205,7 +205,7 @@ static int opFDIV(uint32_t fetchdat)
static int opFDIVr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIV\n");
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -215,7 +215,7 @@ static int opFDIVr(uint32_t fetchdat)
static int opFDIVP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIVP\n");
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -227,7 +227,7 @@ static int opFDIVP(uint32_t fetchdat)
static int opFDIVR(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIVR\n");
x87_div(ST(0), ST(fetchdat&7), ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -237,7 +237,7 @@ static int opFDIVR(uint32_t fetchdat)
static int opFDIVRr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIVR\n");
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -247,7 +247,7 @@ static int opFDIVRr(uint32_t fetchdat)
static int opFDIVRP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDIVR\n");
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -259,7 +259,7 @@ static int opFDIVRP(uint32_t fetchdat)
static int opFMUL(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FMUL\n");
ST(0) = ST(0) * ST(fetchdat & 7);
tag[TOP] &= ~TAG_UINT64;
@ -269,7 +269,7 @@ static int opFMUL(uint32_t fetchdat)
static int opFMULr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FMUL\n");
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -279,7 +279,7 @@ static int opFMULr(uint32_t fetchdat)
static int opFMULP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FMULP\n");
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -291,7 +291,7 @@ static int opFMULP(uint32_t fetchdat)
static int opFSUB(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUB\n");
ST(0) = ST(0) - ST(fetchdat & 7);
tag[TOP] &= ~TAG_UINT64;
@ -301,7 +301,7 @@ static int opFSUB(uint32_t fetchdat)
static int opFSUBr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUB\n");
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -311,7 +311,7 @@ static int opFSUBr(uint32_t fetchdat)
static int opFSUBP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUBP\n");
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -323,7 +323,7 @@ static int opFSUBP(uint32_t fetchdat)
static int opFSUBR(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUBR\n");
ST(0) = ST(fetchdat & 7) - ST(0);
tag[TOP] &= ~TAG_UINT64;
@ -333,7 +333,7 @@ static int opFSUBR(uint32_t fetchdat)
static int opFSUBRr(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUBR\n");
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -343,7 +343,7 @@ static int opFSUBRr(uint32_t fetchdat)
static int opFSUBRP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSUBRP\n");
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
tag[(TOP + fetchdat) & 7] &= ~TAG_UINT64;
@ -355,7 +355,7 @@ static int opFSUBRP(uint32_t fetchdat)
static int opFUCOM(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FUCOM\n");
npxs &= ~(C0|C2|C3);
npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));
@ -366,7 +366,7 @@ static int opFUCOM(uint32_t fetchdat)
static int opFUCOMP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FUCOMP\n");
npxs &= ~(C0|C2|C3);
npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));

70
src/x87_ops_misc.h
View file

@ -1,7 +1,7 @@
static int opFSTSW_AX(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSTSW\n");
AX = npxs;
CLOCK_CYCLES(3);
@ -13,7 +13,7 @@ static int opFSTSW_AX(uint32_t fetchdat)
static int opFNOP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
CLOCK_CYCLES(4);
return 0;
}
@ -21,7 +21,7 @@ static int opFNOP(uint32_t fetchdat)
static int opFCLEX(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
npxs &= 0xff00;
CLOCK_CYCLES(4);
return 0;
@ -30,7 +30,7 @@ static int opFCLEX(uint32_t fetchdat)
static int opFINIT(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
npxc = 0x37F;
npxs = 0;
*(uint64_t *)tag = 0x0303030303030303ll;
@ -43,7 +43,7 @@ static int opFINIT(uint32_t fetchdat)
static int opFFREE(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FFREE\n");
tag[(TOP + fetchdat) & 7] = 3;
CLOCK_CYCLES(3);
@ -53,7 +53,7 @@ static int opFFREE(uint32_t fetchdat)
static int opFST(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FST\n");
ST(fetchdat & 7) = ST(0);
tag[(TOP + fetchdat) & 7] = tag[TOP & 7];
@ -65,7 +65,7 @@ static int opFSTP(uint32_t fetchdat)
{
int temp;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSTP\n");
ST(fetchdat & 7) = ST(0);
tag[(TOP + fetchdat) & 7] = tag[TOP & 7];
@ -313,7 +313,7 @@ static int opFLD(uint32_t fetchdat)
uint64_t old_i64;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLD %f\n", ST(fetchdat & 7));
old_tag = tag[(TOP + fetchdat) & 7];
old_i64 = ST_i64[(TOP + fetchdat) & 7];
@ -330,7 +330,7 @@ static int opFXCH(uint32_t fetchdat)
uint8_t old_tag;
uint64_t old_i64;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FXCH\n");
td = ST(0);
ST(0) = ST(fetchdat&7);
@ -349,7 +349,7 @@ static int opFXCH(uint32_t fetchdat)
static int opFCHS(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FCHS\n");
ST(0) = -ST(0);
tag[TOP] &= ~TAG_UINT64;
@ -360,7 +360,7 @@ static int opFCHS(uint32_t fetchdat)
static int opFABS(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FABS %f\n", ST(0));
ST(0) = fabs(ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -371,7 +371,7 @@ static int opFABS(uint32_t fetchdat)
static int opFTST(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FTST\n");
npxs &= ~(C0|C2|C3);
if (ST(0) == 0.0) npxs |= C3;
@ -383,7 +383,7 @@ static int opFTST(uint32_t fetchdat)
static int opFXAM(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FXAM %i %f\n", tag[TOP&7], ST(0));
npxs &= ~(C0|C1|C2|C3);
if (tag[TOP&7] == 3) npxs |= (C0|C3);
@ -397,7 +397,7 @@ static int opFXAM(uint32_t fetchdat)
static int opFLD1(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLD1\n");
x87_push(1.0);
CLOCK_CYCLES(4);
@ -407,7 +407,7 @@ static int opFLD1(uint32_t fetchdat)
static int opFLDL2T(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDL2T\n");
x87_push(3.3219280948873623);
CLOCK_CYCLES(8);
@ -417,7 +417,7 @@ static int opFLDL2T(uint32_t fetchdat)
static int opFLDL2E(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDL2E\n");
x87_push(1.4426950408889634);
CLOCK_CYCLES(8);
@ -427,7 +427,7 @@ static int opFLDL2E(uint32_t fetchdat)
static int opFLDPI(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDPI\n");
x87_push(3.141592653589793);
CLOCK_CYCLES(8);
@ -437,7 +437,7 @@ static int opFLDPI(uint32_t fetchdat)
static int opFLDEG2(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDEG2\n");
x87_push(0.3010299956639812);
CLOCK_CYCLES(8);
@ -447,7 +447,7 @@ static int opFLDEG2(uint32_t fetchdat)
static int opFLDLN2(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDLN2\n");
x87_push(0.693147180559945);
CLOCK_CYCLES(8);
@ -457,7 +457,7 @@ static int opFLDLN2(uint32_t fetchdat)
static int opFLDZ(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FLDZ\n");
x87_push(0.0);
tag[TOP&7] = 1;
@ -468,7 +468,7 @@ static int opFLDZ(uint32_t fetchdat)
static int opF2XM1(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("F2XM1\n");
ST(0) = pow(2.0, ST(0)) - 1.0;
tag[TOP] &= ~TAG_UINT64;
@ -479,7 +479,7 @@ static int opF2XM1(uint32_t fetchdat)
static int opFYL2X(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FYL2X\n");
ST(1) = ST(1) * (log(ST(0)) / log(2.0));
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
@ -491,7 +491,7 @@ static int opFYL2X(uint32_t fetchdat)
static int opFYL2XP1(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FYL2XP1\n");
ST(1) = ST(1) * (log(ST(0)+1.0) / log(2.0));
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
@ -503,7 +503,7 @@ static int opFYL2XP1(uint32_t fetchdat)
static int opFPTAN(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FPTAN\n");
ST(0) = tan(ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -516,7 +516,7 @@ static int opFPTAN(uint32_t fetchdat)
static int opFPATAN(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FPATAN\n");
ST(1) = atan2(ST(1), ST(0));
tag[(TOP + 1) & 7] &= ~TAG_UINT64;
@ -528,7 +528,7 @@ static int opFPATAN(uint32_t fetchdat)
static int opFDECSTP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDECSTP\n");
TOP = (TOP - 1) & 7;
CLOCK_CYCLES(4);
@ -538,7 +538,7 @@ static int opFDECSTP(uint32_t fetchdat)
static int opFINCSTP(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FDECSTP\n");
TOP = (TOP + 1) & 7;
CLOCK_CYCLES(4);
@ -549,7 +549,7 @@ static int opFPREM(uint32_t fetchdat)
{
int64_t temp64;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FPREM %f %f ", ST(0), ST(1));
temp64 = (int64_t)(ST(0) / ST(1));
ST(0) = ST(0) - (ST(1) * (double)temp64);
@ -566,7 +566,7 @@ static int opFPREM1(uint32_t fetchdat)
{
int64_t temp64;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FPREM1 %f %f ", ST(0), ST(1));
temp64 = (int64_t)(ST(0) / ST(1));
ST(0) = ST(0) - (ST(1) * (double)temp64);
@ -583,7 +583,7 @@ static int opFPREM1(uint32_t fetchdat)
static int opFSQRT(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSQRT\n");
ST(0) = sqrt(ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -595,7 +595,7 @@ static int opFSINCOS(uint32_t fetchdat)
{
double td;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSINCOS\n");
td = ST(0);
ST(0) = sin(td);
@ -609,7 +609,7 @@ static int opFSINCOS(uint32_t fetchdat)
static int opFRNDINT(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FRNDINT %g ", ST(0));
ST(0) = (double)x87_fround(ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -622,7 +622,7 @@ static int opFSCALE(uint32_t fetchdat)
{
int64_t temp64;
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSCALE\n");
temp64 = (int64_t)ST(1);
ST(0) = ST(0) * pow(2.0, (double)temp64);
@ -634,7 +634,7 @@ static int opFSCALE(uint32_t fetchdat)
static int opFSIN(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FSIN\n");
ST(0) = sin(ST(0));
tag[TOP] &= ~TAG_UINT64;
@ -646,7 +646,7 @@ static int opFSIN(uint32_t fetchdat)
static int opFCOS(uint32_t fetchdat)
{
FP_ENTER();
pc++;
cpu_state.pc++;
if (fplog) pclog("FCOS\n");
ST(0) = cos(ST(0));
tag[TOP] &= ~TAG_UINT64;