Changed timer base frequency on XT models to 14.318MHz - PIT, CGA and 4.77MHz CPU should now stay in perfect sync.

This commit is contained in:
TomW 2015-11-25 21:50:38 +00:00
commit 79202cc5c0
10 changed files with 49 additions and 29 deletions

View file

@ -227,7 +227,7 @@ void exec386(int cycs)
{
cycdiff=0;
oldcyc=cycles;
timer_start_period(cycles);
timer_start_period(cycles << TIMER_SHIFT);
// pclog("%i %02X\n", ins, ram[8]);
while (cycdiff<100)
{
@ -375,6 +375,6 @@ opcodestart:
tsc += cycdiff;
timer_end_period(cycles);
timer_end_period(cycles << TIMER_SHIFT);
}
}

View file

@ -1215,7 +1215,7 @@ void exec386_dynarec(int cycs)
cycles += 1000;
cycles_start = cycles;
timer_start_period(cycles);
timer_start_period(cycles << TIMER_SHIFT);
// output=3;
while (cycles>0)
{
@ -1510,7 +1510,7 @@ inrecomp=0;
}
}
}
timer_end_period(cycles);
timer_end_period(cycles << TIMER_SHIFT);
cycles_main -= (cycles_start - cycles);
}
}

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@ -20,6 +20,7 @@
#include "timer.h"
#include "x86.h"
int xt_cpu_multi;
int nmi = 0;
int nextcyc=0;
@ -807,7 +808,7 @@ void clockhardware()
current_diff += diff;
timer_end_period(cycles);
timer_end_period(cycles*xt_cpu_multi);
}
static int takeint = 0;
@ -1084,7 +1085,7 @@ void execx86(int cycs)
// if (pc==0x96B && cs==0x9E040) { printf("Hit it\n"); output=1; timetolive=150; }
// if (pc<0x8000) printf("%04X : %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %02X %04X %i\n",pc,AX,BX,CX,DX,cs>>4,ds>>4,es>>4,ss>>4,DI,SI,BP,SP,opcode,flags,disctime);
cycdiff=cycles;
timer_start_period(cycles);
timer_start_period(cycles*xt_cpu_multi);
current_diff = 0;
cycles-=nextcyc;
// if (instime) pclog("Cycles %i %i\n",cycles,cycdiff);

View file

@ -109,7 +109,7 @@ static struct
CPU cpus_8088[] =
{
/*8088 standard*/
{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0, 0, 0},
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0},
{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0, 0, 0},
@ -120,16 +120,16 @@ CPU cpus_8088[] =
CPU cpus_pcjr[] =
{
/*8088 PCjr*/
{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0, 0, 0},
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0},
{"", -1, 0, 0, 0, 0}
};
CPU cpus_8086[] =
{
/*8086 standard*/
{"8086/7.16", CPU_8086, 1, 3579545*2, 1, 0, 0, 0, 0, 0},
{"8086/7.16", CPU_8086, 1, 14318184/2, 1, 0, 0, 0, 0, 0},
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0},
{"8086/9.54", CPU_8086, 1, (3579545*8)/3, 1, 0, 0, 0, 0, 0},
{"8086/9.54", CPU_8086, 1, 4772728*2, 1, 0, 0, 0, 0, 0},
{"8086/10", CPU_8086, 2, 10000000, 1, 0, 0, 0, 0, 0},
{"8086/12", CPU_8086, 3, 12000000, 1, 0, 0, 0, 0, 0},
{"8086/16", CPU_8086, 4, 16000000, 1, 0, 0, 0, 0, 0},

View file

@ -103,3 +103,5 @@ void cpu_RDMSR();
void cpu_WRMSR();
extern int cpu_use_dynarec;
extern int xt_cpu_multi;

View file

@ -1,4 +1,5 @@
#include "ibm.h"
#include "cpu.h"
#include "io.h"
#include "mem.h"
#include "pit.h"

View file

@ -182,7 +182,10 @@ void pc_reset()
pit_reset();
serial_reset();
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
else
setpitclock(14318184.0);
// sb_reset();
@ -463,7 +466,10 @@ void fullspeed()
if (!atfullspeed)
{
printf("Set fullspeed - %i %i %i\n",is386,AT,cpuspeed2);
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
else
setpitclock(14318184.0);
// if (is386) setpitclock(clocks[2][cpuspeed2][0]);
// else setpitclock(clocks[AT?1:0][cpuspeed2][0]);
}
@ -473,13 +479,10 @@ void fullspeed()
void speedchanged()
{
if (atfullspeed)
{
cpuspeed2=cpuspeed;
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
// if (is386) setpitclock(clocks[2][cpuspeed2][0]);
// else setpitclock(clocks[AT?1:0][cpuspeed2][0]);
}
else
setpitclock(14318184.0);
mem_updatecache();
nvr_recalc();
}

View file

@ -13,7 +13,7 @@
#include "pit.h"
#include "timer.h"
#include "video.h"
#include "model.h"
/*B0 to 40, two writes to 43, then two reads - value does not change!*/
/*B4 to 40, two writes to 43, then two reads - value _does_ change!*/
//Tyrian writes 4300 or 17512
@ -36,6 +36,10 @@ void setpitclock(float clock)
isa_timing = clock/8000000.0;
bus_timing = clock/(double)cpu_busspeed;
video_updatetiming();
// pclog("PITCONST=%f CGACONST=%f\n", PITCONST, CGACONST);
// pclog("CPUMULTI=%g\n", ((14318184.0*(double)(1 << TIMER_SHIFT)) / (double)models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed));
xt_cpu_multi = (int)((14318184.0*(double)(1 << TIMER_SHIFT)) / (double)models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
// pclog("egacycles %i egacycles2 %i temp %f clock %f\n",egacycles,egacycles2,temp,clock);
/* if (video_recalctimings)
video_recalctimings();*/

View file

@ -43,7 +43,7 @@ void timer_process()
enable[c] = *timers[c].enable;
if (*timers[c].enable)
{
*timers[c].count = *timers[c].count - (diff << TIMER_SHIFT);
*timers[c].count = *timers[c].count - diff;
if (*timers[c].count <= 0)
process = 1;
}

View file

@ -6,7 +6,7 @@ extern int timer_start;
#define timer_end_period(cycles) \
do \
{ \
int diff = timer_start - cycles; \
int diff = timer_start - (cycles); \
timer_count -= diff; \
timer_start = cycles; \
if (timer_count <= 0) \
@ -16,14 +16,23 @@ extern int timer_start;
} \
} while (0)
#define timer_clock() \
do \
{ \
int diff = timer_start - cycles; \
timer_count -= diff; \
timer_start = cycles; \
timer_process(); \
timer_update_outstanding(); \
#define timer_clock() \
do \
{ \
int diff; \
if (AT) \
{ \
diff = timer_start - (cycles << TIMER_SHIFT); \
timer_start = cycles << TIMER_SHIFT; \
} \
else \
{ \
diff = timer_start - (cycles * xt_cpu_multi); \
timer_start = cycles * xt_cpu_multi; \
} \
timer_count -= diff; \
timer_process(); \
timer_update_outstanding(); \
} while (0)
void timer_process();