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1,264 commits 3 branches 0 tags 5.5 MiB
Commit graph pcem/src/386_dynarec.c
Author SHA1 Message Date
SarahW
9ff1c7f409 Further reductions to codeblock_t size - replace link pointers with uint16_t block indicies, shrink ins to uint8_t, remove endpc. codeblock_t now fits in a 64-byte cacheline on 32-bit platforms. 2018-11-29 20:05:12 +00:00
SarahW
2007c25177 Start reducing size of codeblock_t structure. 
Re-arrange all variables needed to run a block to fit in a single cache line.
 2018-11-28 20:29:48 +00:00
SarahW
a4d3aa1912 Move flags and eflags variables into cpu_struct. 2018-11-28 09:42:04 +00:00
SarahW
d9e38fe37c Fix masking of FPU top-of-stack in several places. Fixes DOS Quake. 2018-10-09 13:51:05 +01:00
SarahW
a7d006b637 Rewrote timer code. 
The new code is based on timestamps, rather than delays. This eliminates the
need to update every timer in timer_process(), which cost a non-trivial amount
of CPU time on low-end machines.

This involved changes to every user of the timer code, so this change almost
certainly introduces bugs.
 2018-08-02 22:06:10 +01:00
SarahW
91143d3c68 Move CPU segment structures into cpu_state structure. 2018-07-22 12:56:03 +01:00
SarahW
0f0a1c3223 Perform NULL segment checks upfront in opcode handlers, rather than on every memory access. 
This removes the need to pass the segment to readmem*l()/writemem*l().
 2018-07-18 22:10:18 +01:00
SarahW
03fe25d818 First stage of dynamic recompiler rewrite. 
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
 2018-06-17 20:26:15 +01:00
SarahW
2957dae2d5 Fixes to x86_was_reset handling. Based on patch from Greatpsycho. 2018-01-08 21:10:46 +00:00
SarahW
f336dd9589 Implemented IDT limit checking on real mode interrupts. Patch from Greatpsycho. 2018-01-08 20:54:19 +00:00
SarahW
4af811699e Fix dynarec timer granularity to 5us. Fixed speed issues in Tubular Worlds. 2017-11-19 21:55:49 +00:00
SarahW
717d815604 Tweak flat DS/SS dynarec optimisation, should reduce block churn when routines are called both with and without flat DS/SS. 
Fixed incorrect STACK32 flag when entering V86 mode that was hidden by block churn.
Protected and V86 mode status now considered when selecting block.
 2017-11-15 21:55:27 +00:00
SarahW
c71963727a Recompiler now uses logical address of 0xffffffff rather than 0 to represent invalid block. Fixes some Unixes when recompiler enabled. 2017-10-15 21:32:01 +01:00
SarahW
5f0d43f782 Prefetch simulation no longer counts prefixes when prefetch calculation disabled (eg when CPU cache enabled). Fixes hang on reset on 486+ CPUs. 2017-10-15 21:29:49 +01:00
SarahW
132a2eb110 Add NMI support to dynamic recompiler. 2017-10-13 22:42:59 +01:00
SarahW
a96e87527e Reorganised REP instructions. 2017-07-20 21:06:21 +01:00
SarahW
1f33b52451 Added VME emulation to Intel DX4, Pentium and Pentium MMX. 
Temporarily disabled recompilation of CLI and STI.
 2017-06-30 20:42:19 +01:00
SarahW
3a7c4687d6 Reduce self modifying code granularity from 64 bytes to 16. 2017-06-13 21:05:10 +01:00
SarahW
083ca3d4a2 Slight optimisation when DS/SS are 'flat' (base=0, limit=4G). 2017-05-24 21:50:37 +01:00
SarahW
2b892d2a7a Fixed compiler warnings for Windows builds. 
Added -Werror to Windows makefiles.
 2017-04-11 19:34:41 +01:00
SarahW
7c7961c578 Fixed inconsistent declaration of biosmask 2016-12-17 21:53:58 +00:00
SarahW
bfc69a4bea Cleaned up ibm.h a bit 2016-11-28 20:06:17 +00:00
SarahW
a4f3b2013e Added AMI 386DX and MR 386DX models (both based on OPTi 495 chipset). AMI 386DX supports external cache, useful for with prefetch emulation. 
Also commit a few fixes required :
- Set EDX correctly on soft reset
- LOCK NOP is now treated as an illegal instruction
- Tweaks to FDC sense interrupt handling following FDC reset
 2016-11-27 21:53:13 +00:00
SarahW
1b73963997 Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing. 2016-11-25 21:32:02 +00:00
SarahW
a174a88c49 Codeblock tree now includes both physical and virtual addresses into key. Fixes performance issues with Windows 3.1. 2016-11-08 21:30:48 +00:00
SarahW
75f9316c11 x86-32 recompiler compiles FPU instructions using direct access to register stack when top-of-stack is static. Minor speedup. 2016-09-11 15:38:05 +01:00
SarahW
eb126fd822 Moved more variables into cpu_state structure. 2016-08-21 21:28:23 +01:00
SarahW
c664682758 Move some more variables into cpu_state structure. Minor speedup (~2%). 2016-08-17 21:28:16 +01:00
SarahW
535604b760 Pack decoded ModR/M data into a single word - minor recompiler speedup. 2016-08-14 16:29:54 +01:00
SarahW
42237ac1f8 Recompiler now only recompiles a block after seeing it twice. Improves performance on stuff that uses self modifying code - eg Doom, Duke Nukem 3D, Windows 95 idle 2016-07-31 12:33:37 +01:00
SarahW
4ae8f2d260 REP instructions now handle trap flag correctly, Windows NT 3.51 now works on 386 systems. 2016-06-28 21:58:21 +01:00
SarahW
7fbb99fe75 Don't quit emulator on triple fault when dynamic recompiler enabled. 2016-05-21 21:14:00 +01:00
SarahW
52636936e9 Limited how long REP instructions are uninterruptable for, improves sound on games/demos that use high-frequency timer interrupts for sound output (eg Crystal Dream, Cronologia) 2016-05-03 21:31:05 +01:00
SarahW
c81a91fd72 Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%). 2016-04-20 21:39:41 +01:00
SarahW
36bb949126 If recompiler block hash table points to wrong block, then walk tree to find correct block instead of recompiling. Speedups of 10-20% on games that were seeing hash aliasing, eg Quake III, System Shock 2, UltraHLE etc 2016-04-06 20:48:36 +01:00
TomW
673a3527af Don't cause illegal instruction exception on unknown REP instruction. Patch from Battler. 2016-03-17 21:47:56 +00:00
TomW
94f33aa873 More accurate timing for INT, IRET, CALL far, RET far and JMP far. 2016-02-06 18:08:10 +00:00
TomW
673d785743 Writing to a memory page with code present only causes code block flushes if the data changes, or if a block is currently being recompiled. 2016-02-03 21:09:05 +00:00
TomW
79202cc5c0 Changed timer base frequency on XT models to 14.318MHz - PIT, CGA and 4.77MHz CPU should now stay in perfect sync. 2015-11-25 21:50:38 +00:00
TomW
2efc56e882 Reset triggered by keyboard controller should now be handled correctly by dynamic recompiler. 2015-08-31 19:31:23 +01:00
TomW
f339f00315 Interpreter and dynamic recompiler now present in a single binary. 2015-08-21 20:55:36 +01:00
TomW
2db98723c7 REP instructions in 32-bit mode with both 0x66 and 0x67 prefixes now work correctly - fixes QEMM and DESQview. 2015-08-07 21:31:00 +01:00
TomW
08254b8dfb Initial 64-bit recompiler. 
Various 64-bit fixes.
Various fixes to allow building under MinGW-w64.
 2015-07-18 12:11:54 +01:00
TomW
854a2ee2a6 Fixed Final Fantasy 7 broken by rev 277. 2015-07-14 20:09:14 +01:00
TomW
6bc394b4c6 Recompiler now handles reset caused by a newly generated codeblock. 2015-07-12 15:22:58 +01:00
TomW
9061c5d2fc Added code generation for : 
- TEST immediate
- register versions of NOT and NEG
- fixed shift versions of SHL, SHR and SAR
- MOVZX and MOVSX
- LEA
- CMP with memory destination
- JL, JNL, JLE, JNLE, JBE, JNBE
 2015-05-30 17:08:54 +01:00
TomW
1fb4de4507 Dynamic recompiler now works on Linux (32-bit only) 2015-04-11 18:31:51 +01:00
TomW
a97e89e857 Added code generation for register and immediate PUSH/POP, RET, relative CALL and JMP instructions. 2015-03-30 20:42:33 +01:00
TomW
ba715706b6 Added code generation for memory versions of MOV, and memory source versions of ADD, SUB, AND, OR, XOR and CMP. 2015-02-08 17:17:14 +00:00
TomW
ea5e96569d Lazy flags code now handles carry flag. 2015-02-02 19:54:01 +00:00