Retro/pcem
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Author SHA1 Message Date
SarahW
a4d3aa1912 Move flags and eflags variables into cpu_struct. 2018-11-28 09:42:04 +00:00
SarahW
c1565eb42f Fix partial register handling - removes pointless loads when writing to non-32-bit registers (eg FPU or MMX). 2018-11-27 19:43:01 +00:00
SarahW
92ab0ee8ef Fix flags on 8-bit memory INC/DEC. 2018-11-27 10:15:18 +00:00
SarahW
07035c97c8 Added recompiled versions of FABS, FCHS, FSQRT and FTST. 2018-11-26 17:00:00 +00:00
SarahW
856f0b4471 ARM64 MMX fixes 2018-11-25 17:59:38 +00:00
SarahW
6341caf318 ARM MMX fixes 2018-11-24 20:35:33 +00:00
SarahW
2a19183d83 Added debug code to log execution rate of non-recompiled instructions. 2018-11-24 20:16:52 +00:00
SarahW
086422b79f Added recompiled versions of PMULLW, PMULHW and PMADDWD. 2018-11-24 12:52:08 +00:00
SarahW
77af266ab2 Added recompiled versions of PACK* and PUNPCK * 2018-11-23 18:34:30 +00:00
SarahW
a991bc3249 Added recompiled versions of PCMP* 2018-11-23 15:17:21 +00:00
SarahW
e43a2a6be0 Added recompiled versions of PSLL*, PSLR* and PSAR* with immediate shifts. 2018-11-22 18:43:36 +00:00
SarahW
35b9e0811b Added recompiled versions of PADD* and PSUB*. 2018-11-22 15:57:44 +00:00
SarahW
78c604c731 Added recompiled versions of PAND, PANDN, POR and PXOR 2018-11-21 20:51:34 +00:00
SarahW
76115568f2 Added recompiled versions of MOVD and MOVQ. 2018-11-21 17:02:20 +00:00
SarahW
f545d9d57f Rename FPU stack-based integer mirror registers, to avoid confusion with non-stack-based MMX registers. 2018-11-21 12:44:47 +00:00
SarahW
fa4ccece48 Fixed pixel clock on S3 ViRGE. 2018-11-20 09:40:54 +00:00
SarahW
964b20e820 Added recompiled versions of FLD1 and FLDZ. 2018-11-14 21:43:22 +00:00
SarahW
0055238ade Added recompiled versions of FCOM, FCOMP, FCOMPP, FICOM, FICOM, FUCOM, FUCOMP and FUCOMPP. 2018-11-14 21:42:20 +00:00
SarahW
b814bcc80d Added recompiled versions of FSTCW and FSTSW. 2018-10-25 21:43:32 +01:00
SarahW
87191dde55 Added recompiled versions of FIST and FISTP. 2018-10-25 20:54:33 +01:00
SarahW
589f50e479 Added recompiled version of FILDq. 2018-10-22 21:23:09 +01:00
SarahW
bce9ad4f3d Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH. 2018-10-21 16:22:20 +01:00
SarahW
6d8af5df4a Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR. 2018-10-20 20:03:28 +01:00
SarahW
8a516df476 Added recompiled versions of FLD, FILD, FST and FSTP. 2018-10-17 19:47:04 +01:00
SarahW
e17a94a409 FDIVP/FDIVRP should pop the stack when a divide by zero occurs and the exception is masked. Fixes software rendering on Need for Speed III. 2018-10-09 22:10:29 +01:00
SarahW
829c74f2d5 Don't write back unchanged registers on flush + invalidate. 2018-10-09 14:07:49 +01:00
SarahW
d9e38fe37c Fix masking of FPU top-of-stack in several places. Fixes DOS Quake. 2018-10-09 13:51:05 +01:00
SarahW
305b6cc4fd Added recompiled register versions of FADDP, FDIVP, FDIVRP, FMULP, FSUBP and FSUBRP. 2018-10-08 21:44:30 +01:00
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
dbb01ef9e2 Cleaned up x87 tag register handling. 2018-10-01 21:02:40 +01:00
SarahW
e9ff110021 Fixed flags on register->register ADD/SUB opcode 00/01/28/29. Fixes rendering in Need For Speed II. 2018-09-30 17:30:28 +01:00
SarahW
94fe85b17e Fixed video clock on Cirrus Logic cards. 2018-09-29 17:43:02 +01:00
SarahW
592b07be63 Added recompiled versions of JMP indirect, JMP far, RETF, LxS, XLAT and LEAVE. 2018-09-29 17:42:44 +01:00
SarahW
1aadfd436d Added recompiled versions of CBW, CDQ, CWD, CWDE and MOVSX. 2018-09-23 21:45:12 +01:00
SarahW
8a19e56340 Added recompiled versions of INC and DEC. 2018-09-12 20:16:27 +01:00
SarahW
3332897886 Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE. 2018-08-30 22:26:33 +01:00
SarahW
872a2da788 Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD. 2018-08-16 21:44:41 +01:00
SarahW
2783471daa Clamp SVGA display on/off timings to a minimum of 1 usec. Fixes hang on Windows XP boot with ViRGE/DX. 2018-08-08 22:15:21 +01:00
SarahW
4846616924 Handle REP prefixed instructions without a dedicated REP instruction handler properly in the recompiler. Fixes Windows XP setup. 2018-08-08 22:14:52 +01:00
SarahW
9bba93e0be Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG. 2018-08-08 22:14:22 +01:00
SarahW
57e5549f48 Remove final remnants of ARM literal pool, and expand work register set to 7 registers. 2018-08-05 16:24:48 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
4ada3382b4 Fix inconsistent size of ide_fn array. 2018-08-03 19:44:35 +01:00
SarahW
a9d46d95ec Use MOVW/MOVT to load immediates on ARM instead of a literal pool. 2018-08-02 22:09:57 +01:00
SarahW
42d62925c3 Fix compiler warnings on ARM builds. 2018-08-02 22:09:18 +01:00
SarahW
a7d006b637 Rewrote timer code. 
The new code is based on timestamps, rather than delays. This eliminates the
need to update every timer in timer_process(), which cost a non-trivial amount
of CPU time on low-end machines.

This involved changes to every user of the timer code, so this change almost
certainly introduces bugs.
 2018-08-02 22:06:10 +01:00
SarahW
ab359ca9c5 Removed rogue CPU_BLOCK_END() from ropMOV_r_b() 2018-07-27 22:25:03 +01:00
SarahW
e64271f5bb Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR. 2018-07-27 22:24:34 +01:00
SarahW
cf508b050f End block when register version hits a maximum count. 2018-07-25 20:18:03 +01:00
SarahW
5ca2533f3c Increase ARM64 work registers from 5 to 10. 2018-07-25 20:17:42 +01:00