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Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG.

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This commit is contained in:
SarahW 2018-08-08 22:14:22 +01:00
commit 9bba93e0be
19 changed files with 938 additions and 29 deletions
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44
src/codegen_backend_arm64_uops.c
View file

@ -127,6 +127,34 @@ static int codegen_AND(codeblock_t *block, uop_t *uop)
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff00ff);
host_arm64_AND_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b))
{
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b))
{
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b))
{
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff00ff);
host_arm64_AND_REG_ROR(block, REG_TEMP, src_reg_a, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b))
{
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_a, 0xffff00ff);
host_arm64_AND_REG_ROR(block, REG_TEMP, src_reg_b, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b))
{
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
@ -149,6 +177,12 @@ static int codegen_AND_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_AND_IMM(block, dest_reg, src_reg, uop->imm_data | 0xffffff00);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size))
{
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm64_AND_IMM(block, dest_reg, src_reg, (uop->imm_data << 8) | 0xffff00ff);
@ -494,6 +528,16 @@ static int codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
host_arm64_AND_IMM(block, dest_reg, src_reg, 0xffff);
}
else if (REG_IS_W(dest_size) && REG_IS_B(src_size))
{
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xff);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_W(dest_size) && REG_IS_BH(src_size))
{
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);

22
src/codegen_backend_arm_ops.c
View file

@ -216,12 +216,34 @@ void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int sr
{
codegen_addlong(block, COND_AL | OPCODE_AND_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void host_arm_AND_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_AND_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void host_arm_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
{
codegen_addlong(block, OPCODE_BFI | Rd(dst_reg) | Rm(src_reg) | BFI_lsb(lsb) | BFI_msb((lsb + width) - 1));
}
void host_arm_BIC_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm))
{
codegen_addlong(block, COND_AL | OPCODE_BIC_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
}
else if (get_arm_imm(~imm, &arm_imm))
{
codegen_addlong(block, COND_AL | OPCODE_AND_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
}
else
{
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_BIC_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void host_arm_BIC_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_BIC_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));

2
src/codegen_backend_arm_ops.h
View file

@ -5,9 +5,11 @@ void host_arm_ADD_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int sr
void host_arm_AND_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_AND_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width);
void host_arm_BIC_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_BIC_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_BIC_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);

58
src/codegen_backend_arm_uops.c
View file

@ -194,6 +194,32 @@ static int codegen_AND(codeblock_t *block, uop_t *uop)
host_arm_AND_IMM(block, REG_TEMP, REG_TEMP, 0x0000ff00);
host_arm_BIC_REG_LSL(block, dest_reg, src_reg_a, REG_TEMP, 0);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b))
{
host_arm_AND_REG_LSL(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b))
{
host_arm_AND_REG_LSL(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b))
{
host_arm_AND_REG_LSR(block, REG_TEMP, src_reg_a, src_reg_b, 8);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b))
{
host_arm_AND_REG_LSR(block, REG_TEMP, src_reg_b, src_reg_a, 8);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b))
{
host_arm_AND_REG_LSL(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
@ -220,6 +246,22 @@ static int codegen_AND_IMM(codeblock_t *block, uop_t *uop)
{
host_arm_AND_IMM(block, dest_reg, src_reg, (uop->imm_data << 8) | 0xffff00ff);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_AND_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_AND_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_B(dest_size) && REG_IS_BH(src_size))
{
host_arm_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm_AND_IMM(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else
fatal("AND_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
@ -562,6 +604,22 @@ static int codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
host_arm_UXTH(block, dest_reg, src_reg, 0);
}
else if (REG_IS_W(dest_size) && REG_IS_B(src_size))
{
if (src_reg == dest_reg)
host_arm_BIC_IMM(block, dest_reg, dest_reg, 0xff00);
else
{
host_arm_UXTB(block, REG_TEMP, src_reg, 0);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
}
else if (REG_IS_W(dest_size) && REG_IS_BH(src_size))
{
host_arm_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm_BIC_IMM(block, dest_reg, dest_reg, 0xff00);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);

12
src/codegen_backend_x86-64_ops.c
View file

@ -242,21 +242,21 @@ void host_x86_AND32_REG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32
void host_x86_AND8_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
if (dst_reg != src_reg_a || (dst_reg & 8) || (src_reg_b & 8))
fatal("host_x86_AND8_REG_IMM - dst_reg != src_reg_a\n");
fatal("host_x86_AND8_REG_REG - dst_reg != src_reg_a\n");
codegen_addbyte2(block, 0x20, 0xc0 | (dst_reg & 7) | ((src_reg_b & 7) << 3)); /*AND dst_reg, src_reg_b*/
}
void host_x86_AND16_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
if (dst_reg != src_reg_a || (dst_reg & 8) || (src_reg_b & 8))
fatal("host_x86_AND16_REG_IMM - dst_reg != src_reg_a\n");
fatal("host_x86_AND16_REG_REG - dst_reg != src_reg_a\n");
codegen_addbyte3(block, 0x66, 0x21, 0xc0 | (dst_reg & 7) | ((src_reg_b & 7) << 3)); /*AND dst_reg, src_reg_b*/
}
void host_x86_AND32_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
if (dst_reg != src_reg_a || (dst_reg & 8) || (src_reg_b & 8))
fatal("host_x86_AND32_REG_IMM - dst_reg != src_reg_a\n");
fatal("host_x86_AND32_REG_REG - dst_reg != src_reg_a\n");
codegen_addbyte2(block, 0x21, 0xc0 | (dst_reg & 7) | ((src_reg_b & 7) << 3)); /*AND dst_reg, src_reg_b*/
}
@ -688,6 +688,12 @@ void host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_r
codegen_addbyte4(block, 0x0f, 0xb7, 0x04 | (dst_reg << 3), (index_reg << 3) | base_reg);
}
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOVZX_REG_16_8 - bad reg\n");
codegen_addbyte4(block, 0x66, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))

1
src/codegen_backend_x86-64_ops.h
View file

@ -69,6 +69,7 @@ void host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_r
void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);

28
src/codegen_backend_x86-64_uops.c
View file

@ -98,15 +98,21 @@ static int codegen_AND(codeblock_t *block, uop_t *uop)
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b))
{
host_x86_AND32_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (dest_reg != src_reg_a)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND32_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b))
{
host_x86_AND16_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (dest_reg != src_reg_a)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND16_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b))
{
host_x86_AND8_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (dest_reg != src_reg_a)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND8_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
@ -121,15 +127,21 @@ static int codegen_AND_IMM(codeblock_t *block, uop_t *uop)
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_x86_AND32_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (dest_reg != src_reg)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_AND32_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_x86_AND16_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (dest_reg != src_reg)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_AND16_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_x86_AND8_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (dest_reg != src_reg)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_AND8_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else
fatal("AND_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
@ -445,6 +457,10 @@ static int codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
host_x86_MOVZX_REG_32_8(block, dest_reg, src_reg);
}
else if (REG_IS_W(dest_size) && REG_IS_B(src_size))
{
host_x86_MOVZX_REG_16_8(block, dest_reg, src_reg);
}
else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;

4
src/codegen_backend_x86_ops.c
View file

@ -599,6 +599,10 @@ void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
}
}
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addbyte4(block, 0x66, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addbyte3(block, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/

1
src/codegen_backend_x86_ops.h
View file

@ -66,6 +66,7 @@ void host_x86_MOV32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_data);
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);

28
src/codegen_backend_x86_uops.c
View file

@ -108,15 +108,21 @@ static int codegen_AND(codeblock_t *block, uop_t *uop)
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b))
{
host_x86_AND32_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND32_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b))
{
host_x86_AND16_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND16_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b))
{
host_x86_AND8_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND8_REG_REG(block, dest_reg, dest_reg, src_reg_b);
}
else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
@ -131,15 +137,21 @@ static int codegen_AND_IMM(codeblock_t *block, uop_t *uop)
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_x86_AND32_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_AND32_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_x86_AND16_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_AND16_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_x86_AND8_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_AND8_REG_IMM(block, dest_reg, dest_reg, uop->imm_data);
}
else
fatal("AND_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
@ -442,6 +454,10 @@ static int codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
host_x86_MOVZX_REG_32_8(block, dest_reg, src_reg);
}
else if (REG_IS_W(dest_size) && REG_IS_B(src_size))
{
host_x86_MOVZX_REG_16_8(block, dest_reg, src_reg);
}
else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;

24
src/codegen_ops.c
View file

@ -20,18 +20,18 @@ RecompOpFn recomp_opcodes[512] =
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPUSH_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16, ropPOP_r16,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_imm_16, NULL, ropPUSH_imm_16_8,NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ rop80, rop81_w, rop80, rop83_w, NULL, NULL, NULL, NULL, ropMOV_b_r, ropMOV_w_r, ropMOV_r_b, ropMOV_r_w, NULL, NULL, NULL, ropPOP_W,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_abs, ropMOV_AX_abs, ropMOV_abs_AL, ropMOV_abs_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ rop80, rop81_w, rop80, rop83_w, ropTEST_b_rm, ropTEST_w_rm, ropXCHG_8, ropXCHG_16, ropMOV_b_r, ropMOV_w_r, ropMOV_r_b, ropMOV_r_w, ropMOV_w_seg, ropLEA_16, ropMOV_seg_w, ropPOP_W,
/*90*/ ropNOP, ropXCHG_AX, ropXCHG_AX, ropXCHG_AX, ropXCHG_AX, ropXCHG_AX, ropXCHG_AX, ropXCHG_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_abs, ropMOV_AX_abs, ropMOV_abs_AL, ropMOV_abs_AX, NULL, NULL, NULL, NULL, ropTEST_AL_imm, ropTEST_AX_imm, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm, ropMOV_rw_imm,
/*c0*/ NULL, NULL, ropRET_imm_16, ropRET_16, NULL, NULL, ropMOV_b_imm, ropMOV_w_imm, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropCALL_r16, ropJMP_r16, NULL, ropJMP_r8, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFF_16,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFF_16,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
@ -42,18 +42,18 @@ RecompOpFn recomp_opcodes[512] =
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPUSH_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32, ropPOP_r32,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_imm_32, NULL, ropPUSH_imm_32_8,NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ rop80, rop81_l, rop80, rop83_l, NULL, NULL, NULL, NULL, ropMOV_b_r, ropMOV_l_r, ropMOV_r_b, ropMOV_r_l, NULL, NULL, NULL, ropPOP_L,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_abs, ropMOV_EAX_abs, ropMOV_abs_AL, ropMOV_abs_EAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ rop80, rop81_l, rop80, rop83_l, ropTEST_b_rm, ropTEST_l_rm, ropXCHG_8, ropXCHG_32, ropMOV_b_r, ropMOV_l_r, ropMOV_r_b, ropMOV_r_l, ropMOV_l_seg, ropLEA_32, ropMOV_seg_w, ropPOP_L,
/*90*/ ropNOP, ropXCHG_EAX, ropXCHG_EAX, ropXCHG_EAX, ropXCHG_EAX, ropXCHG_EAX, ropXCHG_EAX, ropXCHG_EAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropMOV_AL_abs, ropMOV_EAX_abs, ropMOV_abs_AL, ropMOV_abs_EAX, NULL, NULL, NULL, NULL, ropTEST_AL_imm, ropTEST_EAX_imm,NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rb_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm, ropMOV_rl_imm,
/*c0*/ NULL, NULL, ropRET_imm_32, ropRET_32, NULL, NULL, ropMOV_b_imm, ropMOV_l_imm, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropCALL_r32, ropJMP_r32, NULL, ropJMP_r8, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFF_32
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_32, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFF_32
};
@ -74,7 +74,7 @@ RecompOpFn recomp_opcodes_0f[512] =
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_16, ropPOP_FS_16, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_16, ropPOP_GS_16, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropMOVZX_16_8, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@ -96,7 +96,7 @@ RecompOpFn recomp_opcodes_0f[512] =
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ ropPUSH_FS_32, ropPOP_FS_32, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_GS_32, ropPOP_GS_32, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropMOVZX_32_8, ropMOVZX_32_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

111
src/codegen_ops_logic.c
View file

@ -418,6 +418,117 @@ uint32_t ropOR_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
return op_pc + 1;
}
uint32_t ropTEST_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropTEST_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 2;
}
uint32_t ropTEST_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t ropTEST_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_8(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropTEST_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_16(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropTEST_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res, IREG_32(dest_reg), IREG_32(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res, IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropXOR_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);

7
src/codegen_ops_logic.h
View file

@ -18,6 +18,13 @@ uint32_t ropOR_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropOR_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);

239
src/codegen_ops_misc.c
View file

@ -1,6 +1,7 @@
#include "ibm.h"
#include "x86.h"
#include "x86_flags.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
@ -8,6 +9,235 @@
#include "codegen_ops_helpers.h"
#include "codegen_ops_misc.h"
uint32_t ropLEA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
uop_MOV(ir, IREG_16(dest_reg), IREG_eaaddr_W);
return op_pc + 1;
}
uint32_t ropLEA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
uop_MOV(ir, IREG_32(dest_reg), IREG_eaaddr);
return op_pc + 1;
}
uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
uint8_t imm_data;
int reg;
if (fetchdat & 0x20)
return 0;
if ((fetchdat & 0xc0) == 0xc0)
reg = IREG_8(fetchdat & 7);
else
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
codegen_check_seg_write(block, ir, target_seg);
else
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
reg = IREG_temp0_B;
}
switch (fetchdat & 0x38)
{
case 0x00: case 0x08: /*TEST*/
imm_data = fastreadb(cs + op_pc + 1);
uop_AND_IMM(ir, IREG_flags_res_B, reg, imm_data);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc+2;
case 0x10: /*NOT*/
uop_XOR_IMM(ir, reg, reg, 0xff);
if ((fetchdat & 0xc0) != 0xc0)
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
codegen_flags_changed = 1;
return op_pc+1;
case 0x18: /*NEG*/
uop_MOV_IMM(ir, IREG_temp1_B, 0);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOVZX(ir, IREG_flags_op2, reg);
uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, reg);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
uop_MOV(ir, reg, IREG_temp1_B);
}
else
{
uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
uop_MOV_IMM(ir, IREG_flags_op1, 0);
codegen_flags_changed = 1;
return op_pc+1;
}
return 0;
}
uint32_t ropF7_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
uint16_t imm_data;
int reg;
if (fetchdat & 0x20)
return 0;
if ((fetchdat & 0xc0) == 0xc0)
reg = IREG_16(fetchdat & 7);
else
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
codegen_check_seg_write(block, ir, target_seg);
else
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
reg = IREG_temp0_W;
}
switch (fetchdat & 0x38)
{
case 0x00: case 0x08: /*TEST*/
imm_data = fastreadw(cs + op_pc + 1);
uop_AND_IMM(ir, IREG_flags_res_W, reg, imm_data);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc+3;
case 0x10: /*NOT*/
uop_XOR_IMM(ir, reg, reg, 0xffff);
if ((fetchdat & 0xc0) != 0xc0)
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
codegen_flags_changed = 1;
return op_pc+1;
case 0x18: /*NEG*/
uop_MOV_IMM(ir, IREG_temp1_W, 0);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOVZX(ir, IREG_flags_op2, reg);
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, reg);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
uop_MOV(ir, reg, IREG_temp1_W);
}
else
{
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOV_IMM(ir, IREG_flags_op1, 0);
codegen_flags_changed = 1;
return op_pc+1;
}
return 0;
}
uint32_t ropF7_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
uint32_t imm_data;
int reg;
if (fetchdat & 0x20)
return 0;
if ((fetchdat & 0xc0) == 0xc0)
reg = IREG_32(fetchdat & 7);
else
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
codegen_check_seg_write(block, ir, target_seg);
else
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
reg = IREG_temp0;
}
switch (fetchdat & 0x38)
{
case 0x00: case 0x08: /*TEST*/
imm_data = fastreadl(cs + op_pc + 1);
uop_AND_IMM(ir, IREG_flags_res, reg, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc+5;
case 0x10: /*NOT*/
uop_XOR_IMM(ir, reg, reg, 0xffffffff);
if ((fetchdat & 0xc0) != 0xc0)
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
codegen_flags_changed = 1;
return op_pc+1;
case 0x18: /*NEG*/
uop_MOV_IMM(ir, IREG_temp1, 0);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOV(ir, IREG_flags_op2, reg);
uop_SUB(ir, IREG_temp1, IREG_temp1, reg);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
uop_MOV(ir, reg, IREG_temp1);
}
else
{
uop_SUB(ir, IREG_temp1, IREG_temp1, reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV_IMM(ir, IREG_flags_op1, 0);
codegen_flags_changed = 1;
return op_pc+1;
}
return 0;
}
uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg, sp_reg;
@ -49,7 +279,7 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, src_reg);
SUB_SP(ir, 2);
return -1;
return op_pc+1;
}
return 0;
}
@ -95,7 +325,12 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, src_reg);
SUB_SP(ir, 4);
return -1;
return op_pc+1;
}
return 0;
}
uint32_t ropNOP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
return op_pc;
}

9
src/codegen_ops_misc.h
View file

@ -1,2 +1,11 @@
uint32_t ropLEA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLEA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF7_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF7_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropNOP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);

307
src/codegen_ops_mov.c
View file

@ -322,3 +322,310 @@ uint32_t ropMOV_l_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
return op_pc + 5;
}
uint32_t ropMOV_w_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
src_reg = IREG_ES_seg_W;
break;
case 0x08: /*CS*/
src_reg = IREG_CS_seg_W;
break;
case 0x18: /*DS*/
src_reg = IREG_DS_seg_W;
break;
case 0x10: /*SS*/
src_reg = IREG_SS_seg_W;
break;
case 0x20: /*FS*/
src_reg = IREG_FS_seg_W;
break;
case 0x28: /*GS*/
src_reg = IREG_GS_seg_W;
break;
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_16(dest_reg), src_reg);
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, src_reg);
}
return op_pc + 1;
}
uint32_t ropMOV_l_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
src_reg = IREG_ES_seg_W;
break;
case 0x08: /*CS*/
src_reg = IREG_CS_seg_W;
break;
case 0x18: /*DS*/
src_reg = IREG_DS_seg_W;
break;
case 0x10: /*SS*/
src_reg = IREG_SS_seg_W;
break;
case 0x20: /*FS*/
src_reg = IREG_FS_seg_W;
break;
case 0x28: /*GS*/
src_reg = IREG_GS_seg_W;
break;
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), src_reg);
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, src_reg);
}
return op_pc + 1;
}
uint32_t ropMOV_seg_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
x86seg *rseg;
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
rseg = &cpu_state.seg_es;
break;
case 0x18: /*DS*/
rseg = &cpu_state.seg_ds;
break;
case 0x20: /*FS*/
rseg = &cpu_state.seg_fs;
break;
case 0x28: /*GS*/
rseg = &cpu_state.seg_gs;
break;
default:
return 0;
}
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOV(ir, IREG_temp0_W, IREG_16(fetchdat & 7));
src_reg = IREG_temp0_W;
}
else
{
x86seg *target_seg;
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
src_reg = IREG_temp0_W;
}
uop_LOAD_SEG(ir, rseg, src_reg);
return op_pc + 1;
}
uint32_t ropMOVZX_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_16(dest_reg), IREG_8(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_16(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t ropMOVZX_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), IREG_8(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_32(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t ropMOVZX_32_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), IREG_16(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_32(dest_reg), IREG_temp0_W);
}
return op_pc + 1;
}
uint32_t ropXCHG_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg2 = IREG_16(opcode & 7);
uop_MOV(ir, IREG_temp0_W, IREG_AX);
uop_MOV(ir, IREG_AX, reg2);
uop_MOV(ir, reg2, IREG_temp0_W);
return op_pc;
}
uint32_t ropXCHG_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg2 = IREG_32(opcode & 7);
uop_MOV(ir, IREG_temp0, IREG_EAX);
uop_MOV(ir, IREG_EAX, reg2);
uop_MOV(ir, reg2, IREG_temp0);
return op_pc;
}
uint32_t ropXCHG_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_8((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
int reg2 = IREG_8(fetchdat & 7);
uop_MOV(ir, IREG_temp0_B, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0_B);
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t ropXCHG_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_16((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
int reg2 = IREG_16(fetchdat & 7);
uop_MOV(ir, IREG_temp0_W, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0_W);
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0_W);
}
return op_pc + 1;
}
uint32_t ropXCHG_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_32((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
int reg2 = IREG_32(fetchdat & 7);
uop_MOV(ir, IREG_temp0, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0);
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0);
}
return op_pc + 1;
}

15
src/codegen_ops_mov.h
View file

@ -20,3 +20,18 @@ uint32_t ropMOV_abs_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
uint32_t ropMOV_b_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_w_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_l_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_w_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_l_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_seg_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_32_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);

50
src/codegen_ops_stack.c
View file

@ -64,6 +64,56 @@ uint32_t ropPOP_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
return op_pc;
}
uint32_t ropPUSH_imm_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t imm = fastreadw(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 2);
return op_pc + 2;
}
uint32_t ropPUSH_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t imm = fastreadl(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 4);
return op_pc + 4;
}
uint32_t ropPUSH_imm_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t imm = (int16_t)(int8_t)fastreadb(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 2);
return op_pc + 1;
}
uint32_t ropPUSH_imm_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t imm = (int32_t)(int8_t)fastreadb(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 4);
return op_pc + 1;
}
uint32_t ropPOP_W(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);

5
src/codegen_ops_stack.h
View file

@ -4,6 +4,11 @@ uint32_t ropPUSH_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropPOP_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPOP_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUSH_imm_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUSH_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUSH_imm_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUSH_imm_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPOP_W(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPOP_L(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);