SarahW
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1b73963997
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Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing.
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2016-11-25 21:32:02 +00:00 |
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SarahW
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c664682758
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Move some more variables into cpu_state structure. Minor speedup (~2%).
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2016-08-17 21:28:16 +01:00 |
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SarahW
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535604b760
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Pack decoded ModR/M data into a single word - minor recompiler speedup.
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2016-08-14 16:29:54 +01:00 |
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SarahW
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c81a91fd72
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Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).
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2016-04-20 21:39:41 +01:00 |
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TomW
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28a2336aae
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MOV DRx now loads/stores from 'dummy' DRx registers (BeOS).
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2015-05-03 14:42:34 +01:00 |
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TomW
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2905c43db8
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Cycle counts for recompiled blocks now generated at compile time.
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2014-11-12 19:33:49 +00:00 |
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TomW
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4676daade4
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Initial commit of dynamic recompiler.
Various CPU changes to support dynamic recompiler.
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2014-11-05 21:24:16 +00:00 |
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TomW
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262b188790
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Implemented CR4 register for Winchip. Currently only Time Stamp Disable (TSD) has an effect.
Fixed stupid bug in WRMSR - MSRs can now be written with values other than zero.
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2014-08-23 16:28:16 +01:00 |
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TomW
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e737d2fa45
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Loading a segment register in real mode no longer clears USE32.
CR3 no longer masks values written to it.
Real mode interrupts now take IDT base into account.
Fixes 'huge unreal' mode (flat assembler).
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2014-03-29 14:28:13 +00:00 |
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TomW
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f822488656
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Add missing files from last commit.
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2013-05-27 19:56:33 +01:00 |
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