SarahW
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a9541dadea
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Added preliminary emulation of AMD K6 CPUs.
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2018-12-06 20:02:35 +00:00 |
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SarahW
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7ec6f1e4ce
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Added Winchip 2 timing model.
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2018-12-05 20:54:56 +00:00 |
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SarahW
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9b8b6c2c70
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Add Winchip 2A CPUs.
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2018-12-04 21:35:51 +00:00 |
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SarahW
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ca39b51803
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Fix address calculation on PCMPEQD and PCMPGTD.
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2018-12-04 21:35:26 +00:00 |
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SarahW
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da2d819ed4
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Added WinChip 2 emulation, along with (currently non-recompiled) 3DNow! instruction emulation.
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2018-12-03 21:59:41 +00:00 |
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SarahW
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5043cff3f9
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Move SFF-8038i IDE bus mastering code out of PIIX files.
Add bus mastering to VT82C586B emulation.
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2018-12-02 15:46:28 +00:00 |
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SarahW
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99ca11d148
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Added initial emulation of FIC VA-503+ (Super 7).
This includes preliminary emulation of the VIA MVP3 northbridge, VT82C586B 'PIPC' southbridge, and Winbond W83877TF SuperIO chip.
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2018-12-02 12:38:31 +00:00 |
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SarahW
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d5f07a8594
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Fix bad use of flags variable in wx-sdl2-display.c.
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2018-11-30 13:19:16 +00:00 |
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SarahW
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43b5b83644
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Reduce codeblock_hash table to uint16_t.
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2018-11-30 13:18:56 +00:00 |
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SarahW
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9ff1c7f409
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Further reductions to codeblock_t size - replace link pointers with uint16_t block indicies, shrink ins to uint8_t, remove endpc. codeblock_t now fits in a 64-byte cacheline on 32-bit platforms.
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2018-11-29 20:05:12 +00:00 |
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SarahW
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2007c25177
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Start reducing size of codeblock_t structure.
Re-arrange all variables needed to run a block to fit in a single cache line.
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2018-11-28 20:29:48 +00:00 |
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SarahW
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d63176e472
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Move dynarec code memory out of codeblock structure.
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2018-11-28 18:43:40 +00:00 |
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SarahW
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356f406b22
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Fix codegen pointer register reads.
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2018-11-28 18:41:53 +00:00 |
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SarahW
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335cea3ee1
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Added recompiled versions of PUSHF and PUSHFD.
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2018-11-28 15:19:21 +00:00 |
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SarahW
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5df3f6caef
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Added recompiled versions of PUSHA and POPA.
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2018-11-28 11:50:24 +00:00 |
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SarahW
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e012420f90
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Added recompiled versions of CLC, CLD, CLI, CMC, STC, STD and STI.
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2018-11-28 09:58:50 +00:00 |
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SarahW
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a4d3aa1912
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Move flags and eflags variables into cpu_struct.
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2018-11-28 09:42:04 +00:00 |
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SarahW
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c1565eb42f
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Fix partial register handling - removes pointless loads when writing to non-32-bit registers (eg FPU or MMX).
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2018-11-27 19:43:01 +00:00 |
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SarahW
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92ab0ee8ef
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Fix flags on 8-bit memory INC/DEC.
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2018-11-27 10:15:18 +00:00 |
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SarahW
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07035c97c8
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Added recompiled versions of FABS, FCHS, FSQRT and FTST.
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2018-11-26 17:00:00 +00:00 |
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SarahW
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856f0b4471
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ARM64 MMX fixes
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2018-11-25 17:59:38 +00:00 |
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SarahW
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6341caf318
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ARM MMX fixes
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2018-11-24 20:35:33 +00:00 |
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SarahW
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2a19183d83
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Added debug code to log execution rate of non-recompiled instructions.
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2018-11-24 20:16:52 +00:00 |
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SarahW
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086422b79f
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Added recompiled versions of PMULLW, PMULHW and PMADDWD.
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2018-11-24 12:52:08 +00:00 |
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SarahW
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77af266ab2
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Added recompiled versions of PACK* and PUNPCK *
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2018-11-23 18:34:30 +00:00 |
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SarahW
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a991bc3249
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Added recompiled versions of PCMP*
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2018-11-23 15:17:21 +00:00 |
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SarahW
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e43a2a6be0
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Added recompiled versions of PSLL*, PSLR* and PSAR* with immediate shifts.
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2018-11-22 18:43:36 +00:00 |
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SarahW
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35b9e0811b
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Added recompiled versions of PADD* and PSUB*.
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2018-11-22 15:57:44 +00:00 |
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SarahW
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78c604c731
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Added recompiled versions of PAND, PANDN, POR and PXOR
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2018-11-21 20:51:34 +00:00 |
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SarahW
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76115568f2
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Added recompiled versions of MOVD and MOVQ.
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2018-11-21 17:02:20 +00:00 |
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SarahW
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f545d9d57f
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Rename FPU stack-based integer mirror registers, to avoid confusion with non-stack-based MMX registers.
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2018-11-21 12:44:47 +00:00 |
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SarahW
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fa4ccece48
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Fixed pixel clock on S3 ViRGE.
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2018-11-20 09:40:54 +00:00 |
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SarahW
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964b20e820
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Added recompiled versions of FLD1 and FLDZ.
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2018-11-14 21:43:22 +00:00 |
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SarahW
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0055238ade
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Added recompiled versions of FCOM, FCOMP, FCOMPP, FICOM, FICOM, FUCOM, FUCOMP and FUCOMPP.
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2018-11-14 21:42:20 +00:00 |
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SarahW
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b814bcc80d
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Added recompiled versions of FSTCW and FSTSW.
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2018-10-25 21:43:32 +01:00 |
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SarahW
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87191dde55
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Added recompiled versions of FIST and FISTP.
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2018-10-25 20:54:33 +01:00 |
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SarahW
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589f50e479
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Added recompiled version of FILDq.
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2018-10-22 21:23:09 +01:00 |
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SarahW
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bce9ad4f3d
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Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH.
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2018-10-21 16:22:20 +01:00 |
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SarahW
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6d8af5df4a
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Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR.
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2018-10-20 20:03:28 +01:00 |
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SarahW
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8a516df476
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Added recompiled versions of FLD, FILD, FST and FSTP.
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2018-10-17 19:47:04 +01:00 |
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SarahW
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e17a94a409
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FDIVP/FDIVRP should pop the stack when a divide by zero occurs and the exception is masked. Fixes software rendering on Need for Speed III.
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2018-10-09 22:10:29 +01:00 |
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SarahW
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829c74f2d5
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Don't write back unchanged registers on flush + invalidate.
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2018-10-09 14:07:49 +01:00 |
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SarahW
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d9e38fe37c
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Fix masking of FPU top-of-stack in several places. Fixes DOS Quake.
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2018-10-09 13:51:05 +01:00 |
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SarahW
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305b6cc4fd
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Added recompiled register versions of FADDP, FDIVP, FDIVRP, FMULP, FSUBP and FSUBRP.
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2018-10-08 21:44:30 +01:00 |
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SarahW
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78996b3e5c
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Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR.
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2018-10-07 22:02:31 +01:00 |
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SarahW
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dbb01ef9e2
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Cleaned up x87 tag register handling.
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2018-10-01 21:02:40 +01:00 |
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SarahW
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e9ff110021
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Fixed flags on register->register ADD/SUB opcode 00/01/28/29. Fixes rendering in Need For Speed II.
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2018-09-30 17:30:28 +01:00 |
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SarahW
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94fe85b17e
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Fixed video clock on Cirrus Logic cards.
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2018-09-29 17:43:02 +01:00 |
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SarahW
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592b07be63
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Added recompiled versions of JMP indirect, JMP far, RETF, LxS, XLAT and LEAVE.
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2018-09-29 17:42:44 +01:00 |
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SarahW
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1aadfd436d
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Added recompiled versions of CBW, CDQ, CWD, CWDE and MOVSX.
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2018-09-23 21:45:12 +01:00 |
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