Move SFF-8038i IDE bus mastering code out of PIIX files.
Add bus mastering to VT82C586B emulation.
This commit is contained in:
SarahW
parent
99ca11d148
commit
5043cff3f9
8 changed files with 282 additions and 226 deletions
16
src/ide.c
16
src/ide.c
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@ -94,9 +94,10 @@ IDE *ext_ide;
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char ide_fn[7][512];
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int (*ide_bus_master_read_data)(int channel, uint8_t *data, int size);
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int (*ide_bus_master_write_data)(int channel, uint8_t *data, int size);
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void (*ide_bus_master_set_irq)(int channel);
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int (*ide_bus_master_read_data)(int channel, uint8_t *data, int size, void *p);
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int (*ide_bus_master_write_data)(int channel, uint8_t *data, int size, void *p);
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void (*ide_bus_master_set_irq)(int channel, void *p);
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void *ide_bus_master_p;
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pc_timer_t ide_timer[2];
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@ -111,7 +112,7 @@ void ide_irq_raise(IDE *ide)
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// if (ide->board && !ide->irqstat) pclog("IDE_IRQ_RAISE\n");
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picint((ide->board)?(1<<15):(1<<14));
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if (ide_bus_master_set_irq)
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ide_bus_master_set_irq(ide->board);
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ide_bus_master_set_irq(ide->board, ide_bus_master_p);
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}
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ide->irqstat=1;
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ide->service=1;
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@ -905,7 +906,7 @@ void callbackide(int ide_board)
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if (ide_bus_master_read_data)
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{
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if (ide_bus_master_read_data(ide_board, &ide->sector_buffer[ide->sector_pos*512], 512))
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if (ide_bus_master_read_data(ide_board, &ide->sector_buffer[ide->sector_pos*512], 512, ide_bus_master_p))
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timer_set_delay_u64(&ide_timer[ide_board], 6*IDE_TIME); /*DMA not performed, try again later*/
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else
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{
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@ -983,7 +984,7 @@ void callbackide(int ide_board)
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if (ide_bus_master_write_data)
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{
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if (ide_bus_master_write_data(ide_board, (uint8_t *)ide->buffer, 512))
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if (ide_bus_master_write_data(ide_board, (uint8_t *)ide->buffer, 512, ide_bus_master_p))
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timer_set_delay_u64(&ide_timer[ide_board], 6*IDE_TIME); /*DMA not performed, try again later*/
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else
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{
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@ -1270,11 +1271,12 @@ static void ide_close(void *p)
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{
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}
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void ide_set_bus_master(int (*read_data)(int channel, uint8_t *data, int size), int (*write_data)(int channel, uint8_t *data, int size), void (*set_irq)(int channel))
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void ide_set_bus_master(int (*read_data)(int channel, uint8_t *data, int size, void *p), int (*write_data)(int channel, uint8_t *data, int size, void *p), void (*set_irq)(int channel, void *p), void *p)
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{
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ide_bus_master_read_data = read_data;
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ide_bus_master_write_data = write_data;
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ide_bus_master_set_irq = set_irq;
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ide_bus_master_p = p;
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}
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device_t ide_device =
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@ -16,12 +16,13 @@ extern void ide_pri_enable();
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extern void ide_sec_enable();
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extern void ide_pri_disable();
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extern void ide_sec_disable();
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extern void ide_set_bus_master(int (*read_data)(int channel, uint8_t *data, int size), int (*write_data)(int channel, uint8_t *data, int size), void (*set_irq)(int channel));
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extern void ide_set_bus_master(int (*read_data)(int channel, uint8_t *data, int size, void *p), int (*write_data)(int channel, uint8_t *data, int size, void *p), void (*set_irq)(int channel, void *p), void *p);
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void ide_irq_raise(struct IDE *ide);
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extern int (*ide_bus_master_read_data)(int channel, uint8_t *data, int size);
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extern int (*ide_bus_master_write_data)(int channel, uint8_t *data, int size);
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extern void (*ide_bus_master_set_irq)(int channel);
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extern int (*ide_bus_master_read_data)(int channel, uint8_t *data, int size, void *p);
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extern int (*ide_bus_master_write_data)(int channel, uint8_t *data, int size, void *p);
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extern void (*ide_bus_master_set_irq)(int channel, void *p);
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extern void *ide_bus_master_p;
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#include "ide_atapi.h"
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@ -258,7 +258,7 @@ void atapi_process_packet(atapi_device_t *atapi_dev)
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{
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if (ide_bus_master_write_data)
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{
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if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos))
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if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos, ide_bus_master_p))
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{
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atapi_dev->state = ATAPI_STATE_RETRY_WRITE_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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@ -430,7 +430,7 @@ void atapi_process_packet(atapi_device_t *atapi_dev)
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{
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if (ide_bus_master_read_data)
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{
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if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos))
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if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos, ide_bus_master_p))
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{
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atapi_dev->state = ATAPI_STATE_RETRY_READ_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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@ -535,7 +535,7 @@ void atapi_process_packet(atapi_device_t *atapi_dev)
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case ATAPI_STATE_RETRY_READ_DMA:
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{
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if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos))
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if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos, ide_bus_master_p))
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{
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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@ -549,7 +549,7 @@ void atapi_process_packet(atapi_device_t *atapi_dev)
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case ATAPI_STATE_RETRY_WRITE_DMA:
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{
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if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos))
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if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos, ide_bus_master_p))
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{
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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208
src/ide_sff8038i.c
Normal file
208
src/ide_sff8038i.c
Normal file
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@ -0,0 +1,208 @@
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/*Emulation of SFF-8038i IDE bus mastering interface.
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Used by PIIX and VT82C586B IDE controllers*/
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#include "ibm.h"
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#include "ide.h"
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#include "ide_sff8038i.h"
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#include "mem.h"
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static void sff_bus_master_next_addr(sff_busmaster_t *busmaster, int channel)
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{
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busmaster[channel].addr = (*(uint32_t *)(&ram[busmaster[channel].ptr_cur])) & ~1;
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busmaster[channel].count = (*(uint32_t *)(&ram[busmaster[channel].ptr_cur + 4])) & 0xfffe;
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if (!busmaster[channel].count)
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busmaster[channel].count = 0x10000;
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busmaster[channel].eot = (*(uint32_t *)(&ram[busmaster[channel].ptr_cur + 4])) >> 31;
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busmaster[channel].ptr_cur += 8;
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// pclog("New DMA settings on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
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}
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void sff_bus_master_write(uint16_t port, uint8_t val, void *p)
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{
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sff_busmaster_t *busmaster = (sff_busmaster_t *)p;
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int channel = (port & 8) ? 1 : 0;
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// pclog("PIIX Bus Master write %04X %02X %04x:%08x\n", port, val, CS, pc);
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switch (port & 7)
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{
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case 0:
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if ((val & 1) && !(busmaster[channel].command & 1)) /*Start*/
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{
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busmaster[channel].ptr_cur = busmaster[channel].ptr;
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sff_bus_master_next_addr(busmaster, channel);
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busmaster[channel].status |= 1;
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}
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if (!(val & 1) && (busmaster[channel].command & 1)) /*Stop*/
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busmaster[channel].status &= ~1;
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busmaster[channel].command = val;
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break;
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case 2:
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busmaster[channel].status = (val & 0x60) | ((busmaster[channel].status & ~val) & 6) | (busmaster[channel].status & 1);
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break;
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case 4:
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busmaster[channel].ptr = (busmaster[channel].ptr & 0xffffff00) | val;
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break;
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case 5:
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busmaster[channel].ptr = (busmaster[channel].ptr & 0xffff00ff) | (val << 8);
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break;
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case 6:
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busmaster[channel].ptr = (busmaster[channel].ptr & 0xff00ffff) | (val << 16);
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break;
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case 7:
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busmaster[channel].ptr = (busmaster[channel].ptr & 0x00ffffff) | (val << 24);
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break;
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}
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}
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uint8_t sff_bus_master_read(uint16_t port, void *p)
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{
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sff_busmaster_t *busmaster = (sff_busmaster_t *)p;
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int channel = (port & 8) ? 1 : 0;
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// pclog("PIIX Bus Master read %04X %04x:%08x\n", port, CS, pc);
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switch (port & 7)
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{
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case 0:
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return busmaster[channel].command;
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case 2:
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return busmaster[channel].status;
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case 4:
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return busmaster[channel].ptr;
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case 5:
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return busmaster[channel].ptr >> 8;
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case 6:
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return busmaster[channel].ptr >> 16;
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case 7:
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return busmaster[channel].ptr >> 24;
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}
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return 0xff;
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}
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static int sff_bus_master_data_read(int channel, uint8_t *data, int size, void *p)
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{
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sff_busmaster_t *busmaster = (sff_busmaster_t *)p;
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int transferred = 0;
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if (!(busmaster[channel].status & 1))
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return 1; /*DMA disabled*/
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while (transferred < size)
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{
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if (busmaster[channel].count < (size - transferred) && busmaster[channel].eot)
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fatal("DMA on channel %i - Read count less than size! Addr %08X Count %04X EOT %i size %i\n", channel, busmaster[channel].addr, busmaster[channel].count, busmaster[channel].eot, size);
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mem_invalidate_range(busmaster[channel].addr, busmaster[channel].addr+(size-1));
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if (busmaster[channel].count < (size - transferred))
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{
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// pclog("Transferring smaller - %i bytes\n", piix_busmaster[channel].count);
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if (busmaster[channel].addr < (mem_size * 1024))
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{
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int count = busmaster[channel].count;
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if ((busmaster[channel].addr + count) > (mem_size * 1024))
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count = (mem_size * 1024) - busmaster[channel].addr;
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memcpy(&ram[busmaster[channel].addr], data + transferred, count);
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}
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transferred += busmaster[channel].count;
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busmaster[channel].addr += busmaster[channel].count;
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busmaster[channel].count = 0;
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}
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else
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{
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// pclog("Transferring larger - %i bytes\n", size - transferred);
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if (busmaster[channel].addr < (mem_size * 1024))
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{
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int count = size - transferred;
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if ((busmaster[channel].addr + count) > (mem_size * 1024))
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count = (mem_size * 1024) - busmaster[channel].addr;
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memcpy(&ram[busmaster[channel].addr], data + transferred, count);
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}
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busmaster[channel].addr += (size - transferred);
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busmaster[channel].count -= (size - transferred);
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transferred += (size - transferred);
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}
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// pclog("DMA on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
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if (!busmaster[channel].count)
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{
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// pclog("DMA on channel %i - block over\n", channel);
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if (busmaster[channel].eot) /*End of transfer?*/
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{
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// pclog("DMA on channel %i - transfer over\n", channel);
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busmaster[channel].status &= ~1;
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}
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else
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sff_bus_master_next_addr(busmaster, channel);
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}
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}
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return 0;
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}
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static int sff_bus_master_data_write(int channel, uint8_t *data, int size, void *p)
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{
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sff_busmaster_t *busmaster = (sff_busmaster_t *)p;
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int transferred = 0;
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if (!(busmaster[channel].status & 1))
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return 1; /*DMA disabled*/
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while (transferred < size)
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{
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if (busmaster[channel].count < (size - transferred) && busmaster[channel].eot)
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fatal("DMA on channel %i - Write count less than size! Addr %08X Count %04X EOT %i size %i\n", channel, busmaster[channel].addr, busmaster[channel].count, busmaster[channel].eot, size);
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if (busmaster[channel].count < (size - transferred))
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{
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// pclog("Transferring smaller - %i bytes\n", piix_busmaster[channel].count);
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if (busmaster[channel].addr < (mem_size * 1024))
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{
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int count = busmaster[channel].count;
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if ((busmaster[channel].addr + count) > (mem_size * 1024))
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count = (mem_size * 1024) - busmaster[channel].addr;
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memcpy(data + transferred, &ram[busmaster[channel].addr], count);
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}
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transferred += busmaster[channel].count;
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busmaster[channel].addr += busmaster[channel].count;
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busmaster[channel].count = 0;
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}
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else
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{
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// pclog("Transferring larger - %i bytes\n", size - transferred);
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if (busmaster[channel].addr < (mem_size * 1024))
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{
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int count = size - transferred;
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if ((busmaster[channel].addr + count) > (mem_size * 1024))
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count = (mem_size * 1024) - busmaster[channel].addr;
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memcpy(data + transferred, &ram[busmaster[channel].addr], count);
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}
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busmaster[channel].addr += (size - transferred);
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busmaster[channel].count -= (size - transferred);
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transferred += (size - transferred);
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}
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// pclog("DMA on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
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if (!busmaster[channel].count)
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{
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// pclog("DMA on channel %i - block over\n", channel);
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if (busmaster[channel].eot) /*End of transfer?*/
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{
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// pclog("DMA on channel %i - transfer over\n", channel);
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busmaster[channel].status &= ~1;
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}
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else
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sff_bus_master_next_addr(busmaster, channel);
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}
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}
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return 0;
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}
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static void sff_bus_master_set_irq(int channel, void *p)
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{
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sff_busmaster_t *busmaster = (sff_busmaster_t *)p;
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busmaster[channel].status |= 4;
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}
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void sff_bus_master_init(sff_busmaster_t *busmaster)
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{
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ide_set_bus_master(sff_bus_master_data_read, sff_bus_master_data_write, sff_bus_master_set_irq, busmaster);
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}
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13
src/ide_sff8038i.h
Normal file
13
src/ide_sff8038i.h
Normal file
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@ -0,0 +1,13 @@
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typedef struct sff_busmaster_t
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{
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uint8_t command;
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uint8_t status;
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uint32_t ptr, ptr_cur;
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int count;
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uint32_t addr;
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int eot;
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} sff_busmaster_t;
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uint8_t sff_bus_master_read(uint16_t port, void *p);
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void sff_bus_master_write(uint16_t port, uint8_t val, void *p);
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void sff_bus_master_init(sff_busmaster_t *busmaster);
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@ -681,7 +681,7 @@ void model_init()
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{
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pclog("Initting as %s\n", model_getname());
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AMSTRAD = AT = PCI = TANDY = 0;
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ide_set_bus_master(NULL, NULL, NULL);
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ide_set_bus_master(NULL, NULL, NULL, NULL);
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models[model].init();
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if (models[model].device)
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213
src/piix.c
213
src/piix.c
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@ -7,6 +7,7 @@
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#include "ibm.h"
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#include "ide.h"
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#include "ide_sff8038i.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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@ -14,10 +15,8 @@
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#include "piix.h"
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uint8_t piix_bus_master_read(uint16_t port, void *priv);
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void piix_bus_master_write(uint16_t port, uint8_t val, void *priv);
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static uint8_t card_piix[256], card_piix_ide[256];
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static sff_busmaster_t piix_busmaster[2];
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void piix_write(int func, int addr, uint8_t val, void *priv)
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{
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@ -62,9 +61,9 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
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if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
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{
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uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
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io_removehandler(0, 0x10000, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
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io_removehandler(0, 0x10000, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, piix_busmaster);
|
||||
if (card_piix_ide[0x04] & 1)
|
||||
io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
|
||||
io_sethandler(base, 0x10, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, piix_busmaster);
|
||||
}
|
||||
if (addr == 4 || addr == 0x41 || addr == 0x43)
|
||||
{
|
||||
|
|
@ -140,206 +139,6 @@ uint8_t piix_read(int func, int addr, void *priv)
|
|||
return card_piix[addr];
|
||||
}
|
||||
|
||||
struct
|
||||
{
|
||||
uint8_t command;
|
||||
uint8_t status;
|
||||
uint32_t ptr, ptr_cur;
|
||||
int count;
|
||||
uint32_t addr;
|
||||
int eot;
|
||||
} piix_busmaster[2];
|
||||
|
||||
static void piix_bus_master_next_addr(int channel)
|
||||
{
|
||||
piix_busmaster[channel].addr = (*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur])) & ~1;
|
||||
piix_busmaster[channel].count = (*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur + 4])) & 0xfffe;
|
||||
if (!piix_busmaster[channel].count)
|
||||
piix_busmaster[channel].count = 0x10000;
|
||||
piix_busmaster[channel].eot = (*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur + 4])) >> 31;
|
||||
piix_busmaster[channel].ptr_cur += 8;
|
||||
// pclog("New DMA settings on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
|
||||
}
|
||||
|
||||
void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
|
||||
{
|
||||
int channel = (port & 8) ? 1 : 0;
|
||||
// pclog("PIIX Bus Master write %04X %02X %04x:%08x\n", port, val, CS, pc);
|
||||
switch (port & 7)
|
||||
{
|
||||
case 0:
|
||||
if ((val & 1) && !(piix_busmaster[channel].command & 1)) /*Start*/
|
||||
{
|
||||
piix_busmaster[channel].ptr_cur = piix_busmaster[channel].ptr;
|
||||
piix_bus_master_next_addr(channel);
|
||||
piix_busmaster[channel].status |= 1;
|
||||
}
|
||||
if (!(val & 1) && (piix_busmaster[channel].command & 1)) /*Stop*/
|
||||
piix_busmaster[channel].status &= ~1;
|
||||
|
||||
piix_busmaster[channel].command = val;
|
||||
break;
|
||||
case 2:
|
||||
piix_busmaster[channel].status = (val & 0x60) | ((piix_busmaster[channel].status & ~val) & 6) | (piix_busmaster[channel].status & 1);
|
||||
break;
|
||||
case 4:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffffff00) | val;
|
||||
break;
|
||||
case 5:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffff00ff) | (val << 8);
|
||||
break;
|
||||
case 6:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xff00ffff) | (val << 16);
|
||||
break;
|
||||
case 7:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0x00ffffff) | (val << 24);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t piix_bus_master_read(uint16_t port, void *priv)
|
||||
{
|
||||
int channel = (port & 8) ? 1 : 0;
|
||||
// pclog("PIIX Bus Master read %04X %04x:%08x\n", port, CS, pc);
|
||||
switch (port & 7)
|
||||
{
|
||||
case 0:
|
||||
return piix_busmaster[channel].command;
|
||||
case 2:
|
||||
return piix_busmaster[channel].status;
|
||||
case 4:
|
||||
return piix_busmaster[channel].ptr;
|
||||
case 5:
|
||||
return piix_busmaster[channel].ptr >> 8;
|
||||
case 6:
|
||||
return piix_busmaster[channel].ptr >> 16;
|
||||
case 7:
|
||||
return piix_busmaster[channel].ptr >> 24;
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
int piix_bus_master_data_read(int channel, uint8_t *data, int size)
|
||||
{
|
||||
int transferred = 0;
|
||||
|
||||
if (!(piix_busmaster[channel].status & 1))
|
||||
return 1; /*DMA disabled*/
|
||||
|
||||
while (transferred < size)
|
||||
{
|
||||
if (piix_busmaster[channel].count < (size - transferred) && piix_busmaster[channel].eot)
|
||||
fatal("DMA on channel %i - Read count less than size! Addr %08X Count %04X EOT %i size %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot, size);
|
||||
|
||||
mem_invalidate_range(piix_busmaster[channel].addr, piix_busmaster[channel].addr+(size-1));
|
||||
|
||||
if (piix_busmaster[channel].count < (size - transferred))
|
||||
{
|
||||
// pclog("Transferring smaller - %i bytes\n", piix_busmaster[channel].count);
|
||||
if (piix_busmaster[channel].addr < (mem_size * 1024))
|
||||
{
|
||||
int count = piix_busmaster[channel].count;
|
||||
if ((piix_busmaster[channel].addr + count) > (mem_size * 1024))
|
||||
count = (mem_size * 1024) - piix_busmaster[channel].addr;
|
||||
memcpy(&ram[piix_busmaster[channel].addr], data + transferred, count);
|
||||
}
|
||||
transferred += piix_busmaster[channel].count;
|
||||
piix_busmaster[channel].addr += piix_busmaster[channel].count;
|
||||
piix_busmaster[channel].count = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
// pclog("Transferring larger - %i bytes\n", size - transferred);
|
||||
if (piix_busmaster[channel].addr < (mem_size * 1024))
|
||||
{
|
||||
int count = size - transferred;
|
||||
if ((piix_busmaster[channel].addr + count) > (mem_size * 1024))
|
||||
count = (mem_size * 1024) - piix_busmaster[channel].addr;
|
||||
memcpy(&ram[piix_busmaster[channel].addr], data + transferred, count);
|
||||
}
|
||||
piix_busmaster[channel].addr += (size - transferred);
|
||||
piix_busmaster[channel].count -= (size - transferred);
|
||||
transferred += (size - transferred);
|
||||
}
|
||||
|
||||
// pclog("DMA on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
|
||||
|
||||
if (!piix_busmaster[channel].count)
|
||||
{
|
||||
// pclog("DMA on channel %i - block over\n", channel);
|
||||
if (piix_busmaster[channel].eot) /*End of transfer?*/
|
||||
{
|
||||
// pclog("DMA on channel %i - transfer over\n", channel);
|
||||
piix_busmaster[channel].status &= ~1;
|
||||
}
|
||||
else
|
||||
piix_bus_master_next_addr(channel);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
int piix_bus_master_data_write(int channel, uint8_t *data, int size)
|
||||
{
|
||||
int transferred = 0;
|
||||
|
||||
if (!(piix_busmaster[channel].status & 1))
|
||||
return 1; /*DMA disabled*/
|
||||
|
||||
while (transferred < size)
|
||||
{
|
||||
if (piix_busmaster[channel].count < (size - transferred) && piix_busmaster[channel].eot)
|
||||
fatal("DMA on channel %i - Write count less than size! Addr %08X Count %04X EOT %i size %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot, size);
|
||||
|
||||
if (piix_busmaster[channel].count < (size - transferred))
|
||||
{
|
||||
// pclog("Transferring smaller - %i bytes\n", piix_busmaster[channel].count);
|
||||
if (piix_busmaster[channel].addr < (mem_size * 1024))
|
||||
{
|
||||
int count = piix_busmaster[channel].count;
|
||||
if ((piix_busmaster[channel].addr + count) > (mem_size * 1024))
|
||||
count = (mem_size * 1024) - piix_busmaster[channel].addr;
|
||||
memcpy(data + transferred, &ram[piix_busmaster[channel].addr], count);
|
||||
}
|
||||
transferred += piix_busmaster[channel].count;
|
||||
piix_busmaster[channel].addr += piix_busmaster[channel].count;
|
||||
piix_busmaster[channel].count = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
// pclog("Transferring larger - %i bytes\n", size - transferred);
|
||||
if (piix_busmaster[channel].addr < (mem_size * 1024))
|
||||
{
|
||||
int count = size - transferred;
|
||||
if ((piix_busmaster[channel].addr + count) > (mem_size * 1024))
|
||||
count = (mem_size * 1024) - piix_busmaster[channel].addr;
|
||||
memcpy(data + transferred, &ram[piix_busmaster[channel].addr], count);
|
||||
}
|
||||
piix_busmaster[channel].addr += (size - transferred);
|
||||
piix_busmaster[channel].count -= (size - transferred);
|
||||
transferred += (size - transferred);
|
||||
}
|
||||
|
||||
// pclog("DMA on channel %i - Addr %08X Count %04X EOT %i\n", channel, piix_busmaster[channel].addr, piix_busmaster[channel].count, piix_busmaster[channel].eot);
|
||||
|
||||
if (!piix_busmaster[channel].count)
|
||||
{
|
||||
// pclog("DMA on channel %i - block over\n", channel);
|
||||
if (piix_busmaster[channel].eot) /*End of transfer?*/
|
||||
{
|
||||
// pclog("DMA on channel %i - transfer over\n", channel);
|
||||
piix_busmaster[channel].status &= ~1;
|
||||
}
|
||||
else
|
||||
piix_bus_master_next_addr(channel);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void piix_bus_master_set_irq(int channel)
|
||||
{
|
||||
piix_busmaster[channel].status |= 4;
|
||||
}
|
||||
|
||||
void piix_init(int card, int pci_a, int pci_b, int pci_c, int pci_d)
|
||||
{
|
||||
|
|
@ -379,8 +178,8 @@ void piix_init(int card, int pci_a, int pci_b, int pci_c, int pci_d)
|
|||
card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
|
||||
card_piix_ide[0x40] = card_piix_ide[0x41] = 0x00;
|
||||
card_piix_ide[0x42] = card_piix_ide[0x43] = 0x00;
|
||||
|
||||
ide_set_bus_master(piix_bus_master_data_read, piix_bus_master_data_write, piix_bus_master_set_irq);
|
||||
|
||||
sff_bus_master_init(piix_busmaster);
|
||||
|
||||
pci_set_card_routing(pci_a, PCI_INTA);
|
||||
pci_set_card_routing(pci_b, PCI_INTB);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
#include <string.h>
|
||||
|
||||
#include "ibm.h"
|
||||
#include "ide.h"
|
||||
#include "ide_sff8038i.h"
|
||||
#include "io.h"
|
||||
#include "mem.h"
|
||||
#include "pci.h"
|
||||
|
|
@ -16,6 +18,8 @@ static struct
|
|||
uint8_t power_regs[256];
|
||||
|
||||
uint8_t sysctrl;
|
||||
|
||||
sff_busmaster_t busmaster[2];
|
||||
} vt82c586b;
|
||||
|
||||
static uint8_t vt82c586b_read(int func, int addr, void *priv)
|
||||
|
|
@ -101,7 +105,7 @@ static void vt82c586b_pci_isa_bridge_write(int addr, uint8_t val)
|
|||
static void vt82c586b_ide_write(int addr, uint8_t val)
|
||||
{
|
||||
/*Read-only addresses*/
|
||||
if ((addr < 6) || (addr == 8)
|
||||
if ((addr < 4) || (addr == 5) || (addr == 8)
|
||||
|| (addr >= 0xa && addr < 0x0d)
|
||||
|| (addr >= 0x0e && addr < 0x20)
|
||||
|| (addr >= 0x22 && addr < 0x3c)
|
||||
|
|
@ -114,7 +118,7 @@ static void vt82c586b_ide_write(int addr, uint8_t val)
|
|||
switch (addr)
|
||||
{
|
||||
case 4:
|
||||
vt82c586b.ide_regs[4] = (val & 8) | 7;
|
||||
vt82c586b.ide_regs[4] = val & 0x85;
|
||||
break;
|
||||
case 6:
|
||||
vt82c586b.ide_regs[6] &= ~(val & 0xb0);
|
||||
|
|
@ -132,11 +136,32 @@ static void vt82c586b_ide_write(int addr, uint8_t val)
|
|||
vt82c586b.ide_regs[addr] = val;
|
||||
break;
|
||||
}
|
||||
|
||||
if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
|
||||
{
|
||||
uint16_t base = (vt82c586b.ide_regs[0x20] & 0xf0) | (vt82c586b.ide_regs[0x21] << 8);
|
||||
io_removehandler(0, 0x10000, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, vt82c586b.busmaster);
|
||||
if (vt82c586b.ide_regs[0x04] & 1)
|
||||
io_sethandler(base, 0x10, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, vt82c586b.busmaster);
|
||||
}
|
||||
if (addr == 4 || addr == 0x40)
|
||||
{
|
||||
ide_pri_disable();
|
||||
ide_sec_disable();
|
||||
if (vt82c586b.ide_regs[0x04] & 1)
|
||||
{
|
||||
if (vt82c586b.ide_regs[0x40] & 0x02)
|
||||
ide_pri_enable();
|
||||
if (vt82c586b.ide_regs[0x40] & 0x01)
|
||||
ide_sec_enable();
|
||||
}
|
||||
}
|
||||
}
|
||||
static void vt82c586b_usb_write(int addr, uint8_t val)
|
||||
{
|
||||
/*Read-only addresses*/
|
||||
if ((addr < 7) || (addr >= 8 && addr < 0xd)
|
||||
if ((addr < 4) || (addr == 5) || (addr == 6)
|
||||
|| (addr >= 8 && addr < 0xd)
|
||||
|| (addr >= 0xe && addr < 0x20)
|
||||
|| (addr >= 0x22 && addr < 0x3c)
|
||||
|| (addr >= 0x3e && addr < 0x40)
|
||||
|
|
@ -147,6 +172,9 @@ static void vt82c586b_usb_write(int addr, uint8_t val)
|
|||
|
||||
switch (addr)
|
||||
{
|
||||
case 4:
|
||||
vt82c586b.usb_regs[4] = val & 0x97;
|
||||
break;
|
||||
case 7:
|
||||
vt82c586b.usb_regs[7] = val & 0x7f;
|
||||
break;
|
||||
|
|
@ -307,4 +335,9 @@ void vt82c586b_init(int card, int pci_a, int pci_b, int pci_c, int pci_d)
|
|||
pci_set_card_routing(pci_c, PCI_INTC);
|
||||
if (pci_d)
|
||||
pci_set_card_routing(pci_d, PCI_INTD);
|
||||
|
||||
sff_bus_master_init(vt82c586b.busmaster);
|
||||
|
||||
ide_pri_disable();
|
||||
ide_sec_disable();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue