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Commit graph pcem/src/cpu.c
Author SHA1 Message Date
SarahW
fda3832e3a Add Gigabyte GA-686BX emulation. 
As part of this, add i440BX chipset, PIIX4, and i28F002BC Flash.
 2020-11-14 19:33:03 +00:00
SarahW
3c4fa0511e Add Pentium II Overdrive emulation. 2020-11-14 19:33:02 +00:00
SarahW
21dbd868e1 Add initial P6 timing model. Currently only basic decoder limits 
(4-1-1 rule and 16-byte limit) have been implemented.
 2020-11-14 19:33:02 +00:00
SarahW
cf33ab6c39 Add initial implementation of Intel VS440FX motherboard. 
As part of this, add dummy Pentium Pro emulation, as well as Intel 440FX
chipset, PC87307 SuperIO and Intel 28FB200BX-T Flash.
 2020-11-14 19:33:01 +00:00
SarahW
e3fd8698df Remove faulty cyrix special register read access 
Patch from davefiddes. Original commit message :

GCC 10.1 reports this line as being logically always false so will never run.
On inspection it may be that this was intended to be:

   if ((cyrix_addr & 0xf0) == 0xc0) return 0xff;

According to the IBM 6X86MX Microprocessor Databook
(http://datasheets.chipdb.org/IBM/x86/6x86MX/mx_full.pdf) this would correspond
to the Address Region 0 - 3 registers but omit Address Region 4 - 7 registers
which doesn't seem to make a lot of sense.

Delete the code as the default response from the function is to return 0xff
and this is what its behviour up until now has been.
 2020-07-14 19:30:19 +01:00
SarahW
4875f24b53 Added initial attempt at instruction timings for 8087/287/387. 
Also added 287XL using 387 timings.
 2020-01-24 20:33:35 +00:00
SarahW
0e8926936d Added FPU support for pre-486 CPUs. 
This commit does not include timings for 8087, 80287 or 80387 FPUs, these will
be added later. It also does not restrict the use of 486 and later FPU
instructions.
 2020-01-22 20:53:13 +00:00
SarahW
84622584e2 Move CPU tables to separate file. 2019-02-08 21:34:02 +00:00
SarahW
ce4436054d Replace cpu_has* flags with single cpu_features variable and cpu_has_feature() getter. 2019-02-08 21:22:53 +00:00
SarahW
03b5a44aca More CPU sanitisation. 2019-02-08 21:17:56 +00:00
SarahW
dd68b19f0a Second CPU sanitising pass. 2019-02-07 21:53:44 +00:00
SarahW
cfd4ac3a4f Added initial timing model for K6 CPUs. 2018-12-09 22:17:11 +00:00
SarahW
fd10fdd372 Fix ATCLK timings on Winchip 2 CPUs. 2018-12-06 20:02:51 +00:00
SarahW
a9541dadea Added preliminary emulation of AMD K6 CPUs. 2018-12-06 20:02:35 +00:00
SarahW
7ec6f1e4ce Added Winchip 2 timing model. 2018-12-05 20:54:56 +00:00
SarahW
9b8b6c2c70 Add Winchip 2A CPUs. 2018-12-04 21:35:51 +00:00
SarahW
da2d819ed4 Added WinChip 2 emulation, along with (currently non-recompiled) 3DNow! instruction emulation. 2018-12-03 21:59:41 +00:00
SarahW
d489dddeee Tweak 486 prefetch timing when cache disabled, to account for burst accesses. Improves CPU speed detection on SiS496/497. 2018-04-20 10:58:12 +01:00
SarahW
031f64c1a3 Invalid CPUID instructions should return zero in EBX/ECX/EDX. Fixes CPU type test and subsequent invalid 3DNow! instruction execution in NFL Blitz 2000. 2018-04-08 17:16:04 +01:00
SarahW
5762431260 Don't add ROM waitstates on slow CPUs (<= 8 MHz). Fixes IBM AT. 2018-03-12 20:52:07 +00:00
SarahW
b530bdafea Cleaned up turbo handling. 2018-03-11 16:43:32 +00:00
SarahW
8546ce14f0 Added waitstates on instruction fetch from ROM. 2018-03-11 11:03:20 +00:00
SarahW
919f2dd45d Implemented CMPXCHG8B on Winchip. Patch from nerd73. 2018-03-03 21:32:56 +00:00
SarahW
55dbe592ad Fixed bus type detection on Cirrus Logic. 2018-02-22 21:04:32 +00:00
SarahW
b9f196d641 ISA timing now based on integer ATCLK instead of fixed point division. 2018-01-31 20:01:18 +00:00
SarahW
04cbcfb587 Added Pentium 133 to Advanced/EV CPU list. 2017-12-10 17:34:36 +00:00
SarahW
a3ae6a6eed Added IBM XT Model 286 emulation. 2017-10-11 22:09:26 +01:00
SarahW
a96e87527e Reorganised REP instructions. 2017-07-20 21:06:21 +01:00
SarahW
dc511447df Added Page Size Extension (4MB pages) to Pentium CPUs. 2017-07-16 21:24:09 +01:00
SarahW
1f33b52451 Added VME emulation to Intel DX4, Pentium and Pentium MMX. 
Temporarily disabled recompilation of CLI and STI.
 2017-06-30 20:42:19 +01:00
SarahW
45bd0db00c Corrected EuroPC CPU options. Patch from ecksemmess. 2017-06-04 17:47:13 +01:00
SarahW
3b4392bcf8 Implemented data misalignment penalties on 486 and later CPUs. 2017-06-04 16:41:33 +01:00
SarahW
c2a6ce2bac Added IBM PS/2 Model 30-286 emulation. Patch from dns2k. 2017-02-22 20:18:41 +00:00
SarahW
45423fe499 Remove 386DX CPUs from 386SX models (and vice-versa). 2017-02-18 18:14:53 +00:00
SarahW
5457531753 Only enable waitstate selection on CPUs where it has any practical effect (286/386). 2016-12-13 20:44:43 +00:00
SarahW
a4f3b2013e Added AMI 386DX and MR 386DX models (both based on OPTi 495 chipset). AMI 386DX supports external cache, useful for with prefetch emulation. 
Also commit a few fixes required :
- Set EDX correctly on soft reset
- LOCK NOP is now treated as an illegal instruction
- Tweaks to FDC sense interrupt handling following FDC reset
 2016-11-27 21:53:13 +00:00
SarahW
1b73963997 Added prefetch timing approximation for 286/386 CPUs, with configurable memory timing. 2016-11-25 21:32:02 +00:00
SarahW
396992f102 More accurate PCI timing, mainly for Voodoo. 2016-10-22 16:01:49 +01:00
SarahW
7980438e1f Reworking of joystick support : 
- Joystick type now selectable
- Added emulation of standard joysticks with up to 8 buttons
- Added emulation of Microsoft Sidewinder pads
- Host->emulated joystick button & axis mapping now configurable (only on Windows atm)
- Gameport registers now take 1us to access - helps Sidewinder drivers
 2016-06-21 22:00:31 +01:00
SarahW
512c8e5d44 Winchip FPU timings now more accurate. 2016-05-14 19:36:40 +01:00
SarahW
d83249648f Limited PS/1 to 10 MHz. 2016-05-01 12:24:08 +01:00
SarahW
e236fb6d16 Added missing FCMOV instruction for 6x86MX. 2016-04-28 19:34:46 +01:00
SarahW
153c22e442 Cyrix 6x86 emulation. Based on patch from leilei. 
Moved MOV TRx, reg to correct opcode - required by Award 430VX BIOS with 6x86.
 2016-04-27 22:23:49 +01:00
TomW
94f33aa873 More accurate timing for INT, IRET, CALL far, RET far and JMP far. 2016-02-06 18:08:10 +00:00
TomW
7b5766598e Fixed typo in cpu.c when initialising FPU dynarec opcode tables for 486SX CPUs. 2016-01-15 20:10:44 +00:00
TomW
928e76bccc Added socket 4/5 Pentium OverDrive CPUs. 
Added seperate array of socket 5 Pentium CPUs.
Patch from Battler.
 2016-01-05 19:59:41 +00:00
TomW
2ca86ba028 Added support for Tandy 1000 HX and SL/2. As part of this commit : 
- FDC now selects drive number from DOR (0x3f2)
- FDC now fails seeks on drives > 1
- XT systems no longer have BIOS mapping at E0000-EFFFF
- SN76489 now distinguishes between SN76496 (PCjr and early Tandy 1000), NCR8496 (later Tandy 1000 - different noise handling) and PSSJ
- Removed redundant limits on memory configuration - allows selection of 768k for Tandy 1000 SL/2
 2015-12-03 21:48:10 +00:00
TomW
79202cc5c0 Changed timer base frequency on XT models to 14.318MHz - PIT, CGA and 4.77MHz CPU should now stay in perfect sync. 2015-11-25 21:50:38 +00:00
TomW
22f20e3595 Fixed typo that broke 8088 timing. 2015-11-13 20:51:10 +00:00
TomW
1e45ba5f34 Removed a bunch of old #defines. Cleaned up some dead code. 2015-09-16 19:08:50 +01:00