SarahW
9bba93e0be
Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG.
2018-08-08 22:14:22 +01:00
SarahW
648aa0e3e8
Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
2018-07-17 22:08:25 +01:00
SarahW
fc27be592c
Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
2018-07-08 16:36:11 +01:00
SarahW
03fe25d818
First stage of dynamic recompiler rewrite.
...
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
2018-06-17 20:26:15 +01:00
SarahW
0985952317
Added code generation for RMW versions of ADD/SUB/OR/XOR/AND
2016-11-13 14:30:39 +00:00
SarahW
c664682758
Move some more variables into cpu_state structure. Minor speedup (~2%).
2016-08-17 21:28:16 +01:00
SarahW
c81a91fd72
Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).
2016-04-20 21:39:41 +01:00
TomW
f75a24f539
Rewrote recompiler implementation of NEG.
2015-08-08 16:05:05 +01:00
TomW
0bf08d9e74
x86-64 recompiler now at parity with x86-32
2015-08-04 18:36:27 +01:00
TomW
9061c5d2fc
Added code generation for :
...
- TEST immediate
- register versions of NOT and NEG
- fixed shift versions of SHL, SHR and SAR
- MOVZX and MOVSX
- LEA
- CMP with memory destination
- JL, JNL, JLE, JNLE, JBE, JNBE
2015-05-30 17:08:54 +01:00
TomW
c7b6fde58c
Added code generation for memory source versions of AND, OR, XOR and TEST (that was intended for rev 199).
2015-02-09 21:21:48 +00:00
TomW
ea5e96569d
Lazy flags code now handles carry flag.
2015-02-02 19:54:01 +00:00
TomW
630592125c
Added code generation for immediate->register and register versions of MOV, XCHG, ADD, SUB, AND, OR, XOR, TEST, CMP, INC and DEC.
2015-01-16 21:22:14 +00:00
