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Added code generation for RMW versions of ADD/SUB/OR/XOR/AND

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This commit is contained in:
SarahW 2016-11-13 14:30:39 +00:00
commit 0985952317
8 changed files with 2126 additions and 169 deletions
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8
src/codegen.h
View file

@ -300,7 +300,7 @@ extern int block_pos;
static inline void addbyte(uint8_t val)
{
codeblock[block_current].data[block_pos++] = val;
if (block_pos >= 1760)
if (block_pos >= BLOCK_MAX)
{
CPU_BLOCK_END();
}
@ -310,7 +310,7 @@ static inline void addword(uint16_t val)
{
*(uint16_t *)&codeblock[block_current].data[block_pos] = val;
block_pos += 2;
if (block_pos >= 1720)
if (block_pos >= BLOCK_MAX)
{
CPU_BLOCK_END();
}
@ -320,7 +320,7 @@ static inline void addlong(uint32_t val)
{
*(uint32_t *)&codeblock[block_current].data[block_pos] = val;
block_pos += 4;
if (block_pos >= 1720)
if (block_pos >= BLOCK_MAX)
{
CPU_BLOCK_END();
}
@ -330,7 +330,7 @@ static inline void addquad(uint64_t val)
{
*(uint64_t *)&codeblock[block_current].data[block_pos] = val;
block_pos += 8;
if (block_pos >= 1720)
if (block_pos >= BLOCK_MAX)
{
CPU_BLOCK_END();
}

296
src/codegen_ops_arith.h
View file

@ -79,19 +79,38 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t rop ## name ## _b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_B(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_B(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_B_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
@ -100,19 +119,38 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t rop ## name ## _w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_W(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_W(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_W_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
@ -121,19 +159,38 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t rop ## name ## _l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_L(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_L(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_L_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
codegen_flags_changed = 1; \
@ -541,12 +598,33 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
if ((fetchdat & 0x30) == 0x10 || (fetchdat & 0xc0) != 0xc0)
if ((fetchdat & 0x30) == 0x10)
return 0;
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38)
{
MEM_LOAD_ADDR_EA_B(target_seg);
host_reg = 0;
}
else
{
SAVE_EA();
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
}
else
{
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
switch (fetchdat & 0x38)
{
@ -584,7 +662,17 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_B_RELEASE(host_reg);
{
if ((fetchdat & 0xc0) != 0xc0)
{
LOAD_EA();
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, host_reg);
}
else
{
STORE_REG_B_RELEASE(host_reg);
}
}
else
RELEASE_REG(host_reg);
@ -596,12 +684,33 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
if ((fetchdat & 0x30) == 0x10 || (fetchdat & 0xc0) != 0xc0)
x86seg *target_seg;
if ((fetchdat & 0x30) == 0x10)
return 0;
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38)
{
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
else
{
SAVE_EA();
MEM_CHECK_WRITE_W(target_seg);
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
imm = fastreadw(cs + op_pc + 1);
}
else
{
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
}
switch (fetchdat & 0x38)
{
@ -639,7 +748,17 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_W_RELEASE(host_reg);
{
if ((fetchdat & 0xc0) != 0xc0)
{
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
}
else
{
STORE_REG_W_RELEASE(host_reg);
}
}
else
RELEASE_REG(host_reg);
@ -650,13 +769,32 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
if ((fetchdat & 0x30) == 0x10 || (fetchdat & 0xc0) != 0xc0)
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38)
{
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
}
else
{
SAVE_EA();
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
}
else
{
host_reg = LOAD_REG_L(fetchdat & 7);
}
imm = fastreadl(cs + op_pc + 1);
host_reg = LOAD_REG_L(fetchdat & 7);
switch (fetchdat & 0x38)
{
@ -694,7 +832,17 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_L_RELEASE(host_reg);
{
if ((fetchdat & 0xc0) != 0xc0)
{
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
}
else
{
STORE_REG_L_RELEASE(host_reg);
}
}
else
RELEASE_REG(host_reg);
@ -706,12 +854,34 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
if ((fetchdat & 0x30) == 0x10 || (fetchdat & 0xc0) != 0xc0)
x86seg *target_seg;
if ((fetchdat & 0x30) == 0x10)
return 0;
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38)
{
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
else
{
SAVE_EA();
MEM_CHECK_WRITE_W(target_seg);
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
}
else
{
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
if (imm & 0x80)
imm |= 0xff80;
@ -751,7 +921,17 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_W_RELEASE(host_reg);
{
if ((fetchdat & 0xc0) != 0xc0)
{
LOAD_EA();
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, host_reg);
}
else
{
STORE_REG_W_RELEASE(host_reg);
}
}
else
RELEASE_REG(host_reg);
@ -762,12 +942,34 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
if ((fetchdat & 0x30) == 0x10 || (fetchdat & 0xc0) != 0xc0)
if ((fetchdat & 0x30) == 0x10)
return 0;
host_reg = LOAD_REG_L(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0x38) == 0x38)
{
MEM_LOAD_ADDR_EA_L(target_seg);
host_reg = 0;
}
else
{
SAVE_EA();
MEM_CHECK_WRITE_L(target_seg);
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
imm = fastreadb(cs + op_pc + 1);
}
else
{
host_reg = LOAD_REG_L(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
if (imm & 0x80)
imm |= 0xffffff80;
@ -807,10 +1009,20 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
STORE_REG_L_RELEASE(host_reg);
{
if ((fetchdat & 0xc0) != 0xc0)
{
LOAD_EA();
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, host_reg);
}
else
{
STORE_REG_L_RELEASE(host_reg);
}
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}

93
src/codegen_ops_logic.h
View file

@ -2,17 +2,36 @@
static uint32_t rop ## name ## _b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_B(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_B(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_B_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
@ -20,17 +39,36 @@
static uint32_t rop ## name ## _w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_W(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_W(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_W_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_W_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \
@ -38,17 +76,36 @@
static uint32_t rop ## name ## _l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
int src_reg, dst_reg; \
x86seg *target_seg; \
\
if ((fetchdat & 0xc0) != 0xc0) \
return 0; \
\
dst_reg = LOAD_REG_L(fetchdat & 7); \
if ((fetchdat & 0xc0) == 0xc0) \
{ \
dst_reg = LOAD_REG_L(fetchdat & 7); \
} \
else \
{ \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
SAVE_EA(); \
MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_L_RELEASE(dst_reg); \
else \
{ \
LOAD_EA(); \
MEM_STORE_ADDR_EA_L_NO_ABRT(target_seg, dst_reg); \
} \
} \
else \
RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
\
return op_pc + 1; \

1121
src/codegen_ops_x86-64.h
View file

File diff suppressed because it is too large Load diff

122
src/codegen_ops_x86.h
View file

@ -671,6 +671,18 @@ static void MEM_LOAD_ADDR_EA_B(x86seg *seg)
host_reg_mapping[0] = 8;
}
static int MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
{
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_load_addr_ea_b_no_abrt*/
addlong(mem_load_addr_ea_b_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static void MEM_LOAD_ADDR_EA_W(x86seg *seg)
{
addbyte(0x8b); /*MOVL EDX, seg->base*/
@ -681,6 +693,18 @@ static void MEM_LOAD_ADDR_EA_W(x86seg *seg)
host_reg_mapping[0] = 8;
}
static int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
{
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_load_addr_ea_w_no_abrt*/
addlong(mem_load_addr_ea_w_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static void MEM_LOAD_ADDR_EA_L(x86seg *seg)
{
addbyte(0x8b); /*MOVL EDX, seg->base*/
@ -692,6 +716,18 @@ static void MEM_LOAD_ADDR_EA_L(x86seg *seg)
host_reg_mapping[0] = 8;
}
static int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
{
addbyte(0x8b); /*MOVL EDX, seg->base*/
addbyte(0x05 | (REG_EDX << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_load_addr_ea_l_no_abrt*/
addlong(mem_load_addr_ea_l_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static void MEM_LOAD_ADDR_EA_Q(x86seg *seg)
{
@ -736,6 +772,19 @@ static void MEM_STORE_ADDR_EA_B(x86seg *seg, int host_reg)
addbyte(0xe8); /*CALL mem_store_addr_ea_b*/
addlong(mem_store_addr_ea_b - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_B_NO_ABRT(x86seg *seg, int host_reg)
{
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
if (host_reg != REG_ECX)
{
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_b_no_abrt*/
addlong(mem_store_addr_ea_b_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
{
addbyte(0x8b); /*MOVL ESI, seg->base*/
@ -749,6 +798,19 @@ static void MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
addbyte(0xe8); /*CALL mem_store_addr_ea_w*/
addlong(mem_store_addr_ea_w - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_W_NO_ABRT(x86seg *seg, int host_reg)
{
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
if (host_reg != REG_ECX)
{
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_w_no_abrt*/
addlong(mem_store_addr_ea_w_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
{
addbyte(0x8b); /*MOVL ESI, seg->base*/
@ -762,6 +824,19 @@ static void MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
addbyte(0xe8); /*CALL mem_store_addr_ea_l*/
addlong(mem_store_addr_ea_l - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_L_NO_ABRT(x86seg *seg, int host_reg)
{
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
if (host_reg != REG_ECX)
{
addbyte(0x89); /*MOV ECX, host_reg*/
addbyte(0xc0 | REG_ECX | (host_reg << 3));
}
addbyte(0xe8); /*CALL mem_store_addr_ea_l_no_abrt*/
addlong(mem_store_addr_ea_l_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
}
static void MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
{
if (host_reg != REG_EBX)
@ -3541,3 +3616,50 @@ static void MMX_PSLLQ_imm(int dst_reg, int amount)
addbyte(0xc0 | dst_reg | 0x30);
addbyte(amount);
}
static void SAVE_EA()
{
addbyte(0x89); /*MOV [ESP+12], EAX*/
addbyte(0x44);
addbyte(0x24);
addbyte(12);
}
static void LOAD_EA()
{
addbyte(0x8b); /*MOV EAX, [ESP+12]*/
addbyte(0x44);
addbyte(0x24);
addbyte(12);
}
static void MEM_CHECK_WRITE(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_check_write*/
addlong(mem_check_write - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}
static void MEM_CHECK_WRITE_W(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_check_write_w*/
addlong(mem_check_write_w - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}
static void MEM_CHECK_WRITE_L(x86seg *seg)
{
CHECK_SEG_WRITE(seg);
addbyte(0x8b); /*MOVL ESI, seg->base*/
addbyte(0x05 | (REG_ESI << 3));
addlong((uint32_t)&seg->base);
addbyte(0xe8); /*CALL mem_check_write_l*/
addlong(mem_check_write_l - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
LOAD_EA();
}

2
src/codegen_x86-64.h
View file

@ -10,6 +10,8 @@
#define BLOCK_EXIT_OFFSET 0x7e0
#define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 20)
#define BLOCK_MAX 1650
enum
{
OP_RET = 0xc3

641
src/codegen_x86.c
View file

@ -68,6 +68,15 @@ uint32_t mem_store_addr_ea_b;
uint32_t mem_store_addr_ea_w;
uint32_t mem_store_addr_ea_l;
uint32_t mem_store_addr_ea_q;
uint32_t mem_load_addr_ea_b_no_abrt;
uint32_t mem_store_addr_ea_b_no_abrt;
uint32_t mem_load_addr_ea_w_no_abrt;
uint32_t mem_store_addr_ea_w_no_abrt;
uint32_t mem_load_addr_ea_l_no_abrt;
uint32_t mem_store_addr_ea_l_no_abrt;
uint32_t mem_check_write;
uint32_t mem_check_write_w;
uint32_t mem_check_write_l;
static uint32_t gen_MEM_LOAD_ADDR_EA_B()
{
@ -505,6 +514,604 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
return addr;
}
static char gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_B_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x89); /*MOV EDI, EDX*/
addbyte(0xd7);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t)readlookup2);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4+1);
addbyte(0x0f); /*MOVZX ECX, B[EDX+EDI]*/
addbyte(0xb6);
addbyte(0x0c);
addbyte(0x3a);
addbyte(0xc3); /*RET*/
addbyte(0x50); /*slowpath: PUSH EAX*/
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmembl*/
addlong((uint32_t)readmemb386l - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX ECX, AL*/
addbyte(0xb6);
addbyte(0xc8);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static char gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_W_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x8d); /*LEA EDI, 1[EDX]*/
addbyte(0x7a);
addbyte(0x01);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 0xfff*/
addbyte(0xc7);
addlong(0xfff);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t)readlookup2);
addbyte(0x74); /*JE slowpath*/
addbyte(3+2+5+1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(5+1);
addbyte(0x0f); /*MOVZX EEX, -1[EDX+EDI]W*/
addbyte(0xb7);
addbyte(0x4c);
addbyte(0x3a);
addbyte(-1);
addbyte(0xc3); /*RET*/
addbyte(0x50); /*slowpath: PUSH EAX*/
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemwl*/
addlong((uint32_t)readmemwl - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX ECX, AX*/
addbyte(0xb7);
addbyte(0xc8);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static char gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_L_NO_ABRT aborted\n";
static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
addbyte(0xc2);
addbyte(0x8d); /*LEA EDI, 3[EDX]*/
addbyte(0x7a);
addbyte(0x03);
addbyte(0xc1); /*SHR EDX, 12*/
addbyte(0xea);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 0xffc*/
addbyte(0xc7);
addlong(0xffc);
addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t)readlookup2);
addbyte(0x74); /*JE slowpath*/
addbyte(3+2+4+1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4+1);
addbyte(0x8b); /*MOV ECX, -3[EDX+EDI]*/
addbyte(0x4c);
addbyte(0x3a);
addbyte(-3);
addbyte(0xc3); /*RET*/
addbyte(0x50); /*slowpath: PUSH EAX*/
addbyte(0x56); /*PUSH ESI*/
addbyte(0xe8); /*CALL readmemll*/
addlong((uint32_t)readmemll - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x89); /*MOV ECX, EAX*/
addbyte(0xc1);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0x83); /*SUBL 4,%esp*/
addbyte(0xEC);
addbyte(4);
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x89); /*MOV EDI, ESI*/
addbyte(0xc0 | (REG_ESI << 3) | REG_EDI);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t)writelookup2);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(3+1);
addbyte(0x88); /*MOV [EDI+ESI],CL*/
addbyte(0x04 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x50); /*PUSH EAX*/
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememb386l*/
addlong((uint32_t)writememb386l - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 12*/
addbyte(0xc4);
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x8d); /*LEA EDI, 1[ESI]*/
addbyte(0x7e);
addbyte(0x01);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 0xfff*/
addbyte(0xc7);
addlong(0xfff);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t)writelookup2);
addbyte(0x74); /*JE slowpath*/
addbyte(3+2+5+1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(5+1);
addbyte(0x66); /*MOV -1[EDI+ESI],CX*/
addbyte(0x89);
addbyte(0x44 | (REG_CX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(-1);
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x50); /*PUSH EAX*/
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememwl*/
addlong((uint32_t)writememwl - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 12*/
addbyte(0xc4);
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_ABRT aborted\n";
static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
addbyte(0x01); /*ADDL ESI, EAX*/
addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
addbyte(0x8d); /*LEA EDI, 3[ESI]*/
addbyte(0x7e);
addbyte(0x03);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xe8 | REG_ESI);
addbyte(12);
addbyte(0xf7); /*TEST EDI, 0xffc*/
addbyte(0xc7);
addlong(0xffc);
addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
addbyte(0x04 | (REG_ESI << 3));
addbyte(0x85 | (REG_ESI << 3));
addlong((uint32_t)writelookup2);
addbyte(0x74); /*JE slowpath*/
addbyte(3+2+4+1);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xf8 | REG_ESI);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(4+1);
addbyte(0x89); /*MOV -3[EDI+ESI],ECX*/
addbyte(0x44 | (REG_ECX << 3));
addbyte(REG_EDI | (REG_ESI << 3));
addbyte(-3);
addbyte(0xc3); /*RET*/
addbyte(0x51); /*slowpath: PUSH ECX*/
addbyte(0x50); /*PUSH EAX*/
addbyte(0x53); /*PUSH EBX*/
addbyte(0xe8); /*CALL writememll*/
addlong((uint32_t)writememll - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 12*/
addbyte(0xc4);
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong(gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
return addr;
}
static uint32_t gen_MEM_CHECK_WRITE()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t)&cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t)writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
/*static void checkdebug(uint32_t a)
{
pclog("checkdebug %08x\n", a);
}*/
static uint32_t gen_MEM_CHECK_WRITE_W()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t)&cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x8d); /*LEA ESI, 1[EDI]*/
addbyte(0x77);
addbyte(0x01);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x89); /*MOV EAX, EDI*/
addbyte(0xf8);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t)writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[ESI*4],-1*/
addbyte(0x3c);
addbyte(0xb5);
addlong((uint32_t)writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
/*slowpath_lp:*/
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x83); /*ADD EDI, 1*/
addbyte(0xc7);
addbyte(1);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
/*If bits 0-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST $fff, EDI*/
addbyte(0xc7);
addlong(0xfff);
addbyte(0x74); /*JE slowpath_lp*/
addbyte(-33);
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t gen_MEM_CHECK_WRITE_L()
{
uint32_t addr = &codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
addbyte(0x83); /*CMP cr0, 0*/
addbyte(0x3d);
addlong((uint32_t)&cr0);
addbyte(0);
addbyte(0x78); /*JS +*/
addbyte(1);
addbyte(0xc3); /*RET*/
addbyte(0x83); /*CMP ESI, -1*/
addbyte(0xfe);
addbyte(-1);
addbyte(0x8d); /*LEA ESI, 3[EDI]*/
addbyte(0x77);
addbyte(0x03);
addbyte(0x74); /*JE slowpath*/
addbyte(11);
addbyte(0x89); /*MOV EAX, EDI*/
addbyte(0xf8);
addbyte(0xc1); /*SHR EDI, 12*/
addbyte(0xef);
addbyte(12);
addbyte(0xc1); /*SHR ESI, 12*/
addbyte(0xee);
addbyte(12);
addbyte(0x83); /*CMP writelookup2[EDI*4],-1*/
addbyte(0x3c);
addbyte(0xbd);
addlong((uint32_t)writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(11);
addbyte(0x83); /*CMP writelookup2[ESI*4],-1*/
addbyte(0x3c);
addbyte(0xb5);
addlong((uint32_t)writelookup2);
addbyte(-1);
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
/*slowpath_lp:*/
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
addbyte(4);
addbyte(0x83); /*ADD EDI, 3*/
addbyte(0xc7);
addbyte(3);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
/*If bits 2-11 of the address are now 0 then this crosses a page, so loop back*/
addbyte(0xf7); /*TEST EDI, FFC*/
addbyte(0xc7);
addlong(0xffc);
addbyte(0x74); /*JE slowpath_lp*/
addbyte(-33);
addbyte(0xc3); /*RET*/
return addr;
}
void codegen_init()
{
int c;
@ -547,22 +1154,40 @@ void codegen_init()
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
block_pos = 128;
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l = gen_MEM_LOAD_ADDR_EA_L();
block_pos = 256;
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w = gen_MEM_LOAD_ADDR_EA_W();
block_pos = 384;
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b = gen_MEM_LOAD_ADDR_EA_B();
block_pos = 512;
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_q = gen_MEM_LOAD_ADDR_EA_Q();
block_pos = 640;
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l = gen_MEM_STORE_ADDR_EA_L();
block_pos = 768;
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w = gen_MEM_STORE_ADDR_EA_W();
block_pos = 896;
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b = gen_MEM_STORE_ADDR_EA_B();
block_pos = 1024;
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_q = gen_MEM_STORE_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b_no_abrt = gen_MEM_LOAD_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b_no_abrt = gen_MEM_STORE_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w_no_abrt = gen_MEM_LOAD_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w_no_abrt = gen_MEM_STORE_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l_no_abrt = gen_MEM_LOAD_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l_no_abrt = gen_MEM_STORE_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_check_write = gen_MEM_CHECK_WRITE();
block_pos = (block_pos + 15) & ~15;
mem_check_write_w = gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15;
mem_check_write_l = gen_MEM_CHECK_WRITE_L();
asm(
"fstcw %0\n"

12
src/codegen_x86.h
View file

@ -10,6 +10,8 @@
#define BLOCK_EXIT_OFFSET 0x7f0
#define BLOCK_GPF_OFFSET (BLOCK_EXIT_OFFSET - 20)
#define BLOCK_MAX 1720
enum
{
OP_RET = 0xc3
@ -28,3 +30,13 @@ extern uint32_t mem_store_addr_ea_b;
extern uint32_t mem_store_addr_ea_w;
extern uint32_t mem_store_addr_ea_l;
extern uint32_t mem_store_addr_ea_q;
extern uint32_t mem_load_addr_ea_b_no_abrt;
extern uint32_t mem_store_addr_ea_b_no_abrt;
extern uint32_t mem_load_addr_ea_w_no_abrt;
extern uint32_t mem_store_addr_ea_w_no_abrt;
extern uint32_t mem_load_addr_ea_l_no_abrt;
extern uint32_t mem_store_addr_ea_l_no_abrt;
extern uint32_t mem_check_write;
extern uint32_t mem_check_write_w;
extern uint32_t mem_check_write_l;