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1,229 commits 3 branches 0 tags 5.5 MiB
Commit graph pcem/src
Author SHA1 Message Date
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
dbb01ef9e2 Cleaned up x87 tag register handling. 2018-10-01 21:02:40 +01:00
SarahW
e9ff110021 Fixed flags on register->register ADD/SUB opcode 00/01/28/29. Fixes rendering in Need For Speed II. 2018-09-30 17:30:28 +01:00
SarahW
94fe85b17e Fixed video clock on Cirrus Logic cards. 2018-09-29 17:43:02 +01:00
SarahW
592b07be63 Added recompiled versions of JMP indirect, JMP far, RETF, LxS, XLAT and LEAVE. 2018-09-29 17:42:44 +01:00
SarahW
1aadfd436d Added recompiled versions of CBW, CDQ, CWD, CWDE and MOVSX. 2018-09-23 21:45:12 +01:00
SarahW
8a19e56340 Added recompiled versions of INC and DEC. 2018-09-12 20:16:27 +01:00
SarahW
3332897886 Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE. 2018-08-30 22:26:33 +01:00
SarahW
872a2da788 Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD. 2018-08-16 21:44:41 +01:00
SarahW
2783471daa Clamp SVGA display on/off timings to a minimum of 1 usec. Fixes hang on Windows XP boot with ViRGE/DX. 2018-08-08 22:15:21 +01:00
SarahW
4846616924 Handle REP prefixed instructions without a dedicated REP instruction handler properly in the recompiler. Fixes Windows XP setup. 2018-08-08 22:14:52 +01:00
SarahW
9bba93e0be Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG. 2018-08-08 22:14:22 +01:00
SarahW
57e5549f48 Remove final remnants of ARM literal pool, and expand work register set to 7 registers. 2018-08-05 16:24:48 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
4ada3382b4 Fix inconsistent size of ide_fn array. 2018-08-03 19:44:35 +01:00
SarahW
a9d46d95ec Use MOVW/MOVT to load immediates on ARM instead of a literal pool. 2018-08-02 22:09:57 +01:00
SarahW
42d62925c3 Fix compiler warnings on ARM builds. 2018-08-02 22:09:18 +01:00
SarahW
a7d006b637 Rewrote timer code. 
The new code is based on timestamps, rather than delays. This eliminates the
need to update every timer in timer_process(), which cost a non-trivial amount
of CPU time on low-end machines.

This involved changes to every user of the timer code, so this change almost
certainly introduces bugs.
 2018-08-02 22:06:10 +01:00
SarahW
ab359ca9c5 Removed rogue CPU_BLOCK_END() from ropMOV_r_b() 2018-07-27 22:25:03 +01:00
SarahW
e64271f5bb Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR. 2018-07-27 22:24:34 +01:00
SarahW
cf508b050f End block when register version hits a maximum count. 2018-07-25 20:18:03 +01:00
SarahW
5ca2533f3c Increase ARM64 work registers from 5 to 10. 2018-07-25 20:17:42 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
91143d3c68 Move CPU segment structures into cpu_state structure. 2018-07-22 12:56:03 +01:00
SarahW
4e7a13f452 Corrected effective address for POP 0x8f. Windows 95 now works on recompiler. 2018-07-18 22:19:09 +01:00
SarahW
0f0a1c3223 Perform NULL segment checks upfront in opcode handlers, rather than on every memory access. 
This removes the need to pass the segment to readmem*l()/writemem*l().
 2018-07-18 22:10:18 +01:00
SarahW
648aa0e3e8 Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-17 22:08:25 +01:00
SarahW
e4e0f76d5c De-duplicate ARM literal pools. 2018-07-08 16:36:26 +01:00
SarahW
fc27be592c Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-08 16:36:11 +01:00
SarahW
67804322b6 Add codegen_accumulate.c to Makefile.am. 2018-07-06 17:54:17 +01:00
SarahW
ced37ac545 Hacked in quick ARM64 UOP_AND_IMM handling of immediate 0xffff. 2018-07-06 17:53:58 +01:00
SarahW
d666c0aeb9 ARM64 UOP_ADD_IMM can now generate SUB instructions to better handle negative data. 2018-07-06 17:53:11 +01:00
SarahW
dc2afee957 ARM UOP_ADD_IMM can now generate SUB instructions to better handle negative data. 2018-07-06 17:52:33 +01:00
SarahW
774f4201ee Recompiler now handles instruction and cycle counting. 2018-07-06 17:51:22 +01:00
SarahW
93ec6b0692 Recompiler now handles FPU prefixes. 2018-07-06 17:50:32 +01:00
SarahW
94fea237b4 Implemented effective address compilation. 2018-06-28 22:06:42 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00
SarahW
03fe25d818 First stage of dynamic recompiler rewrite. 
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
 2018-06-17 20:26:15 +01:00
SarahW
e6dce0920b Disable SDL thread naming on Windows. Fixes running PCem through GDB. 2018-06-05 18:22:47 +01:00
SarahW
e44ca65ad6 Removed old bitrotted Win32 port. 2018-06-04 22:08:38 +01:00
SarahW
b62127f7a8 Move BIOS loading out of mem.c. 2018-06-04 22:03:45 +01:00
SarahW
8ac2157f87 Fixed AT systems broken by rev 1184. 2018-06-04 21:38:18 +01:00
SarahW
cbf4b9f813 Configurable MAC address. Patch from Tux. 2018-06-04 21:02:36 +01:00
SarahW
38e842d88d Load BASIC on Generic XT clone if present. Patch from Greatpsycho. 2018-06-04 20:20:05 +01:00
SarahW
82fcbd99de Allow 704kb on Generic XT clone when MDA/CGA/Hercules are in use. Patch from Greatpsycho. 2018-06-04 20:19:47 +01:00
SarahW
2955df2c5a Fixed strncpy() length when parsing command line. 2018-06-04 20:06:11 +01:00
Greg V
f002abe258 Add dummy cdrom ioctl module for other OSes 2018-05-18 02:51:33 +03:00
Greg V
d5b7a69ff6 Respect the WX_CONFIG_PATH variable 
The configure script takes a --with-wx-config argument, we should respect it.
It is very necessary for FreeBSD, which installs wx configs under more specific names such as 'wxgtk2u-3.0-config'.
 2018-05-18 02:48:43 +03:00
SarahW
429f49abd1 Update version number and readme for v14 release. 2018-04-20 14:14:10 +01:00
SarahW
8a1cef9851 Tweak DIV timing for Cyrix 486es. Improves Cyrix 486 CPU speed detection on SiS496/497. 2018-04-20 10:58:43 +01:00