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Commit graph pcem/src/codegen.h
Author SHA1 Message Date
SarahW
114cdd7a15 Add VIA Cyrix III CPUs. Note that this is currently limited to 500 MHz, 
as Windows 98 won't boot on anything any faster than this. This is most
likely a limitation of the current timer subsystem.
 2020-11-14 19:33:53 +00:00
SarahW
21dbd868e1 Add initial P6 timing model. Currently only basic decoder limits 
(4-1-1 rule and 16-byte limit) have been implemented.
 2020-11-14 19:33:02 +00:00
SarahW
83f2869123 Don't unroll a loop if x87 top of stack is different at the start and end of the loop. Fixes Battlezone. 2019-05-11 11:44:33 +01:00
SarahW
a0ab14f56f When unrolling a loop, set op_32, ea_seg and ssegs to the correct values at the start of the loop. Fixes mode setting on Bahamas 64 and most likely some other bugs. 2019-04-01 21:23:09 +01:00
SarahW
ab124776a0 Rework self modifying code handling. 
Code blocks now have a varying level of granularity in the page and dirty masks.
Most blocks have 64-byte granularity, but blocks that are repeatedly modified
drop to 1-byte granularity. This reduces the maximum size of the affected block
significantly, but reduces recompilation due to data located too close to code.

If the block is still marked as dirty, then it is recompiled without any
immediate instruction parameters being baked into the recompiled code, instead
being fetched from the RAM array as needed. This severely reduces recompilation
rates on some SMC-heavy games, eg Duke Nukem 3D, System Shock, Screamer etc,
giving a major speedup.
 2019-03-16 14:53:26 +00:00
SarahW
ec18c8a2fb Implement more intelligent out-of-memory algorithm. 2019-01-21 21:52:32 +00:00
SarahW
bf392ffd3a Maintain a list of free code blocks, and allocate new blocks from the list rather than evicting at random. 
Also maintain a list of memory pages with dirty code blocks that can be evicted. This allows the recompiler to evict dirty blocks in preference to freeing usable blocks when the free list is empty.
Increase the number of available code blocks on x86.
Increase the non-ARM code allocator memory to 128 MB.
This reduces the amount of code block churning when running software with a lot of code, eg Windows XP.
 2019-01-19 21:54:14 +00:00
SarahW
66fba50e06 Add new codegen memory allocator. This allows the recompiler to allocate memory from a central pool as required. This central pool is by default 64 MB on x86, x86-64 and ARMv8, and 32 MB on ARMv7. 
The current design does not allow for ARMv8 literal pools, therefore these have been removed.
 2019-01-12 15:15:43 +00:00
SarahW
3c7d1b1204 Ensure that taken jump/branch instructions do not count as 0 cycles. Fixes Windows 95 hang with K6. 2019-01-06 13:46:17 +00:00
SarahW
cfd4ac3a4f Added initial timing model for K6 CPUs. 2018-12-09 22:17:11 +00:00
SarahW
7ec6f1e4ce Added Winchip 2 timing model. 2018-12-05 20:54:56 +00:00
SarahW
43b5b83644 Reduce codeblock_hash table to uint16_t. 2018-11-30 13:18:56 +00:00
SarahW
9ff1c7f409 Further reductions to codeblock_t size - replace link pointers with uint16_t block indicies, shrink ins to uint8_t, remove endpc. codeblock_t now fits in a 64-byte cacheline on 32-bit platforms. 2018-11-29 20:05:12 +00:00
SarahW
2007c25177 Start reducing size of codeblock_t structure. 
Re-arrange all variables needed to run a block to fit in a single cache line.
 2018-11-28 20:29:48 +00:00
SarahW
d63176e472 Move dynarec code memory out of codeblock structure. 2018-11-28 18:43:40 +00:00
SarahW
2a19183d83 Added debug code to log execution rate of non-recompiled instructions. 2018-11-24 20:16:52 +00:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00
SarahW
03fe25d818 First stage of dynamic recompiler rewrite. 
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
 2018-06-17 20:26:15 +01:00
SarahW
a602cb0580 Tweaked recompiler block lookup. Fixes massive slowdown seen on some Windows 9x installations at startup & possibly some other slowdowns. 2017-12-16 17:26:42 +00:00
SarahW
c71963727a Recompiler now uses logical address of 0xffffffff rather than 0 to represent invalid block. Fixes some Unixes when recompiler enabled. 2017-10-15 21:32:01 +01:00
SarahW
a883399781 Added AGI stalls to 486 and later CPUs. 
Reworked codegen timing a bit - split timing tables into CPU-specific and generic files.
A few other timing tweaks.
 2017-07-23 17:41:24 +01:00
SarahW
3a7c4687d6 Reduce self modifying code granularity from 64 bytes to 16. 2017-06-13 21:05:10 +01:00
SarahW
083ca3d4a2 Slight optimisation when DS/SS are 'flat' (base=0, limit=4G). 2017-05-24 21:50:37 +01:00
SarahW
2b892d2a7a Fixed compiler warnings for Windows builds. 
Added -Werror to Windows makefiles.
 2017-04-11 19:34:41 +01:00
SarahW
0985952317 Added code generation for RMW versions of ADD/SUB/OR/XOR/AND 2016-11-13 14:30:39 +00:00
SarahW
a174a88c49 Codeblock tree now includes both physical and virtual addresses into key. Fixes performance issues with Windows 3.1. 2016-11-08 21:30:48 +00:00
SarahW
75f9316c11 x86-32 recompiler compiles FPU instructions using direct access to register stack when top-of-stack is static. Minor speedup. 2016-09-11 15:38:05 +01:00
SarahW
eb126fd822 Moved more variables into cpu_state structure. 2016-08-21 21:28:23 +01:00
SarahW
42237ac1f8 Recompiler now only recompiles a block after seeing it twice. Improves performance on stuff that uses self modifying code - eg Doom, Duke Nukem 3D, Windows 95 idle 2016-07-31 12:33:37 +01:00
SarahW
512c8e5d44 Winchip FPU timings now more accurate. 2016-05-14 19:36:40 +01:00
SarahW
2909742567 Re-wrote broken codeblock_tree_delete() function. 2016-05-12 21:21:49 +01:00
SarahW
153c22e442 Cyrix 6x86 emulation. Based on patch from leilei. 
Moved MOV TRx, reg to correct opcode - required by Award 430VX BIOS with 6x86.
 2016-04-27 22:23:49 +01:00
SarahW
14df80109b Added recompiler block tree to x86-64 recompiler. Fixed return value in codeblock_tree_find() that could cause GCC to generate bad code. 2016-04-08 20:49:03 +01:00
SarahW
36bb949126 If recompiler block hash table points to wrong block, then walk tree to find correct block instead of recompiling. Speedups of 10-20% on games that were seeing hash aliasing, eg Quake III, System Shock 2, UltraHLE etc 2016-04-06 20:48:36 +01:00
TomW
4011a246ff Added code generation for MMX instructions 2016-02-24 20:55:48 +00:00
TomW
673d785743 Writing to a memory page with code present only causes code block flushes if the data changes, or if a block is currently being recompiled. 2016-02-03 21:09:05 +00:00
TomW
e9bea8ab7e Added recompiled versions of PUSH [mem], PUSH seg, NOP, CLD, STD, JMP indirect, CALL indirect. 2015-11-17 20:52:51 +00:00
TomW
f339f00315 Interpreter and dynamic recompiler now present in a single binary. 2015-08-21 20:55:36 +01:00
TomW
5f391a1992 Reduced number of unnecessary register loads in x86-64 recompiler. 2015-08-05 20:31:20 +01:00
TomW
634c235dc2 Fix Linux build. Enable 64-bit recompiler in Linux. 2015-07-18 16:03:39 +01:00
TomW
08254b8dfb Initial 64-bit recompiler. 
Various 64-bit fixes.
Various fixes to allow building under MinGW-w64.
 2015-07-18 12:11:54 +01:00
TomW
f3607c2308 Added code generation for : 
- FCOM/FUCOM
- FSUBR/FSUBRP/FDIVR/FDIVRP
- FLDCW/FSTCW
- FILD/FIST/FISTP (16-bit, 32-bit and 64-bit variants)
- FLD/FST/FSTP double precision
- Integer and double precision variants of FADD/FSUB/FMUL/FDIV
Also added 64-bit readmemq/writememq functions.
 2015-06-13 16:14:35 +01:00
TomW
15bca849c8 Added code generation for first batch of FPU instructions; instructions added are most common instructions used in Quake. 2015-04-19 08:42:04 +01:00
TomW
bbf0011e95 Added code generation for JCXZ, LOOP, JE, JNE, JS, JNS, JB, JNB, JO, JNO, JP and JNP. 2015-04-14 20:40:40 +01:00
TomW
a97e89e857 Added code generation for register and immediate PUSH/POP, RET, relative CALL and JMP instructions. 2015-03-30 20:42:33 +01:00
TomW
ba715706b6 Added code generation for memory versions of MOV, and memory source versions of ADD, SUB, AND, OR, XOR and CMP. 2015-02-08 17:17:14 +00:00
TomW
b4592cdea3 Implemented new memory mapping to improve performance of self modifying code. 
New scheme allows code blocks to cross pages.
Reduced code block size down to 2kB.
 2015-01-28 21:58:02 +00:00
TomW
630592125c Added code generation for immediate->register and register versions of MOV, XCHG, ADD, SUB, AND, OR, XOR, TEST, CMP, INC and DEC. 2015-01-16 21:22:14 +00:00