SarahW
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cfd4ac3a4f
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Added initial timing model for K6 CPUs.
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2018-12-09 22:17:11 +00:00 |
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SarahW
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da2d819ed4
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Added WinChip 2 emulation, along with (currently non-recompiled) 3DNow! instruction emulation.
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2018-12-03 21:59:41 +00:00 |
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SarahW
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43b5b83644
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Reduce codeblock_hash table to uint16_t.
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2018-11-30 13:18:56 +00:00 |
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SarahW
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a4d3aa1912
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Move flags and eflags variables into cpu_struct.
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2018-11-28 09:42:04 +00:00 |
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SarahW
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2a19183d83
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Added debug code to log execution rate of non-recompiled instructions.
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2018-11-24 20:16:52 +00:00 |
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SarahW
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6d8af5df4a
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Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR.
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2018-10-20 20:03:28 +01:00 |
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SarahW
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8a516df476
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Added recompiled versions of FLD, FILD, FST and FSTP.
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2018-10-17 19:47:04 +01:00 |
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SarahW
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305b6cc4fd
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Added recompiled register versions of FADDP, FDIVP, FDIVRP, FMULP, FSUBP and FSUBRP.
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2018-10-08 21:44:30 +01:00 |
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SarahW
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78996b3e5c
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Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR.
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2018-10-07 22:02:31 +01:00 |
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SarahW
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872a2da788
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Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD.
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2018-08-16 21:44:41 +01:00 |
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SarahW
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4846616924
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Handle REP prefixed instructions without a dedicated REP instruction handler properly in the recompiler. Fixes Windows XP setup.
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2018-08-08 22:14:52 +01:00 |
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SarahW
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f1df9be8f6
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Added recompiled versions of JMP, CALL, RET, PUSH and POP.
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2018-08-05 16:24:15 +01:00 |
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SarahW
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f27b7f757a
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Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
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2018-07-25 20:16:58 +01:00 |
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SarahW
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91143d3c68
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Move CPU segment structures into cpu_state structure.
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2018-07-22 12:56:03 +01:00 |
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SarahW
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4e7a13f452
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Corrected effective address for POP 0x8f. Windows 95 now works on recompiler.
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2018-07-18 22:19:09 +01:00 |
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SarahW
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648aa0e3e8
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Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-17 22:08:25 +01:00 |
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SarahW
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fc27be592c
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Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-08 16:36:11 +01:00 |
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SarahW
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774f4201ee
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Recompiler now handles instruction and cycle counting.
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2018-07-06 17:51:22 +01:00 |
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SarahW
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93ec6b0692
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Recompiler now handles FPU prefixes.
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2018-07-06 17:50:32 +01:00 |
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SarahW
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94fea237b4
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Implemented effective address compilation.
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2018-06-28 22:06:42 +01:00 |
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SarahW
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ee3f9210dc
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Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
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2018-06-23 19:04:36 +01:00 |
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SarahW
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03fe25d818
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First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
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2018-06-17 20:26:15 +01:00 |
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TomW
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673d785743
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Writing to a memory page with code present only causes code block flushes if the data changes, or if a block is currently being recompiled.
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2016-02-03 21:09:05 +00:00 |
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TomW
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f339f00315
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Interpreter and dynamic recompiler now present in a single binary.
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2015-08-21 20:55:36 +01:00 |
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TomW
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b4592cdea3
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Implemented new memory mapping to improve performance of self modifying code.
New scheme allows code blocks to cross pages.
Reduced code block size down to 2kB.
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2015-01-28 21:58:02 +00:00 |
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TomW
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13226a2bd4
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Added Pentium and Pentium MMX emulation.
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2014-11-17 20:41:02 +00:00 |
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