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Commit graph pcem/src/codegen.c
Author SHA1 Message Date
SarahW
c0a7fcb343 Correct code present mask when using 16-bit addressing. Fixes graphics issues on Windows 9x with VGA 16-colour driver. 2019-04-10 22:05:26 +01:00
SarahW
7f99cb7fb1 Use correct value for MAX_INSTRUCTION_COUNT. 2019-04-01 21:24:32 +01:00
SarahW
a0ab14f56f When unrolling a loop, set op_32, ea_seg and ssegs to the correct values at the start of the loop. Fixes mode setting on Bahamas 64 and most likely some other bugs. 2019-04-01 21:23:09 +01:00
SarahW
4b99070fc0 Flush accumulators before call to non-recompiled instruction. 2019-03-16 15:47:49 +00:00
SarahW
ab124776a0 Rework self modifying code handling. 
Code blocks now have a varying level of granularity in the page and dirty masks.
Most blocks have 64-byte granularity, but blocks that are repeatedly modified
drop to 1-byte granularity. This reduces the maximum size of the affected block
significantly, but reduces recompilation due to data located too close to code.

If the block is still marked as dirty, then it is recompiled without any
immediate instruction parameters being baked into the recompiled code, instead
being fetched from the RAM array as needed. This severely reduces recompilation
rates on some SMC-heavy games, eg Duke Nukem 3D, System Shock, Screamer etc,
giving a major speedup.
 2019-03-16 14:53:26 +00:00
SarahW
8998024225 Move GPF and early exit routines out of individual code blocks and into the common helper block. 2019-01-13 12:57:32 +00:00
SarahW
66fba50e06 Add new codegen memory allocator. This allows the recompiler to allocate memory from a central pool as required. This central pool is by default 64 MB on x86, x86-64 and ARMv8, and 32 MB on ARMv7. 
The current design does not allow for ARMv8 literal pools, therefore these have been removed.
 2019-01-12 15:15:43 +00:00
SarahW
3c7d1b1204 Ensure that taken jump/branch instructions do not count as 0 cycles. Fixes Windows 95 hang with K6. 2019-01-06 13:46:17 +00:00
SarahW
e26abe7a1f Added recompiled versions of 3DNow instructions - PF2ID, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQRT, PFRSQIT1, PFSUB, PFSUBR and PI2FD. 2018-12-14 21:59:03 +00:00
SarahW
cfd4ac3a4f Added initial timing model for K6 CPUs. 2018-12-09 22:17:11 +00:00
SarahW
da2d819ed4 Added WinChip 2 emulation, along with (currently non-recompiled) 3DNow! instruction emulation. 2018-12-03 21:59:41 +00:00
SarahW
43b5b83644 Reduce codeblock_hash table to uint16_t. 2018-11-30 13:18:56 +00:00
SarahW
a4d3aa1912 Move flags and eflags variables into cpu_struct. 2018-11-28 09:42:04 +00:00
SarahW
2a19183d83 Added debug code to log execution rate of non-recompiled instructions. 2018-11-24 20:16:52 +00:00
SarahW
6d8af5df4a Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR. 2018-10-20 20:03:28 +01:00
SarahW
8a516df476 Added recompiled versions of FLD, FILD, FST and FSTP. 2018-10-17 19:47:04 +01:00
SarahW
305b6cc4fd Added recompiled register versions of FADDP, FDIVP, FDIVRP, FMULP, FSUBP and FSUBRP. 2018-10-08 21:44:30 +01:00
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
872a2da788 Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD. 2018-08-16 21:44:41 +01:00
SarahW
4846616924 Handle REP prefixed instructions without a dedicated REP instruction handler properly in the recompiler. Fixes Windows XP setup. 2018-08-08 22:14:52 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
91143d3c68 Move CPU segment structures into cpu_state structure. 2018-07-22 12:56:03 +01:00
SarahW
4e7a13f452 Corrected effective address for POP 0x8f. Windows 95 now works on recompiler. 2018-07-18 22:19:09 +01:00
SarahW
648aa0e3e8 Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-17 22:08:25 +01:00
SarahW
fc27be592c Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-08 16:36:11 +01:00
SarahW
774f4201ee Recompiler now handles instruction and cycle counting. 2018-07-06 17:51:22 +01:00
SarahW
93ec6b0692 Recompiler now handles FPU prefixes. 2018-07-06 17:50:32 +01:00
SarahW
94fea237b4 Implemented effective address compilation. 2018-06-28 22:06:42 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00
SarahW
03fe25d818 First stage of dynamic recompiler rewrite. 
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
 2018-06-17 20:26:15 +01:00
TomW
673d785743 Writing to a memory page with code present only causes code block flushes if the data changes, or if a block is currently being recompiled. 2016-02-03 21:09:05 +00:00
TomW
f339f00315 Interpreter and dynamic recompiler now present in a single binary. 2015-08-21 20:55:36 +01:00
TomW
b4592cdea3 Implemented new memory mapping to improve performance of self modifying code. 
New scheme allows code blocks to cross pages.
Reduced code block size down to 2kB.
 2015-01-28 21:58:02 +00:00
TomW
13226a2bd4 Added Pentium and Pentium MMX emulation. 2014-11-17 20:41:02 +00:00