SarahW
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6d8af5df4a
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Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR.
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2018-10-20 20:03:28 +01:00 |
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SarahW
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8a516df476
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Added recompiled versions of FLD, FILD, FST and FSTP.
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2018-10-17 19:47:04 +01:00 |
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SarahW
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78996b3e5c
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Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR.
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2018-10-07 22:02:31 +01:00 |
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SarahW
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592b07be63
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Added recompiled versions of JMP indirect, JMP far, RETF, LxS, XLAT and LEAVE.
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2018-09-29 17:42:44 +01:00 |
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SarahW
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1aadfd436d
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Added recompiled versions of CBW, CDQ, CWD, CWDE and MOVSX.
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2018-09-23 21:45:12 +01:00 |
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SarahW
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8a19e56340
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Added recompiled versions of INC and DEC.
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2018-09-12 20:16:27 +01:00 |
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SarahW
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3332897886
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Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE.
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2018-08-30 22:26:33 +01:00 |
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SarahW
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872a2da788
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Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD.
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2018-08-16 21:44:41 +01:00 |
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SarahW
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9bba93e0be
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Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG.
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2018-08-08 22:14:22 +01:00 |
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SarahW
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f1df9be8f6
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Added recompiled versions of JMP, CALL, RET, PUSH and POP.
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2018-08-05 16:24:15 +01:00 |
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SarahW
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a9d46d95ec
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Use MOVW/MOVT to load immediates on ARM instead of a literal pool.
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2018-08-02 22:09:57 +01:00 |
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SarahW
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42d62925c3
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Fix compiler warnings on ARM builds.
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2018-08-02 22:09:18 +01:00 |
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SarahW
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e64271f5bb
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Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR.
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2018-07-27 22:24:34 +01:00 |
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SarahW
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f27b7f757a
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Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
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2018-07-25 20:16:58 +01:00 |
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SarahW
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648aa0e3e8
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Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-17 22:08:25 +01:00 |
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SarahW
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e4e0f76d5c
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De-duplicate ARM literal pools.
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2018-07-08 16:36:26 +01:00 |
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SarahW
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fc27be592c
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Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-08 16:36:11 +01:00 |
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SarahW
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dc2afee957
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ARM UOP_ADD_IMM can now generate SUB instructions to better handle negative data.
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2018-07-06 17:52:33 +01:00 |
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SarahW
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94fea237b4
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Implemented effective address compilation.
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2018-06-28 22:06:42 +01:00 |
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SarahW
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ee3f9210dc
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Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
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2018-06-23 19:04:36 +01:00 |
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SarahW
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03fe25d818
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First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
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2018-06-17 20:26:15 +01:00 |
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