Jeff
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7e207db2a1
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Added PDP-10 JSP and JFCL operations (which seem to be the simplest means of getting and setting the processor flags)
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2017-03-07 13:44:43 -08:00 |
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Jeff
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0e18448423
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Added PDP-10 SUB and MUL operations
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2017-03-07 10:21:17 -08:00 |
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Jeff
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38a598d21e
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Added PDP-10 ADD operations
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2017-03-06 23:36:48 -08:00 |
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Jeff
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1b4129d7ad
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Added some ASHC tests
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2017-03-06 17:18:41 -08:00 |
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Jeff
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04ae721eb6
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Updated the extended logical operations (LSHC and ROTC) to treat the result as a 71-bit result, and ASHC to treat it as a 70-bit result
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2017-03-06 16:42:29 -08:00 |
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Jeff
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3d4795bbe4
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Updated the Int36 class with support for both signed 71-bit values (my original double-length format) and 70-bit values consisting of two signed 35-bit values (DEC's double-length format)
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2017-03-06 15:48:31 -08:00 |
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Jeff
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6b68525f24
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Fixed minor ASHC bug
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2017-03-05 16:19:25 -08:00 |
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Jeff
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e885a29788
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Whitespace
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2017-03-05 14:15:24 -08:00 |
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Jeff
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286a122b05
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Implemented (but have not yet tested) ASHC opcode for PDP-10
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2017-03-05 14:14:14 -08:00 |
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Jeff
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61e64bf3fc
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Sync'ed some of the constants used in the pdp10 and int36 modules
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2017-03-05 10:19:04 -08:00 |
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Jeff
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234e8871ba
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Added "lsh" and "rot" commands to the Int36 command-line tool to mimic the PDP-10 opcodes and test their logic
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2017-03-05 10:04:18 -08:00 |
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Jeff
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ffb7fa1221
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New improved PDP-10 processor flag handling
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2017-03-04 21:07:56 -08:00 |
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Jeff
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87e17a695c
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Fixed opIO() dispatch
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2017-03-04 16:52:44 -08:00 |
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Jeff
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1ac769431f
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Added initial logic for decoding PDP-10 input-output instructions
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2017-03-04 16:47:56 -08:00 |
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Jeff
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e04bec1af4
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Typo
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2017-03-04 14:46:26 -08:00 |
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Jeff
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5d48383363
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Added logic (untested) for ASH
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2017-03-04 14:43:21 -08:00 |
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Jeff
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20c24053b9
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Simplified ROT and ROTC, converting all right (negative) rotations into left (positive) rotations
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2017-03-04 11:22:57 -08:00 |
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Jeff
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88f66f9590
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Added ROT and ROTC (albeit untested)
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2017-03-03 21:09:45 -08:00 |
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Jeff
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a08c8c30bf
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Added LSH and LSHC (albeit untested)
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2017-03-03 17:44:27 -08:00 |
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Jeff
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b8a38c8ac6
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Finished PDP-10 logical operations
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2017-03-03 15:58:15 -08:00 |
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Jeff
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616f9d4cda
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Started work on PDP-10 logical operations
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2017-03-03 11:30:34 -08:00 |
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Jeff
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796a23ce6c
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Added some "special considerations" to PDP-10 byte pointer processing
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2017-03-03 09:01:49 -08:00 |
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Jeff
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25aa95cec8
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First cut at PDP-10 byte instructions
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2017-03-02 23:10:24 -08:00 |
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Jeff
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affaa1075c
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Finished the PDP-10 Move Magnitude opcodes, along with the Push Down and Pop Up opcodes (uncovering some SIMH weirdness along the way)
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2017-03-02 16:38:00 -08:00 |
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Jeff
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85a338b8c4
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All PDP-10 MOVN (Move Negative) opcodes implemented
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2017-03-02 10:20:11 -08:00 |
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Jeff
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84f8cece67
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All PDP-10 MOVN (Move Negative) opcodes implemented
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2017-03-02 10:19:37 -08:00 |
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Jeff
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202374dd09
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Added the PDP-10's four arithmetic flags along with a negate() function -- the first of our functions that actually needs to set those flags
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2017-03-01 17:23:54 -08:00 |
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Jeff
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e870fd6eec
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Fixed the accumulator update logic in all the PDP-10 half-word self-mode instructions, and started work on EXCH, BLT, and MOVE instructions (the BLT is a real odd-ball, and SIMH does some very strange things with the accumulator used by BLT, which we do NOT attempt to replicate; the strangeness is most noticeable when the accumulator is part of the range being transferred)
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2017-03-01 16:00:48 -08:00 |
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Jeff
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3508b1050e
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Started work on v1.34.2: More PDP-10 opcode handlers
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2017-03-01 12:26:57 -08:00 |
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Jeff
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ac06857b10
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Updated home page
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2017-02-28 19:45:04 -08:00 |
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Jeff Parsons
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5f363c97b8
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Picked up the updated blog post about the PDP-10
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2017-02-28 19:39:49 -08:00 |
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Jeff Parsons
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13d7acc9cb
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New blog post about the PDP-10
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2017-02-28 19:16:21 -08:00 |
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Jeff Parsons
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639eb6e945
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Picked up published 1.34.1 changes
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2017-02-28 17:06:29 -08:00 |
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Jeff Parsons
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32ff93ef3e
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Promoted version to 1.34.1
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2017-02-28 16:36:15 -08:00 |
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Jeff Parsons
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ce3479c422
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Promoted version to 1.34.1
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2017-02-28 16:35:16 -08:00 |
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Jeff Parsons
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51274c1a30
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Make sure all machines support JSON-encoded resources with either 'longs' or 'data' arrays
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2017-02-28 16:20:49 -08:00 |
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Jeff Parsons
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f0bfe81cc9
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Added more half-word opcode tests
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2017-02-28 15:46:47 -08:00 |
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Jeff Parsons
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cafd7c493c
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Finished writing all the half-word move permutations, now it's time to test them all (ugh)
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2017-02-28 11:02:15 -08:00 |
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Jeff Parsons
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d7b8122a40
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All HLL and HRL permutations implemented now (up next: HRR and HLR)
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2017-02-28 10:24:29 -08:00 |
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Jeff Parsons
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a1dba6a679
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Added support for assembling PDP-10 I/O instructions
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2017-02-28 09:14:56 -08:00 |
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Jeff Parsons
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c4f7262e71
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Cleaned up the integer base conversion code, and expanded the PDP-10 register dump
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2017-02-27 19:18:19 -08:00 |
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Jeff Parsons
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caa5fd6c86
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Tighten up disassembler output
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2017-02-27 18:20:34 -08:00 |
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Jeff Parsons
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8863f1127c
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Added rudimentary PDP-10 assembler capability to the built-in debugger
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2017-02-27 18:06:08 -08:00 |
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Jeff Parsons
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06324dd499
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Minor PDP-10 debugger alignment change
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2017-02-27 12:27:23 -08:00 |
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Jeff Parsons
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17e807ecb6
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Tested a couple half-word instructions (so far, so good)
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2017-02-27 12:25:13 -08:00 |
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Jeff Parsons
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0255b7b891
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Implemented all four primary half-word moves (HLL, HLR, HRL, HRR) but none of the flavors (Z, O, E); need to test the primary instructions first
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2017-02-27 09:50:28 -08:00 |
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Jeff Parsons
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aecd943c52
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Added support for PDP-10 RAM images
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2017-02-26 20:37:16 -08:00 |
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Jeff Parsons
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6cf141baf9
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getOpcode() can now handle infinite indirections without starving the emulator
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2017-02-26 12:17:21 -08:00 |
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Jeff Parsons
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ed4c031035
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Implemented my first 4 PDP-10 opcodes (HLL, HLLI, HLLM, HLLS)
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2017-02-26 10:51:49 -08:00 |
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Jeff Parsons
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0451774bc6
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Added preliminary PDP-10 opcode decoding
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2017-02-26 09:25:44 -08:00 |
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