Initial commit (a clone of the jsmachines project as of v1.15.3)
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jeffpar
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311
my_modules/pcjs-client/lib/x86.js
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my_modules/pcjs-client/lib/x86.js
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/**
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* @fileoverview Defines PCjs x86 constants.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @version 1.0
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* @suppress {missingProperties}
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* Created 2012-Sep-05
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*
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* Copyright © 2012-2014 Jeff Parsons <Jeff@pcjs.org>
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*
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* This file is part of PCjs, which is part of the JavaScript Machines Project (aka JSMachines)
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* at <http://jsmachines.net/> and <http://pcjs.org/>.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every source code file of every
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* copy or modified version of this work, and to display that copyright notice on every screen
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* that loads or runs any version of this software (see Computer.sCopyright).
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of the
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* PCjs program for purposes of the GNU General Public License, and the author does not claim
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* any copyright as to their contents.
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*/
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"use strict";
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var X86 = {
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/*
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* CPU model numbers
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*/
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MODEL_8086: 8086,
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MODEL_8088: 8088,
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MODEL_80186: 80186,
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MODEL_80188: 80188,
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MODEL_80286: 80286,
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/*
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* Processor Status flag definitions (stored in regPS)
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*/
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PS: {
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CF: 0x0001, // bit 0: Carry flag
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BIT1: 0x0002, // bit 1: reserved, always set
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PF: 0x0004, // bit 2: Parity flag
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BIT3: 0x0008, // bit 3: reserved, always clear
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AF: 0x0010, // bit 4: Auxiliary Carry flag (aka Arithmetic flag)
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BIT5: 0x0020, // bit 5: reserved, always clear
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ZF: 0x0040, // bit 6: Zero flag
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SF: 0x0080, // bit 7: Sign flag
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TF: 0x0100, // bit 8: Trap flag
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IF: 0x0200, // bit 9: Interrupt flag
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DF: 0x0400, // bit 10: Direction flag
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OF: 0x0800, // bit 11: Overflow flag
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IOPL: 0x3000, // 12-13: I/O Privilege Level, always set on 8086/80186, clear on 80286
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NT: 0x4000, // bit 14: Nested Task flag, always set on 8086/80186, clear on 80286
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BIT15: 0x8000 // bit 15: reserved, always set on 8086/80186, clear otherwise
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},
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/*
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* Machine Status Word definitions (stored in regMSW)
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*/
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MSW: {
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PE: 0x0001, // protected-mode enabled
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MP: 0x0002, // monitor processor extension (ie, coprocessor)
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EM: 0x0004, // emulate processor extension
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TS: 0x0008, // task switch indicator
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SET: 0xfff0 // on the 80286, these are always set (TODO: Verify)
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},
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SEL: {
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LEVEL: 0x0003, // selector privilege level (0-3)
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LDT: 0x0004, // table indicator (0: GDT, 1: LDT)
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MASK: 0xfff8 // table index
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},
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DESC: { // Descriptor Table Entry
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LIMIT: {
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OFFSET: 0x0
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},
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BASE: {
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OFFSET: 0x2
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},
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ACC: { // bit definitions for the access word (offset 0x4)
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OFFSET: 0x4,
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BASE1623: 0x00ff,
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MASK: 0xff00,
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TYPE: {
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MASK: 0x1f00,
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SEG: 0x1000,
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/*
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* The rest of these apply only when SEG is set
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*/
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ACCESSED: 0x0100,
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READABLE: 0x0200, // CODE: set if readable, clear if execute-only
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WRITEABLE: 0x0200, // DATA: set if writable, clear if read-only
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CONFORMING: 0x0400, // CODE: set if conforming, clear if not
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EXPDOWN: 0x0400, // DATA: set if expand-down, clear if not
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CODE: 0x0800, // set for CODE, clear for DATA
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CODE_READABLE: 0x0A00, // both CODE and READABLE
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CODE_CONFORMING: 0x0C00, // both CODE and CONFORMING
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CODE_CONFORMING_READABLE: 0x0E00, // all of CODE and CONFORMING and READABLE
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/*
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* The rest of these apply only when SEG is clear
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*/
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TSS: 0x0100,
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LDT: 0x0200,
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TSS_LDT: 0x0300,
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TSS_BUSY: 0x0300,
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GATE_CALL: 0x0400,
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GATE_TASK: 0x0500,
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GATE_INT: 0x0600,
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GATE_TRAP: 0x0700
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},
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LEVEL: {
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MASK: 0x6000,
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SHIFT: 13
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},
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PRESENT: 0x8000
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}
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},
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/*
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* Processor Exception Interrupts
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*
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* Of the following exceptions, all are designed to be restartable, except for 0x08 and 0x09 (and 0x0D
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* after an attempt to write to a read-only segment).
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*
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* Error codes are pushed onto the stack for 0x08 (always 0) and 0x0A through 0x0D.
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*
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* Priority: Instruction exception, TRAP, NMI, Processor Extension Segment Overrun, and finally INTR.
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*
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* All exceptions can also occur in real-mode, except where noted. A GP_FAULT in real-mode can be triggered
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* by "any memory reference instruction that attempts to reference [a] 16-bit word at offset 0FFFFH".
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*
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* Interrupts beyond 0x10 (up through 0x1F) are reserved for future exceptions.
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*
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* Implementation Detail: For any opcode we know must generate a UD_FAULT interrupt, we invoke opInvalid().
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* We reserve the term "undefined" for opcodes that require further investigation, and we invoke opUndefined()
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* in those cases until an opcode's behavior has been defined; at that point, it's either valid or invalid.
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*
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* As for "illegal", that's a silly (and redundant) term in this context, so we don't use it. Similarly,
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* the term "undocumented" should be limited to operations that are valid but that Intel did not document.
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*/
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EXCEPTION: {
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DIV_ERR: 0x00, // Divide Error Interrupt
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TRAP: 0x01, // Single Step (aka Trap) Interrupt
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NMI: 0x02, // Non-Maskable Interrupt
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BREAKPOINT: 0x03, // Breakpoint Interrupt
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OVERFLOW: 0x04, // INTO Overflow Interrupt (FYI, return address does NOT point to offending instruction)
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BOUND_ERR: 0x05, // BOUND Error Interrupt
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UD_FAULT: 0x06, // Invalid (aka Undefined or Illegal) Opcode (see implementation detail above)
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NM_FAULT: 0x07, // No Math Unit Available (see ESC or WAIT)
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DF_FAULT: 0x08, // Double Fault (see LIDT)
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MP_FAULT: 0x09, // Math Unit Protection Fault (see ESC)
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TS_FAULT: 0x0A, // Invalid Task State Segment Fault (protected-mode only)
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NP_FAULT: 0x0B, // Not Present Fault (protected-mode only)
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SS_FAULT: 0x0C, // Stack Fault (protected-mode only)
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GP_FAULT: 0x0D, // General Protection Fault
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MF_FAULT: 0x10 // Math Fault (see ESC or WAIT)
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},
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ERRCODE: {
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EXT: 0x0001,
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IDT: 0x0002,
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LDT: 0x0004,
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MASK: 0xfff8 // index of corresponding entry in GDT, LDT or IDT
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},
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RESULT: {
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SIZE_BYTE: 0x00100, // mask for byte arithmetic instructions (after subtracting 1)
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SIZE_WORD: 0x10000, // mask for word arithmetic instructions (after subtracting 1)
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AUXOVF_AF: 0x00010,
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AUXOVF_OF: 0x08080,
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AUXOVF_CF: 0x10100
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},
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PARITY: [ // 256-byte array with a 1 wherever the number of set bits of the array index is EVEN
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
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],
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/*
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* Bit values for opFlags, which are all reset to zero prior to each instruction
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*/
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OPFLAG: {
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NOREAD: 0x0001,
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NOWRITE: 0x0002,
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NOINTR: 0x0004, // indicates a segreg has been set, or a prefix, or an STI (delay INTR acknowledgement)
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SEG: 0x0010,
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LOCK: 0x0020,
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REPZ: 0x0040, // repeat while Z (NOTE: this value MUST match PS_ZF; see opCMPSb/opCMPSw/opSCASb/opSCASw)
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REPNZ: 0x0080, // repeat while NZ
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REPEAT: 0x0100, // this indicates that an instruction is being repeated (ie, some iteration AFTER the first)
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PUSHSP: 0x0200 // the SP register is potentially being referenced by a PUSH SP opcode, adjustment may be required
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},
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/*
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* Bit values for intFlags
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*/
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INTFLAG: {
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NONE: 0x00,
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INTR: 0x01, // h/w interrupt requested
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TRAP: 0x02, // trap (INT 0x01) requested
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HALT: 0x04, // halt (HLT) requested
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DMA: 0x08 // async DMA operation in progress
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},
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/*
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* Common opcodes
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*/
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OPCODE: {
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ES: 0x26, // opES()
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CS: 0x2E, // opCS()
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SS: 0x36, // opSS()
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DS: 0x3E, // opDS()
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PUSHSP: 0x54,
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PUSHA: 0x60,
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POPA: 0x61,
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BOUND: 0x62,
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ARPL: 0x63,
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PUSH16: 0x68,
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IMUL16: 0x69,
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PUSH8: 0x6A,
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IMUL8: 0x6B,
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INSB: 0x6C,
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INSW: 0x6D,
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OUTSB: 0x6E,
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OUTSW: 0x6F,
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ENTER: 0xC8,
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LEAVE: 0xC9,
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CALLF: 0x9A, // opCALLf()
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MOVSB: 0xA4, // opMOVSb()
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MOVSW: 0xA5, // opMOVSw()
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CMPSB: 0xA6,
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CMPSW: 0xA7,
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STOSB: 0xAA,
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STOSW: 0xAB,
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LODSB: 0xAC,
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LODSW: 0xAD,
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SCASB: 0xAE,
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SCASW: 0xAF,
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INT3: 0xCC,
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INTn: 0xCD,
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INTO: 0xCE,
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LOOPNZ: 0xE0,
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LOOPZ: 0xE1,
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LOOP: 0xE2,
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CALL: 0xE8,
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JMP: 0xE9, // JMP opcode (2-byte displacement)
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JMPS: 0xEB, // JMP opcode (1-byte displacement)
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LOCK: 0xF0,
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REPNZ: 0xF2,
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REPZ: 0xF3,
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CALLW: 0x10FF,
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CALLDW: 0x18FF,
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UD2: 0x0B0F // UD2 (invalid opcode guaranteed to generate UD_FAULT on all post-8086 processors)
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}
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};
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/*
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* Some PS flags are stored directly in regPS, hence the "direct" designation.
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*/
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X86.PS.DIRECT = (X86.PS.TF | X86.PS.IF | X86.PS.DF);
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/*
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* However, PS "arithmetic" flags are NOT stored in regPS; they are maintained across
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* separate result registers, hence the "indirect" designation.
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*/
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X86.PS.INDIRECT = (X86.PS.CF | X86.PS.PF | X86.PS.AF | X86.PS.ZF | X86.PS.SF | X86.PS.OF);
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/*
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* NOTE: This is the default for 8086/8088; other processors must tweak these bits before
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* calling setPS(). TODO: Verify that PS_1 was always set on reset, even on the 8086/8088.
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*/
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X86.PS.SET = (X86.PS.BIT1 | X86.PS.IOPL | X86.PS.NT | X86.PS.BIT15);
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/*
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* getPS() brings all the direct and indirect flags together, and setPS() performs the
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* reverse, setting all the corresponding "result registers" to match the indirect flags.
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*
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* These "result registers" are created/reset by an initial call to setPS(0); they include:
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*
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* this.resultSize (must be set to one of: SIZE_BYTE or SIZE_WORD)
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* this.resultValue
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* this.resultParitySign
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* this.resultAuxOverflow
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*
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* PS_SAHF is a subset of the arithmetic flags, and refers only to those flags that the
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* SAHF and LAHF "8080 legacy" opcodes affect.
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*/
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X86.PS.SAHF = (X86.PS.CF | X86.PS.PF | X86.PS.AF | X86.PS.ZF | X86.PS.SF);
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/*
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* Before we zero opFlags, we first see if any of the following PREFIX bits were set. If any were set, they are OR'ed
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* into opPrefixes; otherwise, opPrefixes is zeroed as well. This gives prefix-conscious instructions like LODS, MOVS,
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* STOS, CMPS, etc, a way of determining which prefixes, if any, immediately preceded them.
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*/
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X86.OPFLAG.PREFIXES = (X86.OPFLAG.SEG | X86.OPFLAG.LOCK | X86.OPFLAG.REPZ | X86.OPFLAG.REPNZ);
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if (typeof module !== 'undefined') module.exports = X86;
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