SarahW
|
8998024225
|
Move GPF and early exit routines out of individual code blocks and into the common helper block.
|
2019-01-13 12:57:32 +00:00 |
|
SarahW
|
6341caf318
|
ARM MMX fixes
|
2018-11-24 20:35:33 +00:00 |
|
SarahW
|
87191dde55
|
Added recompiled versions of FIST and FISTP.
|
2018-10-25 20:54:33 +01:00 |
|
SarahW
|
589f50e479
|
Added recompiled version of FILDq.
|
2018-10-22 21:23:09 +01:00 |
|
SarahW
|
8a516df476
|
Added recompiled versions of FLD, FILD, FST and FSTP.
|
2018-10-17 19:47:04 +01:00 |
|
SarahW
|
78996b3e5c
|
Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR.
|
2018-10-07 22:02:31 +01:00 |
|
SarahW
|
57e5549f48
|
Remove final remnants of ARM literal pool, and expand work register set to 7 registers.
|
2018-08-05 16:24:48 +01:00 |
|
SarahW
|
42d62925c3
|
Fix compiler warnings on ARM builds.
|
2018-08-02 22:09:18 +01:00 |
|
SarahW
|
f27b7f757a
|
Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
|
2018-07-25 20:16:58 +01:00 |
|
SarahW
|
94fea237b4
|
Implemented effective address compilation.
|
2018-06-28 22:06:42 +01:00 |
|
SarahW
|
ee3f9210dc
|
Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
|
2018-06-23 19:04:36 +01:00 |
|
SarahW
|
03fe25d818
|
First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
|
2018-06-17 20:26:15 +01:00 |
|