SarahW
9bba93e0be
Added recompiled versions of LEA, MOV seg, MOVZX, NEG, NOP, NOT, PUSH imm, TEST and XCHG.
2018-08-08 22:14:22 +01:00
SarahW
f1df9be8f6
Added recompiled versions of JMP, CALL, RET, PUSH and POP.
2018-08-05 16:24:15 +01:00
SarahW
f27b7f757a
Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
2018-07-25 20:16:58 +01:00
SarahW
648aa0e3e8
Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
2018-07-17 22:08:25 +01:00
SarahW
fc27be592c
Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
2018-07-08 16:36:11 +01:00
SarahW
03fe25d818
First stage of dynamic recompiler rewrite.
...
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
2018-06-17 20:26:15 +01:00
SarahW
a96e87527e
Reorganised REP instructions.
2017-07-20 21:06:21 +01:00
SarahW
d729fc8297
Added recompiled versions of MOV seg, POP seg, PUSH FS/GS, LDS,LES,LFS,LGS,LSS.
2016-12-10 12:23:06 +00:00
SarahW
0cf0c7792c
Added code generation for CLI and SEI.
2016-12-07 21:32:12 +00:00
SarahW
437a9560f2
Added code generation for FCHS, FCOMPP, and FLD constant forms.
2016-12-07 20:52:02 +00:00
SarahW
b9a7fb042f
Added code generation for RMW versions of INC/DEC
2016-11-16 21:14:38 +00:00
SarahW
a2f96effad
Added 0xDC aliases for FCOM/FCOMP - Trespasser now works.
2016-05-25 19:23:36 +01:00
TomW
4011a246ff
Added code generation for MMX instructions
2016-02-24 20:55:48 +00:00
TomW
e9bea8ab7e
Added recompiled versions of PUSH [mem], PUSH seg, NOP, CLD, STD, JMP indirect, CALL indirect.
2015-11-17 20:52:51 +00:00
TomW
f339f00315
Interpreter and dynamic recompiler now present in a single binary.
2015-08-21 20:55:36 +01:00
TomW
0bf08d9e74
x86-64 recompiler now at parity with x86-32
2015-08-04 18:36:27 +01:00
TomW
f3607c2308
Added code generation for :
...
- FCOM/FUCOM
- FSUBR/FSUBRP/FDIVR/FDIVRP
- FLDCW/FSTCW
- FILD/FIST/FISTP (16-bit, 32-bit and 64-bit variants)
- FLD/FST/FSTP double precision
- Integer and double precision variants of FADD/FSUB/FMUL/FDIV
Also added 64-bit readmemq/writememq functions.
2015-06-13 16:14:35 +01:00
TomW
9061c5d2fc
Added code generation for :
...
- TEST immediate
- register versions of NOT and NEG
- fixed shift versions of SHL, SHR and SAR
- MOVZX and MOVSX
- LEA
- CMP with memory destination
- JL, JNL, JLE, JNLE, JBE, JNBE
2015-05-30 17:08:54 +01:00
TomW
15bca849c8
Added code generation for first batch of FPU instructions; instructions added are most common instructions used in Quake.
2015-04-19 08:42:04 +01:00
TomW
bbf0011e95
Added code generation for JCXZ, LOOP, JE, JNE, JS, JNS, JB, JNB, JO, JNO, JP and JNP.
2015-04-14 20:40:40 +01:00
TomW
a97e89e857
Added code generation for register and immediate PUSH/POP, RET, relative CALL and JMP instructions.
2015-03-30 20:42:33 +01:00
TomW
ba715706b6
Added code generation for memory versions of MOV, and memory source versions of ADD, SUB, AND, OR, XOR and CMP.
2015-02-08 17:17:14 +00:00
TomW
630592125c
Added code generation for immediate->register and register versions of MOV, XCHG, ADD, SUB, AND, OR, XOR, TEST, CMP, INC and DEC.
2015-01-16 21:22:14 +00:00
