SarahW
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6a09e9636c
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Disable a lot of dynarec sanity checks in release builds.
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2020-11-14 19:33:51 +00:00 |
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SarahW
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25fe224ea9
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Add dynarec optimisation for UOP_MOV_IMM, to avoid register allocation
if the destination register won't be immediately used again.
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2020-11-14 19:33:50 +00:00 |
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SarahW
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0d7103368a
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Add register rename optimisation to dynarec to eliminate some redundant
UOP_MOVs.
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2020-11-14 19:33:50 +00:00 |
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SarahW
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a0ab14f56f
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When unrolling a loop, set op_32, ea_seg and ssegs to the correct values at the start of the loop. Fixes mode setting on Bahamas 64 and most likely some other bugs.
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2019-04-01 21:23:09 +01:00 |
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SarahW
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7e099c277e
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Added basic loop unrolling. Blocks that end in a JMP, LOOP or conditional branch to a previous instruction in the block will be unrolled up to 10 times.
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2019-03-25 19:07:51 +00:00 |
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SarahW
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3f2d9ecf87
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Optimise out redundant uOPs, where the output register is never read.
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2019-02-10 12:32:25 +00:00 |
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SarahW
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d66731f85a
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In codegen_ir_compile(), rearrange order of register lookups and order barrier flushing to reduce pointless writes of temporary registers.
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2019-02-03 21:35:24 +00:00 |
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SarahW
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66fba50e06
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Add new codegen memory allocator. This allows the recompiler to allocate memory from a central pool as required. This central pool is by default 64 MB on x86, x86-64 and ARMv8, and 32 MB on ARMv7.
The current design does not allow for ARMv8 literal pools, therefore these have been removed.
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2019-01-12 15:15:43 +00:00 |
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SarahW
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87191dde55
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Added recompiled versions of FIST and FISTP.
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2018-10-25 20:54:33 +01:00 |
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SarahW
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3332897886
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Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE.
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2018-08-30 22:26:33 +01:00 |
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SarahW
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f27b7f757a
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Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
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2018-07-25 20:16:58 +01:00 |
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SarahW
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648aa0e3e8
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Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-17 22:08:25 +01:00 |
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SarahW
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774f4201ee
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Recompiler now handles instruction and cycle counting.
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2018-07-06 17:51:22 +01:00 |
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SarahW
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94fea237b4
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Implemented effective address compilation.
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2018-06-28 22:06:42 +01:00 |
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SarahW
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ee3f9210dc
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Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
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2018-06-23 19:04:36 +01:00 |
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SarahW
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03fe25d818
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First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
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2018-06-17 20:26:15 +01:00 |
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