Added WinChip 2 emulation, along with (currently non-recompiled) 3DNow! instruction emulation.
This commit is contained in:
SarahW
parent
5043cff3f9
commit
da2d819ed4
8 changed files with 607 additions and 25 deletions
146
src/cpu.c
146
src/cpu.c
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@ -34,6 +34,7 @@ OpFn *x86_dynarec_opcodes_df_a16;
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OpFn *x86_dynarec_opcodes_df_a32;
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OpFn *x86_dynarec_opcodes_REPE;
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OpFn *x86_dynarec_opcodes_REPNE;
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OpFn *x86_dynarec_opcodes_3DNOW;
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OpFn *x86_opcodes;
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OpFn *x86_opcodes_0f;
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@ -55,6 +56,7 @@ OpFn *x86_opcodes_df_a16;
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OpFn *x86_opcodes_df_a32;
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OpFn *x86_opcodes_REPE;
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OpFn *x86_opcodes_REPNE;
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OpFn *x86_opcodes_3DNOW;
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enum
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{
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@ -68,6 +70,12 @@ enum
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CPUID_MMX = (1 << 23)
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};
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/*Addition flags returned by CPUID function 0x80000001*/
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enum
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{
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CPUID_3DNOW = (1 << 31)
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};
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int cpu = 3, cpu_manufacturer = 0;
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CPU *cpu_s;
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int cpu_multi;
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@ -79,6 +87,7 @@ int cpu_hasMMX, cpu_hasMSR;
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int cpu_hasCR4;
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int cpu_hasCX8;
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int cpu_hasVME;
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int cpu_has3DNOW;
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int cpu_use_dynarec;
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int cpu_cyrix_alignment;
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@ -402,8 +411,22 @@ CPU cpus_WinChip[] =
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{"WinChip 166", CPU_WINCHIP, 15, 166666666, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15,15,7,7, (5*8)/2},
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{"WinChip 180", CPU_WINCHIP, 16, 180000000, 3, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*7},
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{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
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{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
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{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
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{"WinChip 2/200", CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
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{"WinChip 2/240", CPU_WINCHIP2, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_WinChip_SS7[] =
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{
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/*IDT WinChip (Super Socket 7)*/
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{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 33333333, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
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{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 37500000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
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{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 30000000, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
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{"WinChip 2/200", CPU_WINCHIP2, 17, 200000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*8},
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{"WinChip 2/225", CPU_WINCHIP2, 17, 225000000, 3, 37500000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 3*9},
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{"WinChip 2/240", CPU_WINCHIP2, 17, 240000000, 6, 30000000, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
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{"WinChip 2/250", CPU_WINCHIP2, 17, 250000000, 6, 41666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 4*7},
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{"", -1, 0, 0, 0}
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};
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@ -505,6 +528,7 @@ void cpu_set()
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cpu_hasMSR = 0;
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cpu_hasCR4 = 0;
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cpu_hasCX8 = 0;
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cpu_has3DNOW = 0;
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ccr0 = ccr1 = ccr2 = ccr3 = ccr4 = ccr5 = ccr6 = 0;
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has_vlb = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type <= CPU_Cx5x86);
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@ -548,8 +572,10 @@ void cpu_set()
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x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
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x86_opcodes_REPE = ops_REPE;
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x86_opcodes_REPNE = ops_REPNE;
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x86_opcodes_3DNOW = ops_3DNOW;
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x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
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x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
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x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOW;
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if (hasfpu)
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{
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@ -950,7 +976,7 @@ void cpu_set()
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timing_bt = 3-1; /*branch taken*/
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timing_bnt = 1; /*branch not taken*/
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cpu_hasrdtsc = 1;
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msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
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msr.fcr = (1 << 8) | (1 << 16);
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cpu_hasMMX = cpu_hasMSR = 1;
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cpu_hasCR4 = 1;
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cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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@ -978,6 +1004,46 @@ void cpu_set()
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codegen_timing_set(&codegen_timing_winchip);
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break;
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case CPU_WINCHIP2:
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x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
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timing_rr = 1; /*register dest - register src*/
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timing_rm = 2; /*register dest - memory src*/
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timing_mr = 2; /*memory dest - register src*/
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timing_mm = 3;
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timing_rml = 2; /*register dest - memory src long*/
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timing_mrl = 2; /*memory dest - register src long*/
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timing_mml = 3;
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timing_bt = 3-1; /*branch taken*/
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timing_bnt = 1; /*branch not taken*/
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cpu_hasrdtsc = 1;
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msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
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cpu_hasMMX = cpu_hasMSR = cpu_has3DNOW = 1;
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cpu_hasCR4 = 1;
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cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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/*unknown*/
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timing_int_rm = 26;
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timing_int_v86 = 82;
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timing_int_pm = 44;
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timing_int_pm_outer = 71;
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timing_iret_rm = 7;
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timing_iret_v86 = 26;
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timing_iret_pm = 10;
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timing_iret_pm_outer = 26;
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timing_call_rm = 4;
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timing_call_pm = 15;
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timing_call_pm_gate = 26;
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timing_call_pm_gate_inner = 35;
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timing_retf_rm = 4;
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timing_retf_pm = 7;
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timing_retf_pm_outer = 23;
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timing_jmp_rm = 5;
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timing_jmp_pm = 7;
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timing_jmp_pm_gate = 17;
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timing_misaligned = 2;
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cpu_cyrix_alignment = 1;
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codegen_timing_set(&codegen_timing_winchip);
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break;
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case CPU_PENTIUM:
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x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
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timing_rr = 1; /*register dest - register src*/
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@ -1308,7 +1374,7 @@ void cpu_CPUID()
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else
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{
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EBX = 0x746e6543; /*CentaurHauls*/
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ECX = 0x736c7561;
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ECX = 0x736c7561;
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EDX = 0x48727561;
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}
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}
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@ -1317,14 +1383,74 @@ void cpu_CPUID()
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EAX = 0x540;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_hasCX8)
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EDX |= CPUID_CMPXCHG8B;
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if (cpu_hasCX8)
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EDX |= CPUID_CMPXCHG8B;
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if (msr.fcr & (1 << 9))
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EDX |= CPUID_MMX;
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}
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else
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EAX = EBX = ECX = EDX = 0;
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break;
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case CPU_WINCHIP2:
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switch (EAX)
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{
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case 0:
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EAX = 1;
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if (msr.fcr2 & (1 << 14))
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{
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EBX = msr.fcr3 >> 32;
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ECX = msr.fcr3 & 0xffffffff;
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EDX = msr.fcr2 >> 32;
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}
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else
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{
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EBX = 0x746e6543; /*CentaurHauls*/
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ECX = 0x736c7561;
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EDX = 0x48727561;
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}
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break;
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case 1:
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EAX = 0x580;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_hasCX8)
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EDX |= CPUID_CMPXCHG8B;
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if (msr.fcr & (1 << 9))
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EDX |= CPUID_MMX;
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break;
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case 0x80000000:
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EAX = 0x80000005;
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break;
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case 0x80000001:
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EAX = 0x580;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_hasCX8)
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EDX |= CPUID_CMPXCHG8B;
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if (msr.fcr & (1 << 9))
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EDX |= CPUID_MMX;
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if (cpu_has3DNOW)
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EDX |= CPUID_3DNOW;
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break;
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case 0x80000002: /*Processor name string*/
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EAX = 0x20544449; /*IDT WinChip 2-3D*/
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EBX = 0x436e6957;
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ECX = 0x20706968;
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EDX = 0x44332d32;
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break;
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case 0x80000005: /*Cache information*/
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EBX = 0x08800880; /*TLBs*/
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ECX = 0x20040120; /*L1 data cache*/
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EDX = 0x20020120; /*L1 instruction cache*/
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break;
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default:
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EAX = EBX = ECX = EDX = 0;
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break;
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}
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break;
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case CPU_PENTIUM:
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if (!EAX)
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@ -1447,6 +1573,7 @@ void cpu_RDMSR()
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switch (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type)
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{
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case CPU_WINCHIP:
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case CPU_WINCHIP2:
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EAX = EDX = 0;
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switch (ECX)
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{
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@ -1507,6 +1634,7 @@ void cpu_WRMSR()
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switch (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type)
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{
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case CPU_WINCHIP:
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case CPU_WINCHIP2:
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switch (ECX)
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{
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case 0x02:
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@ -1525,9 +1653,13 @@ void cpu_WRMSR()
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msr.fcr = EAX;
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cpu_hasMMX = EAX & (1 << 9);
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if (EAX & (1 << 1))
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cpu_hasCX8 = 1;
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cpu_hasCX8 = 1;
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else
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cpu_hasCX8 = 0;
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cpu_hasCX8 = 0;
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if ((EAX & (1 << 20)) && models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type >= CPU_WINCHIP2)
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cpu_has3DNOW = 1;
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else
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cpu_has3DNOW = 0;
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if (EAX & (1 << 29))
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CPUID = 0;
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else
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