Implement CPU clock control on SCAT. Patch from Greatpsycho.
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fbb5904b52
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3 changed files with 24 additions and 2 deletions
17
src/cpu.c
17
src/cpu.c
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@ -212,6 +212,7 @@ void cpu_set()
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cpu_nonturbo_speed = cpu_s->rspeed;
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else
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cpu_nonturbo_speed = 8000000;
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cpu_turbo = 1;
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cpu_update_waitstates();
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@ -2181,9 +2182,25 @@ void cpu_set_turbo(int turbo)
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}
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}
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int cpu_get_turbo()
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{
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return cpu_turbo;
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}
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int cpu_get_speed()
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{
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if (cpu_turbo)
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return cpu_turbo_speed;
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return cpu_nonturbo_speed;
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}
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void cpu_set_nonturbo_divider(int divider)
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{
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if (divider < 2)
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cpu_set_turbo(1);
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else
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{
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cpu_nonturbo_speed = cpu_turbo_speed / divider;
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cpu_set_turbo(0);
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}
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}
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@ -196,10 +196,13 @@ extern uint64_t xt_cpu_multi;
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extern int isa_cycles;
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#define ISA_CYCLES(x) (x * isa_cycles)
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#define CPU_CLOCK_DIVIDER_MAX 16384
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void cpu_update_waitstates();
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void cpu_set();
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void cpu_set_edx();
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void cpu_set_turbo(int turbo);
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int cpu_get_turbo();
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void cpu_set_nonturbo_divider(int divider);
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int cpu_get_speed();
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extern int has_vlb;
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@ -1046,8 +1046,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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scat_reg_valid = 1;
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break;
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case SCAT_POWER_MANAGEMENT:
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// TODO - Only use AUX parity disable bit for this version. Other bits should be implemented later.
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val &= (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x40 : 0x60;
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cpu_set_nonturbo_divider((val & 0xc) > 0 ? 1 << ((val & 0xc) >> 2) : 0);
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scat_reg_valid = 1;
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break;
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case SCAT_DRAM_CONFIGURATION:
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@ -1220,6 +1219,9 @@ uint8_t scat_read(uint16_t port, void *priv)
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case SCAT_MISCELLANEOUS_STATUS:
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val = (scat_regs[scat_index] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5);
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break;
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case SCAT_POWER_MANAGEMENT:
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val = (scat_regs[scat_index] & (cpu_get_turbo() ? 0xF3 : 0xFF));
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break;
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case SCAT_DRAM_CONFIGURATION:
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if ((scat_regs[SCAT_VERSION] & 0xF0) == 0) val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
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else val = scat_regs[scat_index];
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