diff --git a/src/cpu.c b/src/cpu.c
index ce1dbc0..99c0c8b 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -212,6 +212,7 @@ void cpu_set()
                 cpu_nonturbo_speed = cpu_s->rspeed;
         else
                 cpu_nonturbo_speed = 8000000;
+        cpu_turbo = 1;
 
         cpu_update_waitstates();
   
@@ -2181,9 +2182,25 @@ void cpu_set_turbo(int turbo)
         }
 }
 
+int cpu_get_turbo()
+{
+        return cpu_turbo;
+}
+
 int cpu_get_speed()
 {
         if (cpu_turbo)
                 return cpu_turbo_speed;
         return cpu_nonturbo_speed;
 }
+
+void cpu_set_nonturbo_divider(int divider)
+{
+        if (divider < 2)
+                cpu_set_turbo(1);
+        else
+        {
+                cpu_nonturbo_speed = cpu_turbo_speed / divider;
+                cpu_set_turbo(0);
+        }
+}
diff --git a/src/cpu.h b/src/cpu.h
index ee54925..97acec1 100644
--- a/src/cpu.h
+++ b/src/cpu.h
@@ -196,10 +196,13 @@ extern uint64_t xt_cpu_multi;
 extern int isa_cycles;
 #define ISA_CYCLES(x) (x * isa_cycles)
 
+#define CPU_CLOCK_DIVIDER_MAX 16384
 void cpu_update_waitstates();
 void cpu_set();
 void cpu_set_edx();
 void cpu_set_turbo(int turbo);
+int cpu_get_turbo();
+void cpu_set_nonturbo_divider(int divider);
 int cpu_get_speed();
 
 extern int has_vlb;
diff --git a/src/scat.c b/src/scat.c
index 2e29d17..ca33af5 100644
--- a/src/scat.c
+++ b/src/scat.c
@@ -1046,8 +1046,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
                         scat_reg_valid = 1;
                         break;
                         case SCAT_POWER_MANAGEMENT:
-                        // TODO - Only use AUX parity disable bit for this version. Other bits should be implemented later.
-                        val &= (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x40 : 0x60;
+                        cpu_set_nonturbo_divider((val & 0xc) > 0 ? 1 << ((val & 0xc) >> 2) : 0);
                         scat_reg_valid = 1;
                         break;
                         case SCAT_DRAM_CONFIGURATION:
@@ -1220,6 +1219,9 @@ uint8_t scat_read(uint16_t port, void *priv)
                         case SCAT_MISCELLANEOUS_STATUS:
                         val = (scat_regs[scat_index] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5);
                         break;
+                        case SCAT_POWER_MANAGEMENT:
+                        val = (scat_regs[scat_index] & (cpu_get_turbo() ? 0xF3 : 0xFF));
+                        break;
                         case SCAT_DRAM_CONFIGURATION:
                         if ((scat_regs[SCAT_VERSION] & 0xF0) == 0) val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
                         else val = scat_regs[scat_index];