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Tweak 486 prefetch timing when cache disabled, to account for burst accesses. Improves CPU speed detection on SiS496/497.

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SarahW 2018-04-20 10:58:12 +01:00
commit d489dddeee
1 changed files with 1 additions and 1 deletions
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src/cpu.c
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@ -1681,7 +1681,7 @@ void cpu_update_waitstates()
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles; cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles;
} }
if (is486) if (is486)
cpu_prefetch_cycles *= 4; cpu_prefetch_cycles = (cpu_prefetch_cycles * 11) / 16;
cpu_mem_prefetch_cycles = cpu_prefetch_cycles; cpu_mem_prefetch_cycles = cpu_prefetch_cycles;
if (cpu_s->rspeed <= 8000000) if (cpu_s->rspeed <= 8000000)
cpu_rom_prefetch_cycles = cpu_mem_prefetch_cycles; cpu_rom_prefetch_cycles = cpu_mem_prefetch_cycles;