From d489dddeee3ab3d106db69968a524089f2cff2a1 Mon Sep 17 00:00:00 2001
From: SarahW <pcem@pcem-emulator.co.uk>
Date: Fri, 20 Apr 2018 10:58:12 +0100
Subject: [PATCH] Tweak 486 prefetch timing when cache disabled, to account for
 burst accesses. Improves CPU speed detection on SiS496/497.

---
 src/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu.c b/src/cpu.c
index d380c6b..c5958c5 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -1681,7 +1681,7 @@ void cpu_update_waitstates()
                 cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles;
         }
         if (is486)
-                cpu_prefetch_cycles *= 4;
+                cpu_prefetch_cycles = (cpu_prefetch_cycles * 11) / 16;
         cpu_mem_prefetch_cycles = cpu_prefetch_cycles;
         if (cpu_s->rspeed <= 8000000)
                 cpu_rom_prefetch_cycles = cpu_mem_prefetch_cycles;