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Added correct clock support for S3 Trio64 (Number Nine 9FX).

Browse source 
Seperated TGUI9440 and TVGA8900D implementations.
Modes > 8 bpp now handled more logically in SVGA core.
Fixed broken status window for most SVGA cards.
Masking of address on 'legacy' VGA memory ranges now handled better.
This commit is contained in:
TomW 2013-11-20 21:34:09 +00:00
commit a8b286a2ec
21 changed files with 1382 additions and 937 deletions
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2
src/Makefile.mingw
View file

@ -17,7 +17,7 @@ OBJ = 386.o 808x.o acer386sx.o ali1429.o amstrad.o cdrom-ioctl.o \
vid_hercules.o vid_icd2061.o vid_ics2595.o vid_mda.o vid_olivetti_m24.o \
vid_oti067.o vid_paradise.o vid_pc1512.o vid_pc1640.o vid_pc200.o vid_s3.o \
vid_s3_virge.o vid_sdac_ramdac.o vid_stg_ramdac.o vid_svga.o vid_svga_render.o \
vid_tandy.o vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o \
vid_tandy.o vid_tgui9440.o vid_tkd8001_ramdac.o vid_tvga.o vid_unk_ramdac.o vid_vga.o \
vid_voodoo.o video.o wd76c10.o win.o win-d3d.o win-ddraw.o win-keyboard.o win-midi.o \
win-mouse.o win-timer.o win-video.o x86seg.o x87.o xtide.o pc.res
FMOBJ = fmopl.o ymf262.o

9
src/vid_ati18800.c
View file

@ -160,6 +160,13 @@ void ati18800_force_redraw(void *p)
ati18800->svga.fullchange = changeframecount;
}
int ati18800_add_status_info(char *s, int max_len, void *p)
{
ati18800_t *ati18800 = (ati18800_t *)p;
return svga_add_status_info(s, max_len, &ati18800->svga);
}
device_t ati18800_device =
{
"ATI-18800",
@ -168,6 +175,6 @@ device_t ati18800_device =
NULL,
ati18800_speed_changed,
ati18800_force_redraw,
svga_add_status_info
ati18800_add_status_info
};

9
src/vid_ati28800.c
View file

@ -181,6 +181,13 @@ void ati28800_force_redraw(void *p)
ati28800->svga.fullchange = changeframecount;
}
int ati28800_add_status_info(char *s, int max_len, void *p)
{
ati28800_t *ati28800 = (ati28800_t *)p;
return svga_add_status_info(s, max_len, &ati28800->svga);
}
device_t ati28800_device =
{
"ATI-28800",
@ -189,5 +196,5 @@ device_t ati28800_device =
NULL,
ati28800_speed_changed,
ati28800_force_redraw,
svga_add_status_info
ati28800_add_status_info
};

13
src/vid_ati_mach64.c
View file

@ -336,21 +336,25 @@ void mach64_updatemapping(mach64_t *mach64)
mem_mapping_set_p(&mach64->svga.mapping, mach64);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
mem_mapping_enable(&mach64->mmio_mapping);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_handler(&mach64->svga.mapping, mach64_read, NULL, NULL, mach64_write, NULL, NULL);
mem_mapping_set_p(&mach64->svga.mapping, mach64);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
mem_mapping_set_p(&mach64->svga.mapping, svga);
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
mem_mapping_set_p(&mach64->svga.mapping, svga);
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
if (mach64->linear_base)
@ -2081,6 +2085,13 @@ void mach64_force_redraw(void *p)
mach64->svga.fullchange = changeframecount;
}
int mach64_add_status_info(char *s, int max_len, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
return svga_add_status_info(s, max_len, &mach64->svga);
}
device_t mach64gx_device =
{
"ATI Mach64GX",
@ -2089,5 +2100,5 @@ device_t mach64gx_device =
NULL,
mach64_speed_changed,
mach64_force_redraw,
svga_add_status_info
mach64_add_status_info
};

18
src/vid_cl5429.c
View file

@ -17,6 +17,7 @@ typedef struct gd5429_t
svga_t svga;
uint32_t bank[2];
uint32_t mask;
struct
{
@ -228,19 +229,23 @@ void gd5429_recalc_mapping(gd5429_t *gd5429)
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_disable(&gd5429->mmio_mapping);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
if (svga->seqregs[0x17] & 0x04)
mem_mapping_set_addr(&gd5429->mmio_mapping, 0xb8000, 0x00100);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
mem_mapping_disable(&gd5429->mmio_mapping);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
mem_mapping_disable(&gd5429->mmio_mapping);
svga->banked_mask = 0x7fff;
break;
}
}
@ -294,7 +299,9 @@ void gd5429_write_linear(uint32_t addr, uint8_t val, void *p);
void gd5429_write(uint32_t addr, uint8_t val, void *p)
{
gd5429_t *gd5429 = (gd5429_t *)p;
svga_t *svga = &gd5429->svga;
// pclog("gd5429_write : %05X %02X ", addr, val);
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + gd5429->bank[(addr >> 15) & 1];
// pclog("%08X\n", addr);
gd5429_write_linear(addr, val, p);
@ -303,8 +310,10 @@ void gd5429_write(uint32_t addr, uint8_t val, void *p)
uint8_t gd5429_read(uint32_t addr, void *p)
{
gd5429_t *gd5429 = (gd5429_t *)p;
svga_t *svga = &gd5429->svga;
uint8_t ret;
// pclog("gd5429_read : %05X ", addr);
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + gd5429->bank[(addr >> 15) & 1];
ret = svga_read_linear(addr, &gd5429->svga);
// pclog("%08X %02X\n", addr, ret);
@ -850,6 +859,13 @@ void gd5429_force_redraw(void *p)
gd5429->svga.fullchange = changeframecount;
}
int gd5429_add_status_info(char *s, int max_len, void *p)
{
gd5429_t *gd5429 = (gd5429_t *)p;
return svga_add_status_info(s, max_len, &gd5429->svga);
}
device_t gd5429_device =
{
"Cirrus Logic GD5429",
@ -858,5 +874,5 @@ device_t gd5429_device =
NULL,
gd5429_speed_changed,
gd5429_force_redraw,
svga_add_status_info
gd5429_add_status_info
};

20
src/vid_et4000.c
View file

@ -113,7 +113,16 @@ void et4000_recalctimings(svga_t *svga)
case 5: svga->clock = cpuclock / 65000000.0; break;
default: svga->clock = cpuclock / 36000000.0; break;
}
switch (svga->bpp)
{
case 15: case 16:
svga->hdisp /= 2;
break;
case 24:
svga->hdisp /= 3;
break;
}
}
void *et4000_init()
@ -154,6 +163,13 @@ void et4000_force_redraw(void *p)
et4000->svga.fullchange = changeframecount;
}
int et4000_add_status_info(char *s, int max_len, void *p)
{
et4000_t *et4000 = (et4000_t *)p;
return svga_add_status_info(s, max_len, &et4000->svga);
}
device_t et4000_device =
{
"Tseng Labs ET4000AX",
@ -162,5 +178,5 @@ device_t et4000_device =
NULL,
et4000_speed_changed,
et4000_force_redraw,
svga_add_status_info
et4000_add_status_info
};

18
src/vid_et4000w32.c
View file

@ -251,7 +251,7 @@ void et4000w32p_recalctimings(svga_t *svga)
svga->hdisp >>= 1;
break;
case 24:
svga->hdisp /= 8;
svga->hdisp /= 3;
break;
}
}
@ -277,30 +277,37 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000)
case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0xffff;
break;
case 0x1: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0xffff;
break;
case 0x2: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x7fff;
break;
case 0x3: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x7fff;
break;
case 0x5: case 0x9: case 0xD: /*64k at A0000, MMU at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xb8000, 0x08000);
svga->banked_mask = 0xffff;
break;
case 0x6: case 0xA: case 0xE: /*32k at B0000, MMU at A8000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0x7: case 0xB: case 0xF: /*32k at B8000, MMU at A8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
@ -983,6 +990,13 @@ void et4000w32p_force_redraw(void *p)
et4000w32p->svga.fullchange = changeframecount;
}
int et4000w32p_add_status_info(char *s, int max_len, void *p)
{
et4000w32p_t *et4000w32p = (et4000w32p_t *)p;
return svga_add_status_info(s, max_len, &et4000w32p->svga);
}
device_t et4000w32p_device =
{
"Tseng Labs ET4000/w32p",
@ -991,5 +1005,5 @@ device_t et4000w32p_device =
NULL,
et4000w32p_speed_changed,
et4000w32p_force_redraw,
svga_add_status_info
et4000w32p_add_status_info
};

9
src/vid_oti067.c
View file

@ -149,6 +149,13 @@ void oti067_force_redraw(void *p)
oti067->svga.fullchange = changeframecount;
}
int oti067_add_status_info(char *s, int max_len, void *p)
{
oti067_t *oti067 = (oti067_t *)p;
return svga_add_status_info(s, max_len, &oti067->svga);
}
device_t oti067_device =
{
"Oak OTI-067",
@ -157,5 +164,5 @@ device_t oti067_device =
NULL,
oti067_speed_changed,
oti067_force_redraw,
svga_add_status_info
oti067_add_status_info
};

15
src/vid_paradise.c
View file

@ -70,15 +70,19 @@ void paradise_out(uint16_t addr, uint8_t val, void *p)
{
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
}
@ -331,6 +335,13 @@ void paradise_force_redraw(void *p)
paradise->svga.fullchange = changeframecount;
}
int paradise_add_status_info(char *s, int max_len, void *p)
{
paradise_t *paradise = (paradise_t *)p;
return svga_add_status_info(s, max_len, &paradise->svga);
}
device_t paradise_pvga1a_device =
{
"Paradise PVGA1A",
@ -339,7 +350,7 @@ device_t paradise_pvga1a_device =
NULL,
paradise_speed_changed,
paradise_force_redraw,
svga_add_status_info
paradise_add_status_info
};
device_t paradise_wd90c11_device =
{
@ -349,5 +360,5 @@ device_t paradise_wd90c11_device =
NULL,
paradise_speed_changed,
paradise_force_redraw,
svga_add_status_info
paradise_add_status_info
};

82
src/vid_s3.c
View file

@ -28,6 +28,9 @@ typedef struct s3_t
uint32_t linear_base, linear_size;
float (*getclock)(int clock, void *p);
void *getclock_p;
struct
{
uint8_t subsys_cntl;
@ -85,6 +88,16 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
switch (addr)
{
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20)
{
svga->seqregs[svga->seqaddr] = val;
switch (svga->seqaddr)
{
case 0x12: case 0x13:
svga_recalctimings(svga);
return;
}
}
if (svga->seqaddr == 4) /*Chain-4 - update banking*/
{
if (val & 8) svga->write_bank = svga->read_bank = s3->bank << 16;
@ -213,6 +226,11 @@ uint8_t s3_in(uint16_t addr, void *p)
// if (addr != 0x3da) pclog("S3 in %04X\n", addr);
switch (addr)
{
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20)
return svga->seqregs[svga->seqaddr];
break;
case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
// pclog("Read RAMDAC %04X %04X:%04X\n", addr, CS, pc);
return sdac_ramdac_in(addr, &s3->ramdac, svga);
@ -260,9 +278,14 @@ void s3_recalctimings(svga_t *svga)
else if (svga->crtc[0x43] & 0x04) svga->rowoffset += 0x100;
if (!svga->rowoffset) svga->rowoffset = 256;
svga->interlace = svga->crtc[0x42] & 0x20;
svga->clock = cpuclock / sdac_getclock((svga->miscout >> 2) & 3, &s3->ramdac);
// pclog("SVGA_CLOCK = %f %02X %f\n", svga_clock, svga_miscout, cpuclock);
if (svga->bpp > 8) svga->clock /= 2;
svga->clock = cpuclock / s3->getclock((svga->miscout >> 2) & 3, s3->getclock_p);
switch (svga->crtc[0x67] >> 4)
{
case 3: case 5: case 7:
svga->clock /= 2;
break;
}
svga->lowres = !((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10));
if ((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10))
@ -274,23 +297,23 @@ void s3_recalctimings(svga_t *svga)
break;
case 15:
svga->render = svga_render_15bpp_highres;
svga->hdisp /= 2;
break;
case 16:
svga->render = svga_render_16bpp_highres;
svga->hdisp /= 2;
break;
case 24:
svga->render = svga_render_24bpp_highres;
svga->hdisp /= 3;
break;
case 32:
svga->render = svga_render_32bpp_highres;
if (gfxcard == GFX_N9_9FX) /*Trio64*/
svga->hdisp *= 4;
if (gfxcard != GFX_N9_9FX) /*Trio64*/
svga->hdisp /= 4;
break;
}
}
// if (svga->bpp == 32) svga->hdisp *= 3;
// pclog("svga->hdisp %i %02X %i\n", svga->hdisp, svga->crtc[0x5d], svga->hdisp_time);
}
void s3_updatemapping(s3_t *s3)
@ -305,15 +328,19 @@ void s3_updatemapping(s3_t *s3)
{
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
@ -345,6 +372,7 @@ void s3_updatemapping(s3_t *s3)
{
mem_mapping_disable(&s3->linear_mapping);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
// mem_mapping_set_addr(&s3->linear_mapping, 0xa0000, 0x10000);
}
else
@ -360,6 +388,23 @@ void s3_updatemapping(s3_t *s3)
mem_mapping_disable(&s3->mmio_mapping);
}
static float s3_trio64_getclock(int clock, void *p)
{
s3_t *s3 = (s3_t *)p;
svga_t *svga = &s3->svga;
float t;
int m, n1, n2;
// pclog("Trio64_getclock %i %02X %02X\n", clock, svga->seqregs[0x13], svga->seqregs[0x12]);
if (clock == 0) return 25175000.0;
if (clock == 1) return 28322000.0;
m = svga->seqregs[0x13] + 2;
n1 = (svga->seqregs[0x12] & 0x1f) + 2;
n2 = ((svga->seqregs[0x12] >> 5) & 0x07);
t = (14318184.0 * ((float)m / (float)n1)) / (float)(1 << n2);
// pclog("TRIO64 clock %i %i %i %f %f %i\n", m, n1, n2, t, 14318184.0 * ((float)m / (float)n1), 1 << n2);
return t;
}
void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3);
@ -1591,7 +1636,10 @@ void *s3_bahamas64_init()
s3->id = 0xc1; /*Vision864P*/
s3->id_ext = 0xc1; /*Trio64*/
s3->getclock = sdac_getclock;
s3->getclock_p = &s3->ramdac;
return s3;
}
@ -1601,7 +1649,10 @@ void *s3_9fx_init()
s3->id = 0xe1;
s3->id_ext = 0x11; /*Trio64*/
s3->getclock = s3_trio64_getclock;
s3->getclock_p = s3;
return s3;
}
@ -1628,6 +1679,13 @@ void s3_force_redraw(void *p)
s3->svga.fullchange = changeframecount;
}
int s3_add_status_info(char *s, int max_len, void *p)
{
s3_t *s3 = (s3_t *)p;
return svga_add_status_info(s, max_len, &s3->svga);
}
device_t s3_bahamas64_device =
{
"Paradise Bahamas 64 (S3 Vision864)",
@ -1636,7 +1694,7 @@ device_t s3_bahamas64_device =
NULL,
s3_speed_changed,
s3_force_redraw,
svga_add_status_info
s3_add_status_info
};
device_t s3_9fx_device =
@ -1647,5 +1705,5 @@ device_t s3_9fx_device =
NULL,
s3_speed_changed,
s3_force_redraw,
svga_add_status_info
s3_add_status_info
};

13
src/vid_s3_virge.c
View file

@ -271,15 +271,19 @@ void s3_virge_updatemapping(virge_t *virge)
{
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
@ -503,6 +507,13 @@ void s3_virge_force_redraw(void *p)
virge->svga.fullchange = changeframecount;
}
int s3_virge_add_status_info(char *s, int max_len, void *p)
{
virge_t *virge = (virge_t *)p;
return svga_add_status_info(s, max_len, &virge->svga);
}
device_t s3_virge_device =
{
"Diamond Stealth 3D 2000 (S3 VIRGE)",
@ -511,5 +522,5 @@ device_t s3_virge_device =
NULL,
s3_virge_speed_changed,
s3_virge_force_redraw,
svga_add_status_info
s3_virge_add_status_info
};

3
src/vid_sdac_ramdac.c
View file

@ -121,8 +121,9 @@ uint8_t sdac_ramdac_in(uint16_t addr, sdac_ramdac_t *ramdac, svga_t *svga)
return svga_in(addr, svga);
}
float sdac_getclock(int clock, sdac_ramdac_t *ramdac)
float sdac_getclock(int clock, void *p)
{
sdac_ramdac_t *ramdac = (sdac_ramdac_t *)p;
float t;
int m, n1, n2;
// pclog("SDAC_Getclock %i %04X\n", clock, ramdac->regs[clock]);

2
src/vid_sdac_ramdac.h
View file

@ -11,4 +11,4 @@ typedef struct sdac_ramdac_t
void sdac_ramdac_out(uint16_t addr, uint8_t val, sdac_ramdac_t *ramdac, svga_t *svga);
uint8_t sdac_ramdac_in(uint16_t addr, sdac_ramdac_t *ramdac, svga_t *svga);
float sdac_getclock(int clock, sdac_ramdac_t *ramdac);
float sdac_getclock(int clock, void *p);

57
src/vid_svga.c
View file

@ -136,23 +136,27 @@ void svga_out(uint16_t addr, uint8_t val, void *p)
case 4: svga->readplane=val&3; break;
case 5: svga->writemode=val&3; svga->readmode=val&8; break;
case 6:
pclog("svga_out recalcmapping %p\n", svga);
// pclog("svga_out recalcmapping %p\n", svga);
if ((svga->gdcreg[6] & 0xc) != (val & 0xc))
{
pclog("Write mapping %02X\n", val);
// pclog("Write mapping %02X\n", val);
switch (val&0xC)
{
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
}
@ -309,49 +313,31 @@ void svga_recalctimings(svga_t *svga)
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else
{
svga->render = svga_render_8bpp_highres;
// svga_hdisp <<= 1;
}
break;
case 15:
if (svga->lowres)
svga->render = svga_render_15bpp_lowres;
else
{
svga->render = svga_render_15bpp_highres;
svga->hdisp <<= 1;
}
break;
case 16:
if (svga->lowres)
svga->render = svga_render_16bpp_lowres;
else
{
svga->render = svga_render_16bpp_highres;
svga->hdisp <<= 1;
}
break;
case 24:
if (svga->lowres)
{
svga->render = svga_render_24bpp_lowres;
svga->hdisp = ((svga->hdisp << 3) / 3);
}
else
{
svga->render = svga_render_24bpp_highres;
svga->hdisp = ((svga->hdisp << 3) / 3);
}
break;
case 32:
if (svga->lowres)
svga->render = svga_render_32bpp_lowres;
else
{
svga->render = svga_render_32bpp_highres;
svga->hdisp <<= 1;
}
break;
}
break;
@ -516,15 +502,12 @@ void svga_poll(void *p)
svga->cgastat |= 8;
x = svga->hdisp;
if (svga->bpp == 16 || svga->bpp == 15) x /= 2;
if (svga->bpp == 32) x /= 4;
if (svga->interlace && !svga->oddeven) svga->lastline++;
if (svga->interlace && svga->oddeven) svga->firstline--;
wx = x;
wy = svga->lastline - svga->firstline;
svga_doblit(svga->firstline_draw, svga->lastline_draw + 1, wx, wy, svga);
readflash = 0;
@ -548,7 +531,6 @@ void svga_poll(void *p)
svga->maback <<= 2;
svga->ca <<= 2;
svga->video_res_x = wx;
svga->video_res_y = wy + 1;
// pclog("%i %i %i\n", svga->video_res_x, svga->video_res_y, svga->lowres);
@ -668,13 +650,8 @@ void svga_write(uint32_t addr, uint8_t val, void *p)
cycles_lost += video_timing_b;
if (svga_output) pclog("Writeega %06X ",addr);
if (addr>=0xB0000) addr&=0x7FFF;
else
{
//if (gdcreg[6]&8) return;
addr &= 0xFFFF;
addr += svga->write_bank;
}
addr &= svga->banked_mask;
addr += svga->write_bank;
if (!(svga->gdcreg[6] & 1)) svga->fullchange=2;
if (svga->chain4)
@ -848,12 +825,9 @@ uint8_t svga_read(uint32_t addr, void *p)
egareads++;
// pclog("Readega %06X ",addr);
if (addr>=0xB0000) addr&=0x7FFF;
else
{
addr &= 0xFFFF;
addr += svga->read_bank;
}
addr &= svga->banked_mask;
addr += svga->read_bank;
// pclog("%05X %i %04X:%04X %02X %02X %i\n",addr,svga->chain4,CS,pc, vram[addr & 0x7fffff], vram[(addr << 2) & 0x7fffff], svga->readmode);
// pclog("%i\n", svga->readmode);
if (svga->chain4)
@ -1120,6 +1094,7 @@ void svga_doblit(int y1, int y2, int wx, int wy, svga_t *svga)
// pclog("svga_doblit start\n");
svga->frames++;
// pclog("doblit %i %i\n", y1, y2);
// pclog("svga_doblit %i %i\n", wx, svga->hdisp);
if (y1 > y2)
{
video_blit_memtoscreen(32, 0, 0, 0, xsize, ysize);
@ -1163,7 +1138,7 @@ void svga_writew(uint32_t addr, uint16_t val, void *p)
cycles_lost += video_timing_w;
if (svga_output) pclog("svga_writew: %05X ", addr);
addr = (addr & 0xffff) + svga->write_bank;
addr = (addr & svga->banked_mask) + svga->write_bank;
addr &= 0x7FFFFF;
if (addr >= svga->vram_limit)
return;
@ -1191,7 +1166,7 @@ void svga_writel(uint32_t addr, uint32_t val, void *p)
cycles_lost += video_timing_l;
if (svga_output) pclog("svga_writel: %05X ", addr);
addr = (addr & 0xffff) + svga->write_bank;
addr = (addr & svga->banked_mask) + svga->write_bank;
addr &= 0x7FFFFF;
if (addr >= svga->vram_limit)
return;
@ -1214,7 +1189,7 @@ uint16_t svga_readw(uint32_t addr, void *p)
cycles_lost += video_timing_w;
// pclog("Readw %05X ", addr);
addr = (addr & 0xffff) + svga->read_bank;
addr = (addr & svga->banked_mask) + svga->read_bank;
addr &= 0x7FFFFF;
// pclog("%08X %04X\n", addr, *(uint16_t *)&vram[addr]);
if (addr >= svga->vram_limit) return 0xffff;
@ -1235,7 +1210,7 @@ uint32_t svga_readl(uint32_t addr, void *p)
cycles_lost += video_timing_l;
// pclog("Readl %05X ", addr);
addr = (addr & 0xffff) + svga->read_bank;
addr = (addr & svga->banked_mask) + svga->read_bank;
addr &= 0x7FFFFF;
// pclog("%08X %08X\n", addr, *(uint32_t *)&vram[addr]);
if (addr >= svga->vram_limit) return 0xffffffff;

1
src/vid_svga.h
View file

@ -64,6 +64,7 @@ typedef struct svga_t
uint8_t *vram;
uint8_t *changedvram;
int vrammask;
uint32_t banked_mask;
uint32_t write_bank, read_bank;

1133
src/vid_tgui9440.c Normal file
View file

File diff suppressed because it is too large Load diff

1
src/vid_tgui9440.h Normal file
View file

@ -0,0 +1 @@
extern device_t tgui9440_device;

903
src/vid_tvga.c
View file

File diff suppressed because it is too large Load diff

1
src/vid_tvga.h
View file

@ -1,2 +1 @@
extern device_t tvga8900d_device;
extern device_t tgui9440_device;

9
src/vid_vga.c
View file

@ -114,6 +114,13 @@ void vga_force_redraw(void *p)
vga->svga.fullchange = changeframecount;
}
int vga_add_status_info(char *s, int max_len, void *p)
{
vga_t *vga = (vga_t *)p;
return svga_add_status_info(s, max_len, &vga->svga);
}
device_t vga_device =
{
"VGA",
@ -122,5 +129,5 @@ device_t vga_device =
NULL,
vga_speed_changed,
vga_force_redraw,
svga_add_status_info
vga_add_status_info
};

1
src/video.c
View file

@ -29,6 +29,7 @@
#include "vid_s3.h"
#include "vid_s3_virge.h"
#include "vid_tandy.h"
#include "vid_tgui9440.h"
#include "vid_tvga.h"
#include "vid_vga.h"