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Moved FPU register stack into cpu_state structure.

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Fixed a couple of FPU bugs in x86-64 recompiler that were introduced in rev 543, fixes lightmap issues in Half-Life.
This commit is contained in:
SarahW 2016-08-25 21:09:02 +01:00
commit 5a02b518b8
17 changed files with 907 additions and 883 deletions
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160
src/x86_ops_mmx_shift.h
View file

@ -1,7 +1,7 @@
#define MMX_GETSHIFT() \
if (cpu_mod == 3) \
{ \
shift = MM[cpu_rm].b[0]; \
shift = cpu_state.MM[cpu_rm].b[0]; \
CLOCK_CYCLES(1); \
} \
else \
@ -23,32 +23,32 @@ static int opPSxxW_imm(uint32_t fetchdat)
{
case 0x10: /*PSRLW*/
if (shift > 15)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
{
MM[reg].w[0] >>= shift;
MM[reg].w[1] >>= shift;
MM[reg].w[2] >>= shift;
MM[reg].w[3] >>= shift;
cpu_state.MM[reg].w[0] >>= shift;
cpu_state.MM[reg].w[1] >>= shift;
cpu_state.MM[reg].w[2] >>= shift;
cpu_state.MM[reg].w[3] >>= shift;
}
break;
case 0x20: /*PSRAW*/
if (shift > 15)
shift = 15;
MM[reg].sw[0] >>= shift;
MM[reg].sw[1] >>= shift;
MM[reg].sw[2] >>= shift;
MM[reg].sw[3] >>= shift;
cpu_state.MM[reg].sw[0] >>= shift;
cpu_state.MM[reg].sw[1] >>= shift;
cpu_state.MM[reg].sw[2] >>= shift;
cpu_state.MM[reg].sw[3] >>= shift;
break;
case 0x30: /*PSLLW*/
if (shift > 15)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
{
MM[reg].w[0] <<= shift;
MM[reg].w[1] <<= shift;
MM[reg].w[2] <<= shift;
MM[reg].w[3] <<= shift;
cpu_state.MM[reg].w[0] <<= shift;
cpu_state.MM[reg].w[1] <<= shift;
cpu_state.MM[reg].w[2] <<= shift;
cpu_state.MM[reg].w[3] <<= shift;
}
break;
default:
@ -72,13 +72,13 @@ static int opPSLLW_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 15)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].w[0] <<= shift;
MM[cpu_reg].w[1] <<= shift;
MM[cpu_reg].w[2] <<= shift;
MM[cpu_reg].w[3] <<= shift;
cpu_state.MM[cpu_reg].w[0] <<= shift;
cpu_state.MM[cpu_reg].w[1] <<= shift;
cpu_state.MM[cpu_reg].w[2] <<= shift;
cpu_state.MM[cpu_reg].w[3] <<= shift;
}
return 0;
@ -93,13 +93,13 @@ static int opPSLLW_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 15)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].w[0] <<= shift;
MM[cpu_reg].w[1] <<= shift;
MM[cpu_reg].w[2] <<= shift;
MM[cpu_reg].w[3] <<= shift;
cpu_state.MM[cpu_reg].w[0] <<= shift;
cpu_state.MM[cpu_reg].w[1] <<= shift;
cpu_state.MM[cpu_reg].w[2] <<= shift;
cpu_state.MM[cpu_reg].w[3] <<= shift;
}
return 0;
@ -115,13 +115,13 @@ static int opPSRLW_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 15)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].w[0] >>= shift;
MM[cpu_reg].w[1] >>= shift;
MM[cpu_reg].w[2] >>= shift;
MM[cpu_reg].w[3] >>= shift;
cpu_state.MM[cpu_reg].w[0] >>= shift;
cpu_state.MM[cpu_reg].w[1] >>= shift;
cpu_state.MM[cpu_reg].w[2] >>= shift;
cpu_state.MM[cpu_reg].w[3] >>= shift;
}
return 0;
@ -136,13 +136,13 @@ static int opPSRLW_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 15)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].w[0] >>= shift;
MM[cpu_reg].w[1] >>= shift;
MM[cpu_reg].w[2] >>= shift;
MM[cpu_reg].w[3] >>= shift;
cpu_state.MM[cpu_reg].w[0] >>= shift;
cpu_state.MM[cpu_reg].w[1] >>= shift;
cpu_state.MM[cpu_reg].w[2] >>= shift;
cpu_state.MM[cpu_reg].w[3] >>= shift;
}
return 0;
@ -160,10 +160,10 @@ static int opPSRAW_a16(uint32_t fetchdat)
if (shift > 15)
shift = 15;
MM[cpu_reg].sw[0] >>= shift;
MM[cpu_reg].sw[1] >>= shift;
MM[cpu_reg].sw[2] >>= shift;
MM[cpu_reg].sw[3] >>= shift;
cpu_state.MM[cpu_reg].sw[0] >>= shift;
cpu_state.MM[cpu_reg].sw[1] >>= shift;
cpu_state.MM[cpu_reg].sw[2] >>= shift;
cpu_state.MM[cpu_reg].sw[3] >>= shift;
return 0;
}
@ -179,10 +179,10 @@ static int opPSRAW_a32(uint32_t fetchdat)
if (shift > 15)
shift = 15;
MM[cpu_reg].sw[0] >>= shift;
MM[cpu_reg].sw[1] >>= shift;
MM[cpu_reg].sw[2] >>= shift;
MM[cpu_reg].sw[3] >>= shift;
cpu_state.MM[cpu_reg].sw[0] >>= shift;
cpu_state.MM[cpu_reg].sw[1] >>= shift;
cpu_state.MM[cpu_reg].sw[2] >>= shift;
cpu_state.MM[cpu_reg].sw[3] >>= shift;
return 0;
}
@ -200,26 +200,26 @@ static int opPSxxD_imm(uint32_t fetchdat)
{
case 0x10: /*PSRLD*/
if (shift > 31)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
{
MM[reg].l[0] >>= shift;
MM[reg].l[1] >>= shift;
cpu_state.MM[reg].l[0] >>= shift;
cpu_state.MM[reg].l[1] >>= shift;
}
break;
case 0x20: /*PSRAD*/
if (shift > 31)
shift = 31;
MM[reg].sl[0] >>= shift;
MM[reg].sl[1] >>= shift;
cpu_state.MM[reg].sl[0] >>= shift;
cpu_state.MM[reg].sl[1] >>= shift;
break;
case 0x30: /*PSLLD*/
if (shift > 31)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
{
MM[reg].l[0] <<= shift;
MM[reg].l[1] <<= shift;
cpu_state.MM[reg].l[0] <<= shift;
cpu_state.MM[reg].l[1] <<= shift;
}
break;
default:
@ -243,11 +243,11 @@ static int opPSLLD_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 31)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].l[0] <<= shift;
MM[cpu_reg].l[1] <<= shift;
cpu_state.MM[cpu_reg].l[0] <<= shift;
cpu_state.MM[cpu_reg].l[1] <<= shift;
}
return 0;
@ -262,11 +262,11 @@ static int opPSLLD_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 31)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].l[0] <<= shift;
MM[cpu_reg].l[1] <<= shift;
cpu_state.MM[cpu_reg].l[0] <<= shift;
cpu_state.MM[cpu_reg].l[1] <<= shift;
}
return 0;
@ -282,11 +282,11 @@ static int opPSRLD_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 31)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].l[0] >>= shift;
MM[cpu_reg].l[1] >>= shift;
cpu_state.MM[cpu_reg].l[0] >>= shift;
cpu_state.MM[cpu_reg].l[1] >>= shift;
}
return 0;
@ -301,11 +301,11 @@ static int opPSRLD_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 31)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
{
MM[cpu_reg].l[0] >>= shift;
MM[cpu_reg].l[1] >>= shift;
cpu_state.MM[cpu_reg].l[0] >>= shift;
cpu_state.MM[cpu_reg].l[1] >>= shift;
}
return 0;
@ -323,8 +323,8 @@ static int opPSRAD_a16(uint32_t fetchdat)
if (shift > 31)
shift = 31;
MM[cpu_reg].sl[0] >>= shift;
MM[cpu_reg].sl[1] >>= shift;
cpu_state.MM[cpu_reg].sl[0] >>= shift;
cpu_state.MM[cpu_reg].sl[1] >>= shift;
return 0;
}
@ -340,8 +340,8 @@ static int opPSRAD_a32(uint32_t fetchdat)
if (shift > 31)
shift = 31;
MM[cpu_reg].sl[0] >>= shift;
MM[cpu_reg].sl[1] >>= shift;
cpu_state.MM[cpu_reg].sl[0] >>= shift;
cpu_state.MM[cpu_reg].sl[1] >>= shift;
return 0;
}
@ -359,20 +359,20 @@ static int opPSxxQ_imm(uint32_t fetchdat)
{
case 0x10: /*PSRLW*/
if (shift > 63)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
MM[reg].q >>= shift;
cpu_state.MM[reg].q >>= shift;
break;
case 0x20: /*PSRAW*/
if (shift > 63)
shift = 63;
MM[reg].sq >>= shift;
cpu_state.MM[reg].sq >>= shift;
break;
case 0x30: /*PSLLW*/
if (shift > 63)
MM[reg].q = 0;
cpu_state.MM[reg].q = 0;
else
MM[reg].q <<= shift;
cpu_state.MM[reg].q <<= shift;
break;
default:
pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
@ -395,9 +395,9 @@ static int opPSLLQ_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 63)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
MM[cpu_reg].q <<= shift;
cpu_state.MM[cpu_reg].q <<= shift;
return 0;
}
@ -411,9 +411,9 @@ static int opPSLLQ_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 63)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
MM[cpu_reg].q <<= shift;
cpu_state.MM[cpu_reg].q <<= shift;
return 0;
}
@ -428,9 +428,9 @@ static int opPSRLQ_a16(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 63)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
MM[cpu_reg].q >>= shift;
cpu_state.MM[cpu_reg].q >>= shift;
return 0;
}
@ -444,9 +444,9 @@ static int opPSRLQ_a32(uint32_t fetchdat)
MMX_GETSHIFT();
if (shift > 63)
MM[cpu_reg].q = 0;
cpu_state.MM[cpu_reg].q = 0;
else
MM[cpu_reg].q >>= shift;
cpu_state.MM[cpu_reg].q >>= shift;
return 0;
}