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Moved FPU register stack into cpu_state structure.

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Fixed a couple of FPU bugs in x86-64 recompiler that were introduced in rev 543, fixes lightmap issues in Half-Life.
This commit is contained in:
SarahW 2016-08-25 21:09:02 +01:00
commit 5a02b518b8
17 changed files with 907 additions and 883 deletions
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40
src/x86_ops_mmx_mov.h
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@ -5,8 +5,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
MM[cpu_reg].l[1] = 0;
cpu_state.MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
cpu_state.MM[cpu_reg].l[1] = 0;
CLOCK_CYCLES(1);
}
else
@ -14,8 +14,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
uint32_t dst;
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
MM[cpu_reg].l[0] = dst;
MM[cpu_reg].l[1] = 0;
cpu_state.MM[cpu_reg].l[0] = dst;
cpu_state.MM[cpu_reg].l[1] = 0;
CLOCK_CYCLES(2);
}
@ -28,8 +28,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
MM[cpu_reg].l[1] = 0;
cpu_state.MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
cpu_state.MM[cpu_reg].l[1] = 0;
CLOCK_CYCLES(1);
}
else
@ -37,8 +37,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
uint32_t dst;
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
MM[cpu_reg].l[0] = dst;
MM[cpu_reg].l[1] = 0;
cpu_state.MM[cpu_reg].l[0] = dst;
cpu_state.MM[cpu_reg].l[1] = 0;
CLOCK_CYCLES(2);
}
@ -52,13 +52,13 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
CLOCK_CYCLES(1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;
@ -70,13 +70,13 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (cpu_mod == 3)
{
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
CLOCK_CYCLES(1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;
@ -89,7 +89,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_reg].q = MM[cpu_rm].q;
cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q;
CLOCK_CYCLES(1);
}
else
@ -97,7 +97,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
uint64_t dst;
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
MM[cpu_reg].q = dst;
cpu_state.MM[cpu_reg].q = dst;
CLOCK_CYCLES(2);
}
return 0;
@ -109,7 +109,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_reg].q = MM[cpu_rm].q;
cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q;
CLOCK_CYCLES(1);
}
else
@ -117,7 +117,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
uint64_t dst;
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
MM[cpu_reg].q = dst;
cpu_state.MM[cpu_reg].q = dst;
CLOCK_CYCLES(2);
}
return 0;
@ -130,13 +130,13 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_rm].q = MM[cpu_reg].q;
cpu_state.MM[cpu_rm].q = cpu_state.MM[cpu_reg].q;
CLOCK_CYCLES(1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;
@ -148,13 +148,13 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
if (cpu_mod == 3)
{
MM[cpu_rm].q = MM[cpu_reg].q;
cpu_state.MM[cpu_rm].q = cpu_state.MM[cpu_reg].q;
CLOCK_CYCLES(1);
}
else
{
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].q); if (cpu_state.abrt) return 1;
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].q); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;