Moved FPU register stack into cpu_state structure.
Fixed a couple of FPU bugs in x86-64 recompiler that were introduced in rev 543, fixes lightmap issues in Half-Life.
This commit is contained in:
SarahW
parent
eb126fd822
commit
5a02b518b8
17 changed files with 907 additions and 883 deletions
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@ -498,11 +498,11 @@ static void STORE_IMM_REG_L(int reg, uint32_t val)
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static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
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{
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
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{
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addbyte(0xC7); /*MOVL [addr],val*/
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addbyte(0x45);
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addbyte(addr - (uintptr_t)&cpu_state);
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addbyte(addr - (uintptr_t)&cpu_state - 128);
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addlong(val);
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}
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else if (addr < 0x100000000)
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@ -1572,11 +1572,11 @@ static void STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
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addbyte(0x0f); /*MOVZX ECX, host_reg*/
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addbyte(0xb7);
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addbyte(0xc0 | (REG_ECX << 3) | (host_reg & 7));
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
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{
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addbyte(0x89); /*MOV addr, ECX*/
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addbyte(0x45 | (REG_ECX << 3));
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addbyte((uint32_t)addr - (uint32_t)&cpu_state);
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addbyte((uint32_t)addr - (uint32_t)&cpu_state - 128);
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}
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else
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{
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@ -1588,14 +1588,14 @@ static void STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
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}
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static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
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{
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
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{
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addbyte(0x66); /*MOVW [addr],host_reg*/
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if (host_reg & 8)
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addbyte(0x44);
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addbyte(0x89);
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addbyte(0x45 | ((host_reg & 7) << 3));
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addbyte((uint32_t)addr - (uint32_t)&cpu_state);
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addbyte((uint32_t)addr - (uint32_t)&cpu_state - 128);
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}
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else
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{
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@ -1610,13 +1610,13 @@ static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
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}
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static void STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
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{
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
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if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
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{
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if (host_reg & 8)
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addbyte(0x44);
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addbyte(0x89); /*MOVL [addr],host_reg*/
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addbyte(0x45 | ((host_reg & 7) << 3));
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addbyte((uint32_t)addr - (uint32_t)&cpu_state);
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addbyte((uint32_t)addr - (uint32_t)&cpu_state - 128);
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}
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else
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{
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@ -2681,7 +2681,7 @@ static void LOAD_STACK_TO_EA(int off)
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{
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addbyte(0x8b); /*MOVL EAX,[ESP]*/
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addbyte(0x45 | (REG_EAX << 3));
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addbyte((uint32_t)&ESP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].l));
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if (off)
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{
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addbyte(0x83); /*ADD EAX, off*/
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@ -2694,7 +2694,7 @@ static void LOAD_STACK_TO_EA(int off)
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addbyte(0x0f); /*MOVZX EAX,W[ESP]*/
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addbyte(0xb7);
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addbyte(0x45 | (REG_EAX << 3));
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addbyte((uint32_t)&ESP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].w));
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if (off)
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{
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addbyte(0x66); /*ADD AX, off*/
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@ -2709,7 +2709,7 @@ static void LOAD_EBP_TO_EA(int off)
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{
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addbyte(0x8b); /*MOVL EAX,[EBP]*/
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addbyte(0x45 | (REG_EAX << 3));
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addbyte((uint32_t)&EBP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_EBP].l));
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if (off)
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{
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addbyte(0x83); /*ADD EAX, off*/
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@ -2722,7 +2722,7 @@ static void LOAD_EBP_TO_EA(int off)
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addbyte(0x0f); /*MOVZX EAX,W[EBP]*/
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addbyte(0xb7);
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addbyte(0x45 | (REG_EAX << 3));
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addbyte((uint32_t)&EBP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_BP].l));
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if (off)
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{
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addbyte(0x66); /*ADD AX, off*/
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@ -2740,14 +2740,14 @@ static void SP_MODIFY(int off)
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{
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addbyte(0x83); /*ADD [ESP], off*/
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addbyte(0x45);
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addbyte((uint32_t)&ESP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].l));
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addbyte(off);
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}
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else
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{
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addbyte(0x81); /*ADD [ESP], off*/
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addbyte(0x45);
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addbyte((uint32_t)&ESP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].l));
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addlong(off);
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}
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}
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@ -2758,7 +2758,7 @@ static void SP_MODIFY(int off)
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addbyte(0x66); /*ADD [SP], off*/
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addbyte(0x83);
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addbyte(0x45);
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addbyte((uint32_t)&SP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].w));
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addbyte(off);
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}
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else
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@ -2766,7 +2766,7 @@ static void SP_MODIFY(int off)
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addbyte(0x66); /*ADD [SP], off*/
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addbyte(0x81);
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addbyte(0x45);
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addbyte((uint32_t)&SP - (uint32_t)&EAX);
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addbyte(cpu_state_offset(regs[REG_ESP].w));
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addword(off);
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}
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}
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@ -3348,70 +3348,73 @@ static void FP_FXCH(int reg)
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addbyte(0x8b); /*MOV EAX, [TOP]*/
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addbyte(0x45);
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addbyte(cpu_state_offset(TOP));
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addbyte(0x48); /*MOV RSI, ST*/
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addbyte(0xbe);
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addquad((uint64_t)ST);
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addbyte(0x89); /*MOV EBX, EAX*/
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addbyte(0xc3);
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addbyte(0x83); /*ADD EAX, reg*/
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addbyte(0xc0);
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addbyte(reg);
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addbyte(0x48); /*MOV RDX, [RSI + RBX*8]*/
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addbyte(0x48); /*MOV RDX, ST[RBX*8]*/
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addbyte(0x8b);
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addbyte(0x14);
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addbyte(0xde);
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addbyte(0x54);
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addbyte(0xdd);
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addbyte(cpu_state_offset(ST));
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addbyte(0x83); /*AND EAX, 7*/
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addbyte(0xe0);
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addbyte(0x07);
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addbyte(0x48); /*MOV RCX, [RSI + RAX*8]*/
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addbyte(0x48); /*MOV RCX, ST[RAX*8]*/
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addbyte(0x8b);
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addbyte(0x0c);
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addbyte(0xc6);
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addbyte(0x48); /*MOV [RSI + RAX*8], RDX*/
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addbyte(0x4c);
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addbyte(0xc5);
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addbyte(cpu_state_offset(ST));
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addbyte(0x48); /*MOV ST[RAX*8], RDX*/
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addbyte(0x89);
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addbyte(0x14);
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addbyte(0xc6);
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addbyte(0x48); /*MOV [RSI + RBX*8], RCX*/
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addbyte(0x54);
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addbyte(0xc5);
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addbyte(cpu_state_offset(ST));
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addbyte(0x48); /*MOV ST[RBX*8], RCX*/
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addbyte(0x89);
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addbyte(0x0c);
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addbyte(0xde);
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addbyte(0x48); /*MOVL ESI, tag*/
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addbyte(0xbe);
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addquad((uintptr_t)cpu_state.tag);
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addbyte(0x4c);
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addbyte(0xdd);
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addbyte(cpu_state_offset(ST));
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addbyte(0x8a); /*MOV CL, tag[EAX]*/
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addbyte(0x14);
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addbyte(0x1e);
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addbyte(0x4c);
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addbyte(0x05);
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addbyte(cpu_state_offset(tag));
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addbyte(0x8a); /*MOV DL, tag[EBX]*/
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addbyte(0x0c);
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addbyte(0x06);
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addbyte(0x54);
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addbyte(0x1d);
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addbyte(cpu_state_offset(tag));
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addbyte(0x88); /*MOV tag[EBX], CL*/
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addbyte(0x14);
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addbyte(0x06);
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addbyte(0x4c);
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addbyte(0x1d);
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addbyte(cpu_state_offset(tag));
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addbyte(0x88); /*MOV tag[EAX], DL*/
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addbyte(0x0c);
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addbyte(0x1e);
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addbyte(0x54);
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addbyte(0x05);
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addbyte(cpu_state_offset(tag));
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addbyte(0x48); /*MOV RSI, ST_i64*/
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addbyte(0xbe);
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addquad((uint64_t)MM);
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addbyte(0x48); /*MOV RDX, [RSI + RBX*8]*/
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addbyte(0x48); /*MOV RDX, MM[RBX*8]*/
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addbyte(0x8b);
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addbyte(0x14);
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addbyte(0xde);
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addbyte(0x48); /*MOV RCX, [RSI + RAX*8]*/
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addbyte(0x54);
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addbyte(0xdd);
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addbyte(cpu_state_offset(MM));
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addbyte(0x48); /*MOV RCX, MM[RAX*8]*/
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addbyte(0x8b);
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addbyte(0x0c);
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addbyte(0xc6);
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addbyte(0x48); /*MOV [RSI + RAX*8], RDX*/
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addbyte(0x4c);
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addbyte(0xc5);
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addbyte(cpu_state_offset(MM));
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addbyte(0x48); /*MOV MM[RAX*8], RDX*/
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addbyte(0x89);
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addbyte(0x14);
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addbyte(0xc6);
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addbyte(0x48); /*MOV [RSI + RBX*8], RCX*/
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addbyte(0x54);
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addbyte(0xc5);
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addbyte(cpu_state_offset(MM));
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addbyte(0x48); /*MOV MM[RBX*8], RCX*/
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addbyte(0x89);
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addbyte(0x0c);
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addbyte(0xde);
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addbyte(0x4c);
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addbyte(0xdd);
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addbyte(cpu_state_offset(MM));
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reg = reg;
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}
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@ -3445,31 +3448,31 @@ static void FP_FLD(int reg)
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addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
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addbyte(0x8b);
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addbyte(0x0c);
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addbyte(0x4c);
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addbyte(0xc5);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x83); /*AND EBX, 7*/
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addbyte(0xe3);
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addbyte(0x07);
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addbyte(0x48); /*MOV RDX, ST_i64[EAX*8]*/
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addbyte(0x8b);
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addbyte(0x14);
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addbyte(0x54);
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addbyte(0xc5);
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addlong((uintptr_t)MM);
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addbyte(cpu_state_offset(MM));
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addbyte(0x8a); /*MOV AL, [tag+EAX]*/
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addbyte(0x44);
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addbyte(0x1d);
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addbyte(0x05);
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addbyte(cpu_state_offset(tag));
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addbyte(0x48); /*MOV ST[EBX*8], RCX*/
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addbyte(0x89);
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addbyte(0x0c);
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addbyte(0x4c);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x48); /*MOV ST_i64[EBX*8], RDX*/
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addbyte(0x89);
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addbyte(0x14);
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addbyte(0x54);
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addbyte(0xdd);
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addlong((uintptr_t)MM);
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addbyte(cpu_state_offset(MM));
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addbyte(0x88); /*MOV [tag+EBX], AL*/
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addbyte(0x44);
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addbyte(0x1d);
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@ -3487,9 +3490,9 @@ static void FP_FST(int reg)
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addbyte(cpu_state_offset(TOP));
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addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
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addbyte(0x8b);
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addbyte(0x0c);
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addbyte(0x4c);
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addbyte(0xc5);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x8a); /*MOV BL, [tag+EAX]*/
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addbyte(0x5c);
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addbyte(0x05);
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@ -3507,9 +3510,9 @@ static void FP_FST(int reg)
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addbyte(0x48); /*MOV ST[EAX*8], RCX*/
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addbyte(0x89);
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addbyte(0x0c);
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addbyte(0x4c);
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addbyte(0xc5);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x88); /*MOV [tag+EAX], BL*/
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addbyte(0x5c);
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addbyte(0x05);
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@ -3564,9 +3567,9 @@ static void FP_LOAD_S()
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addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
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addbyte(0x0f);
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addbyte(0xd6);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x0f); /*SETE [tag+EBX]*/
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addbyte(0x94);
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addbyte(0x44);
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@ -3592,9 +3595,9 @@ static void FP_LOAD_D()
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addbyte(cpu_state_offset(TOP));
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addbyte(0x48); /*MOVQ [ST+EBX*8], RAX*/
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addbyte(0x89);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x0f); /*SETE [tag+EBX]*/
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addbyte(0x94);
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addbyte(0x44);
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@ -3628,9 +3631,9 @@ static void FP_LOAD_IW()
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addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
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addbyte(0x0f);
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addbyte(0xd6);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x0f); /*SETE [tag+EBX]*/
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addbyte(0x94);
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addbyte(0x44);
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@ -3660,9 +3663,9 @@ static void FP_LOAD_IL()
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addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
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addbyte(0x0f);
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addbyte(0xd6);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x0f); /*SETE [tag+EBX]*/
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addbyte(0x94);
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addbyte(0x44);
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@ -3690,9 +3693,9 @@ static void FP_LOAD_IQ()
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addbyte(0xc0);
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addbyte(0x48); /*MOV [ST_i64+EBX*8], RAX*/
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addbyte(0x89);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)MM);
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addbyte(cpu_state_offset(MM));
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addbyte(0x89); /*MOV TOP, EBX*/
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addbyte(0x5d);
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addbyte(cpu_state_offset(TOP));
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@ -3702,9 +3705,9 @@ static void FP_LOAD_IQ()
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addbyte(0x66); /*MOVQ [ST+EBX*8], XMM0*/
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addbyte(0x0f);
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addbyte(0xd6);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
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addbyte(0x0c); /*OR AL, TAG_UINT64*/
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addbyte(TAG_UINT64);
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addbyte(0x88); /*MOV [tag+EBX], AL*/
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@ -3730,9 +3733,9 @@ static int FP_LOAD_REG(int reg)
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addbyte(0xf3); /*MOVQ XMM0, ST[EBX*8]*/
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addbyte(0x0f);
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addbyte(0x7e);
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addbyte(0x04);
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addbyte(0x44);
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addbyte(0xdd);
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addlong((uintptr_t)ST);
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addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xf2); /*CVTSD2SS XMM0, XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x5a);
|
||||
|
|
@ -3760,9 +3763,9 @@ static void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
|
|||
}
|
||||
addbyte(0x48); /*MOV RBX, ST[EBX*8]*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
*host_reg1 = REG_EBX;
|
||||
}
|
||||
|
|
@ -3809,9 +3812,9 @@ static int FP_LOAD_REG_INT_W(int reg)
|
|||
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
CALL_FUNC(x87_fround);
|
||||
|
||||
|
|
@ -3839,9 +3842,9 @@ static int FP_LOAD_REG_INT(int reg)
|
|||
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
CALL_FUNC(x87_fround);
|
||||
|
||||
|
|
@ -3874,9 +3877,9 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
and just load the 64-bit integer representation directly */
|
||||
addbyte(0x48); /*MOV RAX, [ST_i64+EAX*8]*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
|
||||
addbyte(0x48); /*XCHG RBX, RAX*/
|
||||
addbyte(0x93);
|
||||
|
|
@ -3893,23 +3896,23 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(TAG_UINT64);
|
||||
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(8+2);
|
||||
addbyte(5+2);
|
||||
|
||||
addbyte(0x48); /*MOV RAX, [ST_i64+EAX*8]*/
|
||||
addbyte(0x8b);
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(9+12);
|
||||
addbyte(6+12);
|
||||
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[EAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
CALL_FUNC(x87_fround);
|
||||
|
||||
|
|
@ -3931,9 +3934,6 @@ static void FP_OP_REG(int op, int dst, int src)
|
|||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
addbyte(0x89); /*MOV EBX, EAX*/
|
||||
addbyte(0xc3);
|
||||
if (dst)
|
||||
|
|
@ -3954,72 +3954,86 @@ static void FP_OP_REG(int op, int dst, int src)
|
|||
addbyte(0xe0 | REG_EBX);
|
||||
addbyte(0x07);
|
||||
}
|
||||
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag));
|
||||
addbyte(~TAG_UINT64);
|
||||
if (op == FPU_DIVR || op == FPU_SUBR)
|
||||
{
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
switch (op)
|
||||
{
|
||||
case FPU_ADD:
|
||||
addbyte(0xf2); /*ADDSD XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf2); /*ADDSD XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x58);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
case FPU_DIV:
|
||||
addbyte(0xf2); /*DIVSD XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf2); /*DIVSD XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x5e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
case FPU_DIVR:
|
||||
addbyte(0xf2); /*DIVSD XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf2); /*DIVSD XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x5e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
case FPU_MUL:
|
||||
addbyte(0xf2); /*MULSD XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf2); /*MULSD XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x59);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
case FPU_SUB:
|
||||
addbyte(0xf2); /*SUBSD XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf2); /*SUBSD XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x5c);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
case FPU_SUBR:
|
||||
addbyte(0xf2); /*SUBSD XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf2); /*SUBSD XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x5c);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
break;
|
||||
}
|
||||
addbyte(0x66); /*MOVQ [RSI+RAX*8], XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
|
||||
static void FP_OP_MEM(int op)
|
||||
|
|
@ -4027,14 +4041,12 @@ static void FP_OP_MEM(int op)
|
|||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x05);
|
||||
|
|
@ -4082,19 +4094,21 @@ static void FP_OP_MEM(int op)
|
|||
}
|
||||
if (op == FPU_DIVR || op == FPU_SUBR)
|
||||
{
|
||||
addbyte(0x66); /*MOVQ [RSI+RAX*8], XMM1*/
|
||||
addbyte(0x66); /*MOVQ ST[RAX*8], XMM1*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
addbyte(0x0c);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x4c);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0x66); /*MOVQ [RSI+RAX*8], XMM0*/
|
||||
addbyte(0x66); /*MOVQ ST[RAX*8], XMM0*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4182,9 +4196,6 @@ static void FP_COMPARE_REG(int dst, int src)
|
|||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
addbyte(0x89); /*MOV EBX, EAX*/
|
||||
addbyte(0xc3);
|
||||
if (src || dst)
|
||||
|
|
@ -4209,29 +4220,33 @@ static void FP_COMPARE_REG(int dst, int src)
|
|||
|
||||
if (src)
|
||||
{
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x66); /*COMISD XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x66); /*COMISD XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x2f);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x66); /*COMISD XMM0, [RSI+RBX*8]*/
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x66); /*COMISD XMM0, ST[RBX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x2f);
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
|
||||
addbyte(0x9f); /*LAHF*/
|
||||
|
|
@ -4251,9 +4266,6 @@ static void FP_COMPARE_MEM()
|
|||
addbyte(0x8b); /*MOV EAX, [TOP]*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0x48); /*MOV RSI, ST*/
|
||||
addbyte(0xbe);
|
||||
addquad((uint64_t)ST);
|
||||
|
||||
addbyte(0x8a); /*MOV CL, [npxs+1]*/
|
||||
addbyte(0x0c);
|
||||
|
|
@ -4261,11 +4273,12 @@ static void FP_COMPARE_MEM()
|
|||
addlong(((uintptr_t)&npxs) + 1);
|
||||
// addbyte(0xdb); /*FCLEX*/
|
||||
// addbyte(0xe2);
|
||||
addbyte(0xf3); /*MOVQ XMM0, [RSI+RAX*8]*/
|
||||
addbyte(0xf3); /*MOVQ XMM0, ST[RAX*8]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND CL, ~(C0|C2|C3)*/
|
||||
addbyte(0xe1);
|
||||
addbyte((~(C0|C2|C3)) >> 8);
|
||||
|
|
@ -4415,9 +4428,9 @@ static int LOAD_MMX_D(int guest_reg)
|
|||
int host_reg = REG_EBX;
|
||||
|
||||
addbyte(0x8b); /*MOV EBX, reg*/
|
||||
addbyte(0x04 | (host_reg << 3));
|
||||
addbyte(0x44 | (host_reg << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
|
||||
return host_reg;
|
||||
}
|
||||
|
|
@ -4430,9 +4443,9 @@ static void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
|
|||
else
|
||||
addbyte(0x48);
|
||||
addbyte(0x8b); /*MOV RBX, reg*/
|
||||
addbyte(0x04 | ((host_reg & 7) << 3));
|
||||
addbyte(0x44 | ((host_reg & 7) << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].q);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].q));
|
||||
|
||||
*host_reg1 = host_reg;
|
||||
}
|
||||
|
|
@ -4444,9 +4457,9 @@ static int LOAD_MMX_Q_MMX(int guest_reg)
|
|||
addbyte(0xf3); /*MOV XMMx, reg*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x04 | ((dst_reg & 7) << 3));
|
||||
addbyte(0x44 | ((dst_reg & 7) << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].q);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].q));
|
||||
|
||||
return dst_reg;
|
||||
}
|
||||
|
|
@ -4471,16 +4484,16 @@ static int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
|
|||
static void STORE_MMX_LQ(int guest_reg, int host_reg1)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL [reg],0*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].l[1]);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[1]));
|
||||
addlong(0);
|
||||
if (host_reg1 & 8)
|
||||
addbyte(0x44);
|
||||
addbyte(0x89); /*MOVL [reg],host_reg*/
|
||||
addbyte(0x04 | ((host_reg1 & 7) << 3));
|
||||
addbyte(0x44 | ((host_reg1 & 7) << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
}
|
||||
static void STORE_MMX_Q(int guest_reg, int host_reg1, int host_reg2)
|
||||
{
|
||||
|
|
@ -4489,18 +4502,18 @@ static void STORE_MMX_Q(int guest_reg, int host_reg1, int host_reg2)
|
|||
else
|
||||
addbyte(0x48);
|
||||
addbyte(0x89); /*MOV [reg],host_reg*/
|
||||
addbyte(0x04 | ((host_reg1 & 7) << 3));
|
||||
addbyte(0x44 | ((host_reg1 & 7) << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
}
|
||||
static void STORE_MMX_Q_MMX(int guest_reg, int host_reg)
|
||||
{
|
||||
addbyte(0x66); /*MOVQ [guest_reg],host_reg*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
addbyte(0x04 | (host_reg << 3));
|
||||
addbyte(0x44 | (host_reg << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&MM[guest_reg].q);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].q));
|
||||
}
|
||||
|
||||
#define MMX_x86_OP(name, opcode) \
|
||||
|
|
|
|||
|
|
@ -52,11 +52,11 @@ static void STORE_IMM_ADDR_W(uintptr_t addr, uint16_t val)
|
|||
}
|
||||
static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
|
||||
{
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL [addr],val*/
|
||||
addbyte(0x45);
|
||||
addbyte(addr - (uint32_t)&cpu_state);
|
||||
addbyte(addr - (uint32_t)&cpu_state - 128);
|
||||
addlong(val);
|
||||
}
|
||||
else
|
||||
|
|
@ -239,12 +239,12 @@ static void RELEASE_REG(int host_reg)
|
|||
|
||||
static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
|
||||
{
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
|
||||
{
|
||||
addbyte(0x66); /*MOVW [addr],host_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
|
||||
addbyte((uint32_t)addr - (uint32_t)&cpu_state - 128);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -256,11 +256,11 @@ static void STORE_HOST_REG_ADDR_W(uintptr_t addr, int host_reg)
|
|||
}
|
||||
static void STORE_HOST_REG_ADDR(uintptr_t addr, int host_reg)
|
||||
{
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x100)
|
||||
{
|
||||
addbyte(0x89); /*MOVL [addr],host_reg*/
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte((uint32_t)addr - (uint32_t)&cpu_state);
|
||||
addbyte((uint32_t)addr - (uint32_t)&cpu_state - 128);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1359,7 +1359,7 @@ static void LOAD_STACK_TO_EA(int off)
|
|||
{
|
||||
addbyte(0x8b); /*MOVL EAX,[ESP]*/
|
||||
addbyte(0x45 | (REG_EAX << 3));
|
||||
addbyte((uint32_t)&ESP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].l));
|
||||
if (off)
|
||||
{
|
||||
addbyte(0x83); /*ADD EAX, off*/
|
||||
|
|
@ -1372,7 +1372,7 @@ static void LOAD_STACK_TO_EA(int off)
|
|||
addbyte(0x0f); /*MOVZX EAX,W[ESP]*/
|
||||
addbyte(0xb7);
|
||||
addbyte(0x45 | (REG_EAX << 3));
|
||||
addbyte((uint32_t)&ESP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].w));
|
||||
if (off)
|
||||
{
|
||||
addbyte(0x66); /*ADD AX, off*/
|
||||
|
|
@ -1388,7 +1388,7 @@ static void LOAD_EBP_TO_EA(int off)
|
|||
{
|
||||
addbyte(0x8b); /*MOVL EAX,[EBP]*/
|
||||
addbyte(0x45 | (REG_EAX << 3));
|
||||
addbyte((uint32_t)&EBP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_EBP].l));
|
||||
if (off)
|
||||
{
|
||||
addbyte(0x83); /*ADD EAX, off*/
|
||||
|
|
@ -1401,7 +1401,7 @@ static void LOAD_EBP_TO_EA(int off)
|
|||
addbyte(0x0f); /*MOVZX EAX,W[EBP]*/
|
||||
addbyte(0xb7);
|
||||
addbyte(0x45 | (REG_EAX << 3));
|
||||
addbyte((uint32_t)&EBP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_EBP].w));
|
||||
if (off)
|
||||
{
|
||||
addbyte(0x66); /*ADD AX, off*/
|
||||
|
|
@ -1419,14 +1419,14 @@ static void SP_MODIFY(int off)
|
|||
{
|
||||
addbyte(0x83); /*ADD [ESP], off*/
|
||||
addbyte(0x45);
|
||||
addbyte((uint32_t)&ESP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].l));
|
||||
addbyte(off);
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0x81); /*ADD [ESP], off*/
|
||||
addbyte(0x45);
|
||||
addbyte((uint32_t)&ESP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].l));
|
||||
addlong(off);
|
||||
}
|
||||
}
|
||||
|
|
@ -1437,7 +1437,7 @@ static void SP_MODIFY(int off)
|
|||
addbyte(0x66); /*ADD [SP], off*/
|
||||
addbyte(0x83);
|
||||
addbyte(0x45);
|
||||
addbyte((uint32_t)&SP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].w));
|
||||
addbyte(off);
|
||||
}
|
||||
else
|
||||
|
|
@ -1445,7 +1445,7 @@ static void SP_MODIFY(int off)
|
|||
addbyte(0x66); /*ADD [SP], off*/
|
||||
addbyte(0x81);
|
||||
addbyte(0x45);
|
||||
addbyte((uint32_t)&SP - (uint32_t)&EAX);
|
||||
addbyte(cpu_state_offset(regs[REG_ESP].w));
|
||||
addword(off);
|
||||
}
|
||||
}
|
||||
|
|
@ -1600,7 +1600,7 @@ static int BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int no
|
|||
addbyte(0x75); /*JNZ +*/
|
||||
}
|
||||
if (not)
|
||||
addbyte(5+2+2+7+5+(timing_bt ? 7 : 0));
|
||||
addbyte(5+2+2+7+5+(timing_bt ? 4 : 0));
|
||||
else
|
||||
addbyte(5+2+2);
|
||||
CALL_FUNC(CF_SET);
|
||||
|
|
@ -1863,40 +1863,40 @@ static void FP_FLD(int reg)
|
|||
}
|
||||
|
||||
addbyte(0xdd); /*FLD [ST+EAX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x83); /*AND EBX, 7*/
|
||||
addbyte(0xe3);
|
||||
addbyte(0x07);
|
||||
addbyte(0x8b); /*MOV EDX, [ST_i64+EAX]*/
|
||||
addbyte(0x14);
|
||||
addbyte(0x54);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
addbyte(0x8b); /*MOV ECX, [ST_i64+4+EAX]*/
|
||||
addbyte(0x0c);
|
||||
addbyte(0x4c);
|
||||
addbyte(0xc5);
|
||||
addlong(((uintptr_t)MM) + 4);
|
||||
addbyte(cpu_state_offset(MM)+4);
|
||||
addbyte(0x8a); /*MOV AL, [tag+EAX]*/
|
||||
addbyte(0x44);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x88); /*MOV [tag+EBX], AL*/
|
||||
addbyte(0x44);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(0x89); /*MOV [ST_i64+EBX], EDX*/
|
||||
addbyte(0x14);
|
||||
addbyte(0x54);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
addbyte(0x89); /*MOV [ST_i64+EBX+4], ECX*/
|
||||
addbyte(0x0c);
|
||||
addbyte(0x4c);
|
||||
addbyte(0xdd);
|
||||
addlong(((uintptr_t)MM) + 4);
|
||||
addbyte(cpu_state_offset(MM)+4);
|
||||
|
||||
addbyte(0x89); /*MOV [TOP], EBX*/
|
||||
addbyte(0x5d);
|
||||
|
|
@ -1909,9 +1909,9 @@ static void FP_FST(int reg)
|
|||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xdd); /*FLD [ST+EAX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x8a); /*MOV BL, [tag+EAX]*/
|
||||
addbyte(0x5c);
|
||||
addbyte(0x05);
|
||||
|
|
@ -1928,9 +1928,9 @@ static void FP_FST(int reg)
|
|||
}
|
||||
|
||||
addbyte(0xdd); /*FSTP [ST+EAX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x88); /*MOV [tag+EAX], BL*/
|
||||
addbyte(0x5c);
|
||||
addbyte(0x05);
|
||||
|
|
@ -1949,24 +1949,24 @@ static void FP_FXCH(int reg)
|
|||
addbyte(reg);
|
||||
//#if 0
|
||||
addbyte(0xdd); /*FLD [ST+EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x83); /*AND EAX, 7*/
|
||||
addbyte(0xe0);
|
||||
addbyte(0x07);
|
||||
addbyte(0xdd); /*FLD [ST+EAX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdd); /*FSTP [ST+EAX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xc5);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
// addbyte(0xbe); /*MOVL ESI, tag*/
|
||||
// addlong((uintptr_t)cpu_state.tag);
|
||||
addbyte(0x8a); /*MOV CL, tag[EAX]*/
|
||||
|
|
@ -1986,7 +1986,7 @@ static void FP_FXCH(int reg)
|
|||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(0xbe); /*MOVL ESI, ST_int64*/
|
||||
addlong((uintptr_t)MM);
|
||||
addlong((uintptr_t)cpu_state.MM);
|
||||
addbyte(0x8b); /*MOV ECX, ST_int64[EAX*8]*/
|
||||
addbyte(0x0c);
|
||||
addbyte(0xc6);
|
||||
|
|
@ -2019,7 +2019,7 @@ static void FP_FXCH(int reg)
|
|||
//#endif
|
||||
#if 0
|
||||
addbyte(0xbe); /*MOVL ESI, ST*/
|
||||
addlong((uintptr_t)ST);
|
||||
addlong((uintptr_t)cpu_state.ST);
|
||||
|
||||
addbyte(0x8b); /*MOVL EDX, [ESI+EBX*8]*/
|
||||
addbyte(0x14);
|
||||
|
|
@ -2081,9 +2081,9 @@ static void FP_LOAD_S()
|
|||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x44);
|
||||
|
|
@ -2120,9 +2120,9 @@ static void FP_LOAD_D()
|
|||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x44);
|
||||
|
|
@ -2153,9 +2153,9 @@ static void FP_LOAD_IW()
|
|||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x44);
|
||||
|
|
@ -2186,9 +2186,9 @@ static void FP_LOAD_IL()
|
|||
addbyte(0x5d);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x0f); /*SETE [tag+EBX]*/
|
||||
addbyte(0x94);
|
||||
addbyte(0x44);
|
||||
|
|
@ -2207,29 +2207,29 @@ static void FP_LOAD_IQ()
|
|||
addbyte(0xe3);
|
||||
addbyte(7);
|
||||
addbyte(0x89); /*MOV [ST_i64+EBX*8], EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
addbyte(0x09); /*OR EAX, EDX*/
|
||||
addbyte(0xd0);
|
||||
addbyte(0x89); /*MOV [ST_i64+4+EBX*8], EDX*/
|
||||
addbyte(0x14);
|
||||
addbyte(0x54);
|
||||
addbyte(0xdd);
|
||||
addlong(((uint32_t)MM) + 4);
|
||||
addbyte(cpu_state_offset(MM)+4);
|
||||
addbyte(0x83); /*CMP EAX, 0*/
|
||||
addbyte(0xf8);
|
||||
addbyte(0);
|
||||
addbyte(0xdf); /*FILDl [ST_i64+EBX*8]*/
|
||||
addbyte(0x2c);
|
||||
addbyte(0x6c);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
addbyte(0x0f); /*SETE AL*/
|
||||
addbyte(0x94);
|
||||
addbyte(0xc0);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x0c); /*OR AL, TAG_UINT64*/
|
||||
addbyte(TAG_UINT64);
|
||||
addbyte(0x89); /*MOV TOP, EBX*/
|
||||
|
|
@ -2256,9 +2256,9 @@ static int FP_LOAD_REG(int reg)
|
|||
addbyte(7);
|
||||
}
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xd9); /*FSTP [ESP]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x24);
|
||||
|
|
@ -2284,9 +2284,9 @@ static void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(7);
|
||||
}
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdd); /*FSTP [ESP]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x24);
|
||||
|
|
@ -2393,9 +2393,9 @@ static int FP_LOAD_REG_INT_W(int reg)
|
|||
addbyte(7);
|
||||
}
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
addbyte(0x89); /*MOV [ESP+8], EAX*/
|
||||
addbyte(0x44);
|
||||
|
|
@ -2433,9 +2433,9 @@ static int FP_LOAD_REG_INT(int reg)
|
|||
addbyte(7);
|
||||
}
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
addbyte(0x89); /*MOV [ESP+8], EAX*/
|
||||
addbyte(0x44);
|
||||
|
|
@ -2478,13 +2478,13 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
has not been modified, then we can skip most of the conversion
|
||||
and just load the 64-bit integer representation directly */
|
||||
addbyte(0x8b); /*MOV ECX, [ST_i64+EBX*8]*/
|
||||
addbyte(0x0c);
|
||||
addbyte(0x4c);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM+4);
|
||||
addbyte(cpu_state_offset(MM)+4);
|
||||
addbyte(0x8b); /*MOV EBX, [ST_i64+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -2495,24 +2495,24 @@ static void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
|
|||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(TAG_UINT64);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(7+7+2);
|
||||
addbyte(4+4+2);
|
||||
|
||||
addbyte(0x8b); /*MOV ECX, [ST_i64+EBX*8]*/
|
||||
addbyte(0x0c);
|
||||
addbyte(0x4c);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM+4);
|
||||
addbyte(cpu_state_offset(MM)+4);
|
||||
addbyte(0x8b); /*MOV EBX, [ST_i64+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uint32_t)MM);
|
||||
addbyte(cpu_state_offset(MM));
|
||||
|
||||
addbyte(0xeb); /*JMP done*/
|
||||
addbyte(7+4+3+5+2+2+4);
|
||||
addbyte(4+4+3+5+2+2+4);
|
||||
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
|
||||
addbyte(0x89); /*MOV [ESP+8], EAX*/
|
||||
addbyte(0x44);
|
||||
|
|
@ -2575,9 +2575,9 @@ static void FP_OP_S(int op)
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
|
|
@ -2587,9 +2587,9 @@ static void FP_OP_S(int op)
|
|||
addbyte(0x04 | op);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
static void FP_OP_D(int op)
|
||||
{
|
||||
|
|
@ -2632,9 +2632,9 @@ static void FP_OP_D(int op)
|
|||
addbyte(0x24);
|
||||
addbyte(0x04);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
|
|
@ -2644,9 +2644,9 @@ static void FP_OP_D(int op)
|
|||
addbyte(0x04 | op);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
if (((npxc >> 10) & 3) && op == FPU_ADD)
|
||||
{
|
||||
addbyte(0xd9); /*FLDCW [ESP+8]*/
|
||||
|
|
@ -2664,9 +2664,9 @@ static void FP_OP_IW(int op)
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
|
|
@ -2676,9 +2676,9 @@ static void FP_OP_IW(int op)
|
|||
addbyte(0x04 | op);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
static void FP_OP_IL(int op)
|
||||
{
|
||||
|
|
@ -2689,9 +2689,9 @@ static void FP_OP_IL(int op)
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
|
|
@ -2701,9 +2701,9 @@ static void FP_OP_IL(int op)
|
|||
addbyte(0x04 | op);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
static void FP_OP_IQ(int op)
|
||||
{
|
||||
|
|
@ -2718,9 +2718,9 @@ static void FP_OP_IQ(int op)
|
|||
addbyte(0x24);
|
||||
addbyte(0x04);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
|
|
@ -2730,9 +2730,9 @@ static void FP_OP_IQ(int op)
|
|||
addbyte(0x04 | op);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FSTP [ST+EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
|
||||
#define C0 (1<<8)
|
||||
|
|
@ -2749,9 +2749,9 @@ static void FP_COMPARE_S()
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x8a); /*MOV BL, [npxs+1]*/
|
||||
addbyte(0x1d);
|
||||
addlong(((uintptr_t)&npxs) + 1);
|
||||
|
|
@ -2787,9 +2787,9 @@ static void FP_COMPARE_D()
|
|||
addbyte(0x24);
|
||||
addbyte(0x04);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x8a); /*MOV BL, [npxs+1]*/
|
||||
addbyte(0x1d);
|
||||
addlong(((uintptr_t)&npxs) + 1);
|
||||
|
|
@ -2821,9 +2821,9 @@ static void FP_COMPARE_IW()
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x8a); /*MOV BL, [npxs+1]*/
|
||||
addbyte(0x1d);
|
||||
addlong(((uintptr_t)&npxs) + 1);
|
||||
|
|
@ -2855,9 +2855,9 @@ static void FP_COMPARE_IL()
|
|||
addbyte(0x04);
|
||||
addbyte(0x24);
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addlong((uintptr_t)ST);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x8a); /*MOV BL, [npxs+1]*/
|
||||
addbyte(0x1d);
|
||||
addlong(((uintptr_t)&npxs) + 1);
|
||||
|
|
@ -2886,8 +2886,8 @@ static void FP_OP_REG(int op, int dst, int src)
|
|||
addbyte(0x8b); /*MOV EAX, TOP*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xbe); /*MOVL ESI, ST*/
|
||||
addlong((uintptr_t)ST);
|
||||
// addbyte(0xbe); /*MOVL ESI, ST*/
|
||||
// addlong((uintptr_t)cpu_state.ST);
|
||||
addbyte(0x89); /*MOV EBX, EAX*/
|
||||
addbyte(0xc3);
|
||||
if (src || dst)
|
||||
|
|
@ -2903,36 +2903,42 @@ static void FP_OP_REG(int op, int dst, int src)
|
|||
if (src)
|
||||
{
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EBX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x1d);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(~TAG_UINT64);
|
||||
addbyte(0xdc); /*FADD ST[EAX*8]*/
|
||||
addbyte(0x04 | op);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44 | op);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdd); /*FSTP ST[EBX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0xde);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0xdd); /*FLD [ESI+EAX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0x80); /*AND tag[EAX], ~TAG_UINT64*/
|
||||
addbyte(0x64);
|
||||
addbyte(0x05);
|
||||
addbyte(cpu_state_offset(tag[0]));
|
||||
addbyte(~TAG_UINT64);
|
||||
addbyte(0xdc); /*FADD ST[EBX*8]*/
|
||||
addbyte(0x04 | op);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44 | op);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdd); /*FSTP ST[EAX*8]*/
|
||||
addbyte(0x1c);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x5c);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2941,8 +2947,8 @@ static void FP_COMPARE_REG(int dst, int src)
|
|||
addbyte(0x8b); /*MOV EAX, TOP*/
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(TOP));
|
||||
addbyte(0xbe); /*MOVL ESI, ST*/
|
||||
addlong((uintptr_t)ST);
|
||||
// addbyte(0xbe); /*MOVL ESI, ST*/
|
||||
// addlong((uintptr_t)cpu_state.ST);
|
||||
addbyte(0x89); /*MOV EBX, EAX*/
|
||||
addbyte(0xc3);
|
||||
if (src || dst)
|
||||
|
|
@ -2967,20 +2973,24 @@ static void FP_COMPARE_REG(int dst, int src)
|
|||
if (src)
|
||||
{
|
||||
addbyte(0xdd); /*FLD ST[EBX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdc); /*FCOMP ST[EAX*8]*/
|
||||
addbyte(0x04 | 0x18);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44 | 0x18);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0xdd); /*FLD [ESI+EAX*8]*/
|
||||
addbyte(0x04);
|
||||
addbyte(0xc6);
|
||||
addbyte(0x44);
|
||||
addbyte(0xc5);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
addbyte(0xdc); /*FCOMP ST[EBX*8]*/
|
||||
addbyte(0x04 | 0x18);
|
||||
addbyte(0xde);
|
||||
addbyte(0x44 | 0x18);
|
||||
addbyte(0xdd);
|
||||
addbyte(cpu_state_offset(ST));
|
||||
}
|
||||
|
||||
addbyte(0xdf); /*FSTSW AX*/
|
||||
|
|
@ -3133,8 +3143,8 @@ static int LOAD_MMX_D(int guest_reg)
|
|||
host_reg_mapping[host_reg] = 100;
|
||||
|
||||
addbyte(0x8b); /*MOV EBX, reg*/
|
||||
addbyte(0x05 | (host_reg << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
|
||||
return host_reg;
|
||||
}
|
||||
|
|
@ -3153,11 +3163,11 @@ static int LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
|
|||
}
|
||||
|
||||
addbyte(0x8b); /*MOV EBX, reg*/
|
||||
addbyte(0x05 | ((*host_reg1) << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(0x45 | ((*host_reg1) << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
addbyte(0x8b); /*MOV ECX, reg+4*/
|
||||
addbyte(0x05 | ((*host_reg2) << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[1]);
|
||||
addbyte(0x45 | ((*host_reg2) << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[1]));
|
||||
}
|
||||
static int LOAD_MMX_Q_MMX(int guest_reg)
|
||||
{
|
||||
|
|
@ -3167,8 +3177,8 @@ static int LOAD_MMX_Q_MMX(int guest_reg)
|
|||
addbyte(0xf3); /*MOVQ dst_reg,[reg]*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0x7e);
|
||||
addbyte(0x05 | (dst_reg << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].q);
|
||||
addbyte(0x45 | (dst_reg << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].q));
|
||||
|
||||
return dst_reg;
|
||||
}
|
||||
|
|
@ -3197,29 +3207,29 @@ static int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
|
|||
static void STORE_MMX_LQ(int guest_reg, int host_reg1)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL [reg],0*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&MM[guest_reg].l[1]);
|
||||
addbyte(0x45);
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[1]));
|
||||
addlong(0);
|
||||
addbyte(0x89); /*MOVL [reg],host_reg*/
|
||||
addbyte(0x05 | (host_reg1 << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(0x45 | (host_reg1 << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
}
|
||||
static void STORE_MMX_Q(int guest_reg, int host_reg1, int host_reg2)
|
||||
{
|
||||
addbyte(0x89); /*MOVL [reg],host_reg*/
|
||||
addbyte(0x05 | (host_reg1 << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[0]);
|
||||
addbyte(0x45 | (host_reg1 << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[0]));
|
||||
addbyte(0x89); /*MOVL [reg],host_reg*/
|
||||
addbyte(0x05 | (host_reg2 << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].l[1]);
|
||||
addbyte(0x45 | (host_reg2 << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].l[1]));
|
||||
}
|
||||
static void STORE_MMX_Q_MMX(int guest_reg, int host_reg)
|
||||
{
|
||||
addbyte(0x66); /*MOVQ [guest_reg],host_reg*/
|
||||
addbyte(0x0f);
|
||||
addbyte(0xd6);
|
||||
addbyte(0x05 | (host_reg << 3));
|
||||
addlong((uint32_t)&MM[guest_reg].q);
|
||||
addbyte(0x45 | (host_reg << 3));
|
||||
addbyte(cpu_state_offset(MM[guest_reg].q));
|
||||
}
|
||||
|
||||
#define MMX_x86_OP(name, opcode) \
|
||||
|
|
|
|||
|
|
@ -356,9 +356,9 @@ void codegen_block_start_recompile(codeblock_t *block)
|
|||
addbyte(0x83);
|
||||
addbyte(0xEC);
|
||||
addbyte(0x28);
|
||||
addbyte(0x48); /*MOVL EBP, &EAX*/
|
||||
addbyte(0x48); /*MOVL RBP, &cpu_state*/
|
||||
addbyte(0xBD);
|
||||
addquad((uint64_t)&EAX);
|
||||
addquad(((uintptr_t)&cpu_state) + 128);
|
||||
|
||||
// pclog("New block %i for %08X %03x\n", block_current, cs+pc, block_num);
|
||||
|
||||
|
|
|
|||
|
|
@ -333,8 +333,8 @@ void codegen_block_start_recompile(codeblock_t *block)
|
|||
addbyte(0x83); /*SUBL $16,%esp*/
|
||||
addbyte(0xEC);
|
||||
addbyte(0x10);
|
||||
addbyte(0xBD); /*MOVL EBP, &EAX*/
|
||||
addlong((uint32_t)&EAX);
|
||||
addbyte(0xBD); /*MOVL EBP, &cpu_state*/
|
||||
addlong(((uintptr_t)&cpu_state) + 128);
|
||||
|
||||
// pclog("New block %i for %08X %03x\n", block_current, cs+pc, block_num);
|
||||
|
||||
|
|
|
|||
20
src/ibm.h
20
src/ibm.h
|
|
@ -109,6 +109,18 @@ typedef struct
|
|||
int checked; /*Non-zero if selector is known to be valid*/
|
||||
} x86seg;
|
||||
|
||||
typedef union MMX_REG
|
||||
{
|
||||
uint64_t q;
|
||||
int64_t sq;
|
||||
uint32_t l[2];
|
||||
int32_t sl[2];
|
||||
uint16_t w[4];
|
||||
int16_t sw[4];
|
||||
uint8_t b[8];
|
||||
int8_t sb[8];
|
||||
} MMX_REG;
|
||||
|
||||
struct
|
||||
{
|
||||
x86reg regs[8];
|
||||
|
|
@ -143,6 +155,12 @@ struct
|
|||
|
||||
int _cycles;
|
||||
int cpu_recomp_ins;
|
||||
|
||||
double ST[8];
|
||||
|
||||
uint16_t MM_w4[8];
|
||||
|
||||
MMX_REG MM[8];
|
||||
} cpu_state;
|
||||
|
||||
#define cycles cpu_state._cycles
|
||||
|
|
@ -151,7 +169,7 @@ struct
|
|||
|
||||
COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128);
|
||||
|
||||
#define cpu_state_offset(MEMBER) ((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state)
|
||||
#define cpu_state_offset(MEMBER) ((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)
|
||||
|
||||
/*x86reg regs[8];*/
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#define MMX_GETSRC() \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
src = MM[cpu_rm]; \
|
||||
src = cpu_state.MM[cpu_rm]; \
|
||||
CLOCK_CYCLES(1); \
|
||||
} \
|
||||
else \
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@ static int opPADDB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] += src.b[0];
|
||||
MM[cpu_reg].b[1] += src.b[1];
|
||||
MM[cpu_reg].b[2] += src.b[2];
|
||||
MM[cpu_reg].b[3] += src.b[3];
|
||||
MM[cpu_reg].b[4] += src.b[4];
|
||||
MM[cpu_reg].b[5] += src.b[5];
|
||||
MM[cpu_reg].b[6] += src.b[6];
|
||||
MM[cpu_reg].b[7] += src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] += src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[1] += src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] += src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] += src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[4] += src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[5] += src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[6] += src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[7] += src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -25,14 +25,14 @@ static int opPADDB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] += src.b[0];
|
||||
MM[cpu_reg].b[1] += src.b[1];
|
||||
MM[cpu_reg].b[2] += src.b[2];
|
||||
MM[cpu_reg].b[3] += src.b[3];
|
||||
MM[cpu_reg].b[4] += src.b[4];
|
||||
MM[cpu_reg].b[5] += src.b[5];
|
||||
MM[cpu_reg].b[6] += src.b[6];
|
||||
MM[cpu_reg].b[7] += src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] += src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[1] += src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] += src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] += src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[4] += src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[5] += src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[6] += src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[7] += src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -45,10 +45,10 @@ static int opPADDW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] += src.w[0];
|
||||
MM[cpu_reg].w[1] += src.w[1];
|
||||
MM[cpu_reg].w[2] += src.w[2];
|
||||
MM[cpu_reg].w[3] += src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] += src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] += src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] += src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] += src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -60,10 +60,10 @@ static int opPADDW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] += src.w[0];
|
||||
MM[cpu_reg].w[1] += src.w[1];
|
||||
MM[cpu_reg].w[2] += src.w[2];
|
||||
MM[cpu_reg].w[3] += src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] += src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] += src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] += src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] += src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -76,8 +76,8 @@ static int opPADDD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] += src.l[0];
|
||||
MM[cpu_reg].l[1] += src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] += src.l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] += src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -89,8 +89,8 @@ static int opPADDD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] += src.l[0];
|
||||
MM[cpu_reg].l[1] += src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] += src.l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] += src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -103,14 +103,14 @@ static int opPADDSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,14 +122,14 @@ static int opPADDSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] + src.sb[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] + src.sb[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] + src.sb[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] + src.sb[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] + src.sb[4]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] + src.sb[5]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] + src.sb[6]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] + src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -142,14 +142,14 @@ static int opPADDUSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] + src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] + src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] + src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] + src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] + src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] + src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] + src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] + src.b[7]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] + src.b[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] + src.b[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] + src.b[4]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] + src.b[5]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] + src.b[6]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] + src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -161,14 +161,14 @@ static int opPADDUSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] + src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] + src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] + src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] + src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] + src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] + src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] + src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] + src.b[7]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] + src.b[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] + src.b[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] + src.b[4]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] + src.b[5]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] + src.b[6]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] + src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -181,10 +181,10 @@ static int opPADDSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -196,10 +196,10 @@ static int opPADDSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] + src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] + src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] + src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] + src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -212,10 +212,10 @@ static int opPADDUSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] + src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] + src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] + src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] + src.w[3]);
|
||||
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] + src.w[0]);
|
||||
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] + src.w[1]);
|
||||
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] + src.w[2]);
|
||||
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] + src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -227,10 +227,10 @@ static int opPADDUSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] + src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] + src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] + src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] + src.w[3]);
|
||||
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] + src.w[0]);
|
||||
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] + src.w[1]);
|
||||
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] + src.w[2]);
|
||||
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] + src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -243,15 +243,15 @@ static int opPMADDWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
if (MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[cpu_reg].l[0] = 0x80000000;
|
||||
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
|
||||
else
|
||||
MM[cpu_reg].sl[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
|
||||
if (MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[cpu_reg].l[1] = 0x80000000;
|
||||
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
|
||||
else
|
||||
MM[cpu_reg].sl[1] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -263,15 +263,15 @@ static int opPMADDWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
if (MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
MM[cpu_reg].l[0] = 0x80000000;
|
||||
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
||||
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
|
||||
else
|
||||
MM[cpu_reg].sl[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
||||
|
||||
if (MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
MM[cpu_reg].l[1] = 0x80000000;
|
||||
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
||||
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
|
||||
else
|
||||
MM[cpu_reg].sl[1] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -284,10 +284,10 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].w[0] *= MM[cpu_rm].w[0];
|
||||
MM[cpu_reg].w[1] *= MM[cpu_rm].w[1];
|
||||
MM[cpu_reg].w[2] *= MM[cpu_rm].w[2];
|
||||
MM[cpu_reg].w[3] *= MM[cpu_rm].w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] *= cpu_state.MM[cpu_rm].w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] *= cpu_state.MM[cpu_rm].w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] *= cpu_state.MM[cpu_rm].w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] *= cpu_state.MM[cpu_rm].w[3];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -296,10 +296,10 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
MM[cpu_reg].w[3] *= src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] *= src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] *= src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] *= src.w[3];
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -311,10 +311,10 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].w[0] *= MM[cpu_rm].w[0];
|
||||
MM[cpu_reg].w[1] *= MM[cpu_rm].w[1];
|
||||
MM[cpu_reg].w[2] *= MM[cpu_rm].w[2];
|
||||
MM[cpu_reg].w[3] *= MM[cpu_rm].w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] *= cpu_state.MM[cpu_rm].w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] *= cpu_state.MM[cpu_rm].w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] *= cpu_state.MM[cpu_rm].w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] *= cpu_state.MM[cpu_rm].w[3];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -323,10 +323,10 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
MM[cpu_reg].w[3] *= src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] *= src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] *= src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] *= src.w[3];
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -339,10 +339,10 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)MM[cpu_rm].sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)MM[cpu_rm].sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)MM[cpu_rm].sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)MM[cpu_rm].sw[3]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) >> 16;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -351,10 +351,10 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -366,10 +366,10 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)MM[cpu_rm].sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)MM[cpu_rm].sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)MM[cpu_rm].sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)MM[cpu_rm].sw[3]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) >> 16;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -378,10 +378,10 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
|||
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
MM[cpu_reg].w[3] = ((int32_t)MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -395,14 +395,14 @@ static int opPSUBB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] -= src.b[0];
|
||||
MM[cpu_reg].b[1] -= src.b[1];
|
||||
MM[cpu_reg].b[2] -= src.b[2];
|
||||
MM[cpu_reg].b[3] -= src.b[3];
|
||||
MM[cpu_reg].b[4] -= src.b[4];
|
||||
MM[cpu_reg].b[5] -= src.b[5];
|
||||
MM[cpu_reg].b[6] -= src.b[6];
|
||||
MM[cpu_reg].b[7] -= src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] -= src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[1] -= src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] -= src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] -= src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[4] -= src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[5] -= src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[6] -= src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[7] -= src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -414,14 +414,14 @@ static int opPSUBB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] -= src.b[0];
|
||||
MM[cpu_reg].b[1] -= src.b[1];
|
||||
MM[cpu_reg].b[2] -= src.b[2];
|
||||
MM[cpu_reg].b[3] -= src.b[3];
|
||||
MM[cpu_reg].b[4] -= src.b[4];
|
||||
MM[cpu_reg].b[5] -= src.b[5];
|
||||
MM[cpu_reg].b[6] -= src.b[6];
|
||||
MM[cpu_reg].b[7] -= src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] -= src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[1] -= src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] -= src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] -= src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[4] -= src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[5] -= src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[6] -= src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[7] -= src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -434,10 +434,10 @@ static int opPSUBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] -= src.w[0];
|
||||
MM[cpu_reg].w[1] -= src.w[1];
|
||||
MM[cpu_reg].w[2] -= src.w[2];
|
||||
MM[cpu_reg].w[3] -= src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] -= src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] -= src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] -= src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] -= src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -449,10 +449,10 @@ static int opPSUBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] -= src.w[0];
|
||||
MM[cpu_reg].w[1] -= src.w[1];
|
||||
MM[cpu_reg].w[2] -= src.w[2];
|
||||
MM[cpu_reg].w[3] -= src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] -= src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[1] -= src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] -= src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[3] -= src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -465,8 +465,8 @@ static int opPSUBD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] -= src.l[0];
|
||||
MM[cpu_reg].l[1] -= src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] -= src.l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] -= src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -478,8 +478,8 @@ static int opPSUBD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] -= src.l[0];
|
||||
MM[cpu_reg].l[1] -= src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] -= src.l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] -= src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -492,14 +492,14 @@ static int opPSUBSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -511,14 +511,14 @@ static int opPSUBSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
MM[cpu_reg].sb[5] = SSATB(MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
MM[cpu_reg].sb[6] = SSATB(MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
MM[cpu_reg].sb[7] = SSATB(MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] - src.sb[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] - src.sb[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] - src.sb[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] - src.sb[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] - src.sb[4]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] - src.sb[5]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] - src.sb[6]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] - src.sb[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -531,14 +531,14 @@ static int opPSUBUSB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] - src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] - src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] - src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] - src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] - src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] - src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] - src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] - src.b[7]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] - src.b[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] - src.b[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] - src.b[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] - src.b[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] - src.b[4]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] - src.b[5]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] - src.b[6]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] - src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -550,14 +550,14 @@ static int opPSUBUSB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(MM[cpu_reg].b[0] - src.b[0]);
|
||||
MM[cpu_reg].b[1] = USATB(MM[cpu_reg].b[1] - src.b[1]);
|
||||
MM[cpu_reg].b[2] = USATB(MM[cpu_reg].b[2] - src.b[2]);
|
||||
MM[cpu_reg].b[3] = USATB(MM[cpu_reg].b[3] - src.b[3]);
|
||||
MM[cpu_reg].b[4] = USATB(MM[cpu_reg].b[4] - src.b[4]);
|
||||
MM[cpu_reg].b[5] = USATB(MM[cpu_reg].b[5] - src.b[5]);
|
||||
MM[cpu_reg].b[6] = USATB(MM[cpu_reg].b[6] - src.b[6]);
|
||||
MM[cpu_reg].b[7] = USATB(MM[cpu_reg].b[7] - src.b[7]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] - src.b[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] - src.b[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] - src.b[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] - src.b[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] - src.b[4]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] - src.b[5]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] - src.b[6]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] - src.b[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -570,10 +570,10 @@ static int opPSUBSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -585,10 +585,10 @@ static int opPSUBSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
MM[cpu_reg].sw[3] = SSATW(MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] - src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] - src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] - src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] - src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -601,10 +601,10 @@ static int opPSUBUSW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] - src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] - src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] - src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] - src.w[3]);
|
||||
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] - src.w[0]);
|
||||
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] - src.w[1]);
|
||||
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] - src.w[2]);
|
||||
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] - src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -616,10 +616,10 @@ static int opPSUBUSW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = USATW(MM[cpu_reg].w[0] - src.w[0]);
|
||||
MM[cpu_reg].w[1] = USATW(MM[cpu_reg].w[1] - src.w[1]);
|
||||
MM[cpu_reg].w[2] = USATW(MM[cpu_reg].w[2] - src.w[2]);
|
||||
MM[cpu_reg].w[3] = USATW(MM[cpu_reg].w[3] - src.w[3]);
|
||||
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] - src.w[0]);
|
||||
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] - src.w[1]);
|
||||
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] - src.w[2]);
|
||||
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] - src.w[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,14 +7,14 @@ static int opPCMPEQB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[2] = (cpu_state.MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[3] = (cpu_state.MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[4] = (cpu_state.MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[5] = (cpu_state.MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[6] = (cpu_state.MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[7] = (cpu_state.MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -27,14 +27,14 @@ static int opPCMPEQB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[2] = (cpu_state.MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[3] = (cpu_state.MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[4] = (cpu_state.MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[5] = (cpu_state.MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[6] = (cpu_state.MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[7] = (cpu_state.MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -48,14 +48,14 @@ static int opPCMPGTB_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[2] = (cpu_state.MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[3] = (cpu_state.MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[4] = (cpu_state.MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[5] = (cpu_state.MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[6] = (cpu_state.MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[7] = (cpu_state.MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -68,14 +68,14 @@ static int opPCMPGTB_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = (MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[1] = (MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[2] = (MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[3] = (MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[4] = (MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[5] = (MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[6] = (MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
MM[cpu_reg].b[7] = (MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].sb[0] > src.sb[0]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].sb[1] > src.sb[1]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[2] = (cpu_state.MM[cpu_reg].sb[2] > src.sb[2]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[3] = (cpu_state.MM[cpu_reg].sb[3] > src.sb[3]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[4] = (cpu_state.MM[cpu_reg].sb[4] > src.sb[4]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[5] = (cpu_state.MM[cpu_reg].sb[5] > src.sb[5]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[6] = (cpu_state.MM[cpu_reg].sb[6] > src.sb[6]) ? 0xff : 0;
|
||||
cpu_state.MM[cpu_reg].b[7] = (cpu_state.MM[cpu_reg].sb[7] > src.sb[7]) ? 0xff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -89,10 +89,10 @@ static int opPCMPEQW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = (cpu_state.MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[1] = (cpu_state.MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[2] = (cpu_state.MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[3] = (cpu_state.MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -105,10 +105,10 @@ static int opPCMPEQW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = (cpu_state.MM[cpu_reg].w[0] == src.w[0]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[1] = (cpu_state.MM[cpu_reg].w[1] == src.w[1]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[2] = (cpu_state.MM[cpu_reg].w[2] == src.w[2]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[3] = (cpu_state.MM[cpu_reg].w[3] == src.w[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,10 +122,10 @@ static int opPCMPGTW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = (cpu_state.MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[1] = (cpu_state.MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[2] = (cpu_state.MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[3] = (cpu_state.MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -138,10 +138,10 @@ static int opPCMPGTW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = (MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[1] = (MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[2] = (MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
MM[cpu_reg].w[3] = (MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[0] = (cpu_state.MM[cpu_reg].sw[0] > src.sw[0]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[1] = (cpu_state.MM[cpu_reg].sw[1] > src.sw[1]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[2] = (cpu_state.MM[cpu_reg].sw[2] > src.sw[2]) ? 0xffff : 0;
|
||||
cpu_state.MM[cpu_reg].w[3] = (cpu_state.MM[cpu_reg].sw[3] > src.sw[3]) ? 0xffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -155,8 +155,8 @@ static int opPCMPEQD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = (cpu_state.MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = (cpu_state.MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -169,8 +169,8 @@ static int opPCMPEQD_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = (cpu_state.MM[cpu_reg].l[0] == src.l[0]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = (cpu_state.MM[cpu_reg].l[1] == src.l[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -184,8 +184,8 @@ static int opPCMPGTD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = (cpu_state.MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = (cpu_state.MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -198,8 +198,8 @@ static int opPCMPGTD_a32(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = (MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
MM[cpu_reg].l[1] = (MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = (cpu_state.MM[cpu_reg].sl[0] > src.sl[0]) ? 0xffffffff : 0;
|
||||
cpu_state.MM[cpu_reg].l[1] = (cpu_state.MM[cpu_reg].sl[1] > src.sl[1]) ? 0xffffffff : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ static int opPAND_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q &= src.q;
|
||||
cpu_state.MM[cpu_reg].q &= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPAND_a32(uint32_t fetchdat)
|
||||
|
|
@ -17,7 +17,7 @@ static int opPAND_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q &= src.q;
|
||||
cpu_state.MM[cpu_reg].q &= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ static int opPANDN_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q = ~MM[cpu_reg].q & src.q;
|
||||
cpu_state.MM[cpu_reg].q = ~cpu_state.MM[cpu_reg].q & src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPANDN_a32(uint32_t fetchdat)
|
||||
|
|
@ -40,7 +40,7 @@ static int opPANDN_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q = ~MM[cpu_reg].q & src.q;
|
||||
cpu_state.MM[cpu_reg].q = ~cpu_state.MM[cpu_reg].q & src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static int opPOR_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q |= src.q;
|
||||
cpu_state.MM[cpu_reg].q |= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPOR_a32(uint32_t fetchdat)
|
||||
|
|
@ -63,7 +63,7 @@ static int opPOR_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q |= src.q;
|
||||
cpu_state.MM[cpu_reg].q |= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -75,7 +75,7 @@ static int opPXOR_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q ^= src.q;
|
||||
cpu_state.MM[cpu_reg].q ^= src.q;
|
||||
return 0;
|
||||
}
|
||||
static int opPXOR_a32(uint32_t fetchdat)
|
||||
|
|
@ -86,6 +86,6 @@ static int opPXOR_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].q ^= src.q;
|
||||
cpu_state.MM[cpu_reg].q ^= src.q;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -14,8 +14,8 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = dst;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -28,8 +28,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -37,8 +37,8 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
|||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
cpu_state.MM[cpu_reg].l[0] = dst;
|
||||
cpu_state.MM[cpu_reg].l[1] = 0;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -52,13 +52,13 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -70,13 +70,13 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
cpu_state.regs[cpu_rm].l = MM[cpu_reg].l[0];
|
||||
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -89,7 +89,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].q = MM[cpu_rm].q;
|
||||
cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -97,7 +97,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
|||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
cpu_state.MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -109,7 +109,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].q = MM[cpu_rm].q;
|
||||
cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -117,7 +117,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
|||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
cpu_state.MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -130,13 +130,13 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_rm].q = MM[cpu_reg].q;
|
||||
cpu_state.MM[cpu_rm].q = cpu_state.MM[cpu_reg].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -148,13 +148,13 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_rm].q = MM[cpu_reg].q;
|
||||
cpu_state.MM[cpu_rm].q = cpu_state.MM[cpu_reg].q;
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].q); if (cpu_state.abrt) return 1;
|
||||
writememq(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].q); if (cpu_state.abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].l[1] = MM[cpu_rm].l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] = cpu_state.MM[cpu_rm].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -13,7 +13,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
cpu_state.MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -26,7 +26,7 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (cpu_mod == 3)
|
||||
{
|
||||
MM[cpu_reg].l[1] = MM[cpu_rm].l[0];
|
||||
cpu_state.MM[cpu_reg].l[1] = cpu_state.MM[cpu_rm].l[0];
|
||||
CLOCK_CYCLES(1);
|
||||
}
|
||||
else
|
||||
|
|
@ -34,7 +34,7 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
|||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
cpu_state.MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
|
|
@ -49,8 +49,8 @@ static int opPUNPCKHDQ_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = MM[cpu_reg].l[1];
|
||||
MM[cpu_reg].l[1] = src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1];
|
||||
cpu_state.MM[cpu_reg].l[1] = src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -62,8 +62,8 @@ static int opPUNPCKHDQ_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].l[0] = MM[cpu_reg].l[1];
|
||||
MM[cpu_reg].l[1] = src.l[1];
|
||||
cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1];
|
||||
cpu_state.MM[cpu_reg].l[1] = src.l[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -76,14 +76,14 @@ static int opPUNPCKLBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[7] = src.b[3];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[3];
|
||||
MM[cpu_reg].b[5] = src.b[2];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[2];
|
||||
MM[cpu_reg].b[3] = src.b[1];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[1];
|
||||
MM[cpu_reg].b[1] = src.b[0];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[0];
|
||||
cpu_state.MM[cpu_reg].b[7] = src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3];
|
||||
cpu_state.MM[cpu_reg].b[5] = src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] = src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1];
|
||||
cpu_state.MM[cpu_reg].b[1] = src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -95,14 +95,14 @@ static int opPUNPCKLBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[7] = src.b[3];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[3];
|
||||
MM[cpu_reg].b[5] = src.b[2];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[2];
|
||||
MM[cpu_reg].b[3] = src.b[1];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[1];
|
||||
MM[cpu_reg].b[1] = src.b[0];
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[0];
|
||||
cpu_state.MM[cpu_reg].b[7] = src.b[3];
|
||||
cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3];
|
||||
cpu_state.MM[cpu_reg].b[5] = src.b[2];
|
||||
cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2];
|
||||
cpu_state.MM[cpu_reg].b[3] = src.b[1];
|
||||
cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1];
|
||||
cpu_state.MM[cpu_reg].b[1] = src.b[0];
|
||||
cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -115,14 +115,14 @@ static int opPUNPCKHBW_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[4];
|
||||
MM[cpu_reg].b[1] = src.b[4];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[5];
|
||||
MM[cpu_reg].b[3] = src.b[5];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[6];
|
||||
MM[cpu_reg].b[5] = src.b[6];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[7];
|
||||
MM[cpu_reg].b[7] = src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[4];
|
||||
cpu_state.MM[cpu_reg].b[1] = src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[5];
|
||||
cpu_state.MM[cpu_reg].b[3] = src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[6];
|
||||
cpu_state.MM[cpu_reg].b[5] = src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[7];
|
||||
cpu_state.MM[cpu_reg].b[7] = src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -134,14 +134,14 @@ static int opPUNPCKHBW_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].b[0] = MM[cpu_reg].b[4];
|
||||
MM[cpu_reg].b[1] = src.b[4];
|
||||
MM[cpu_reg].b[2] = MM[cpu_reg].b[5];
|
||||
MM[cpu_reg].b[3] = src.b[5];
|
||||
MM[cpu_reg].b[4] = MM[cpu_reg].b[6];
|
||||
MM[cpu_reg].b[5] = src.b[6];
|
||||
MM[cpu_reg].b[6] = MM[cpu_reg].b[7];
|
||||
MM[cpu_reg].b[7] = src.b[7];
|
||||
cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[4];
|
||||
cpu_state.MM[cpu_reg].b[1] = src.b[4];
|
||||
cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[5];
|
||||
cpu_state.MM[cpu_reg].b[3] = src.b[5];
|
||||
cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[6];
|
||||
cpu_state.MM[cpu_reg].b[5] = src.b[6];
|
||||
cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[7];
|
||||
cpu_state.MM[cpu_reg].b[7] = src.b[7];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -154,10 +154,10 @@ static int opPUNPCKLWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[3] = src.w[1];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[1];
|
||||
MM[cpu_reg].w[1] = src.w[0];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[0];
|
||||
cpu_state.MM[cpu_reg].w[3] = src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[1];
|
||||
cpu_state.MM[cpu_reg].w[1] = src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -169,10 +169,10 @@ static int opPUNPCKLWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[3] = src.w[1];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[1];
|
||||
MM[cpu_reg].w[1] = src.w[0];
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[0];
|
||||
cpu_state.MM[cpu_reg].w[3] = src.w[1];
|
||||
cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[1];
|
||||
cpu_state.MM[cpu_reg].w[1] = src.w[0];
|
||||
cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -185,10 +185,10 @@ static int opPUNPCKHWD_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[2];
|
||||
MM[cpu_reg].w[1] = src.w[2];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[3];
|
||||
MM[cpu_reg].w[3] = src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[2];
|
||||
cpu_state.MM[cpu_reg].w[1] = src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[3];
|
||||
cpu_state.MM[cpu_reg].w[3] = src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -200,10 +200,10 @@ static int opPUNPCKHWD_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
|
||||
MM[cpu_reg].w[0] = MM[cpu_reg].w[2];
|
||||
MM[cpu_reg].w[1] = src.w[2];
|
||||
MM[cpu_reg].w[2] = MM[cpu_reg].w[3];
|
||||
MM[cpu_reg].w[3] = src.w[3];
|
||||
cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[2];
|
||||
cpu_state.MM[cpu_reg].w[1] = src.w[2];
|
||||
cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[3];
|
||||
cpu_state.MM[cpu_reg].w[3] = src.w[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -215,16 +215,16 @@ static int opPACKSSWB_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -235,16 +235,16 @@ static int opPACKSSWB_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sb[0] = SSATB(dst.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sb[1] = SSATB(dst.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sb[2] = SSATB(dst.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sb[3] = SSATB(dst.sw[3]);
|
||||
cpu_state.MM[cpu_reg].sb[4] = SSATB(src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].sb[5] = SSATB(src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].sb[6] = SSATB(src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].sb[7] = SSATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -256,16 +256,16 @@ static int opPACKUSWB_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -276,16 +276,16 @@ static int opPACKUSWB_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
cpu_state.MM[cpu_reg].b[0] = USATB(dst.sw[0]);
|
||||
cpu_state.MM[cpu_reg].b[1] = USATB(dst.sw[1]);
|
||||
cpu_state.MM[cpu_reg].b[2] = USATB(dst.sw[2]);
|
||||
cpu_state.MM[cpu_reg].b[3] = USATB(dst.sw[3]);
|
||||
cpu_state.MM[cpu_reg].b[4] = USATB(src.sw[0]);
|
||||
cpu_state.MM[cpu_reg].b[5] = USATB(src.sw[1]);
|
||||
cpu_state.MM[cpu_reg].b[6] = USATB(src.sw[2]);
|
||||
cpu_state.MM[cpu_reg].b[7] = USATB(src.sw[3]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -297,12 +297,12 @@ static int opPACKSSDW_a16(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_16(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -313,12 +313,12 @@ static int opPACKSSDW_a32(uint32_t fetchdat)
|
|||
|
||||
fetch_ea_32(fetchdat);
|
||||
MMX_GETSRC();
|
||||
dst = MM[cpu_reg];
|
||||
dst = cpu_state.MM[cpu_reg];
|
||||
|
||||
MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
cpu_state.MM[cpu_reg].sw[0] = SSATW(dst.sl[0]);
|
||||
cpu_state.MM[cpu_reg].sw[1] = SSATW(dst.sl[1]);
|
||||
cpu_state.MM[cpu_reg].sw[2] = SSATW(src.sl[0]);
|
||||
cpu_state.MM[cpu_reg].sw[3] = SSATW(src.sl[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#define MMX_GETSHIFT() \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
shift = MM[cpu_rm].b[0]; \
|
||||
shift = cpu_state.MM[cpu_rm].b[0]; \
|
||||
CLOCK_CYCLES(1); \
|
||||
} \
|
||||
else \
|
||||
|
|
@ -23,32 +23,32 @@ static int opPSxxW_imm(uint32_t fetchdat)
|
|||
{
|
||||
case 0x10: /*PSRLW*/
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] >>= shift;
|
||||
MM[reg].w[1] >>= shift;
|
||||
MM[reg].w[2] >>= shift;
|
||||
MM[reg].w[3] >>= shift;
|
||||
cpu_state.MM[reg].w[0] >>= shift;
|
||||
cpu_state.MM[reg].w[1] >>= shift;
|
||||
cpu_state.MM[reg].w[2] >>= shift;
|
||||
cpu_state.MM[reg].w[3] >>= shift;
|
||||
}
|
||||
break;
|
||||
case 0x20: /*PSRAW*/
|
||||
if (shift > 15)
|
||||
shift = 15;
|
||||
MM[reg].sw[0] >>= shift;
|
||||
MM[reg].sw[1] >>= shift;
|
||||
MM[reg].sw[2] >>= shift;
|
||||
MM[reg].sw[3] >>= shift;
|
||||
cpu_state.MM[reg].sw[0] >>= shift;
|
||||
cpu_state.MM[reg].sw[1] >>= shift;
|
||||
cpu_state.MM[reg].sw[2] >>= shift;
|
||||
cpu_state.MM[reg].sw[3] >>= shift;
|
||||
break;
|
||||
case 0x30: /*PSLLW*/
|
||||
if (shift > 15)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].w[0] <<= shift;
|
||||
MM[reg].w[1] <<= shift;
|
||||
MM[reg].w[2] <<= shift;
|
||||
MM[reg].w[3] <<= shift;
|
||||
cpu_state.MM[reg].w[0] <<= shift;
|
||||
cpu_state.MM[reg].w[1] <<= shift;
|
||||
cpu_state.MM[reg].w[2] <<= shift;
|
||||
cpu_state.MM[reg].w[3] <<= shift;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -72,13 +72,13 @@ static int opPSLLW_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].w[0] <<= shift;
|
||||
MM[cpu_reg].w[1] <<= shift;
|
||||
MM[cpu_reg].w[2] <<= shift;
|
||||
MM[cpu_reg].w[3] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[0] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[1] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[2] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[3] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -93,13 +93,13 @@ static int opPSLLW_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].w[0] <<= shift;
|
||||
MM[cpu_reg].w[1] <<= shift;
|
||||
MM[cpu_reg].w[2] <<= shift;
|
||||
MM[cpu_reg].w[3] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[0] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[1] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[2] <<= shift;
|
||||
cpu_state.MM[cpu_reg].w[3] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -115,13 +115,13 @@ static int opPSRLW_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].w[0] >>= shift;
|
||||
MM[cpu_reg].w[1] >>= shift;
|
||||
MM[cpu_reg].w[2] >>= shift;
|
||||
MM[cpu_reg].w[3] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[2] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[3] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -136,13 +136,13 @@ static int opPSRLW_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 15)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].w[0] >>= shift;
|
||||
MM[cpu_reg].w[1] >>= shift;
|
||||
MM[cpu_reg].w[2] >>= shift;
|
||||
MM[cpu_reg].w[3] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[2] >>= shift;
|
||||
cpu_state.MM[cpu_reg].w[3] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -160,10 +160,10 @@ static int opPSRAW_a16(uint32_t fetchdat)
|
|||
if (shift > 15)
|
||||
shift = 15;
|
||||
|
||||
MM[cpu_reg].sw[0] >>= shift;
|
||||
MM[cpu_reg].sw[1] >>= shift;
|
||||
MM[cpu_reg].sw[2] >>= shift;
|
||||
MM[cpu_reg].sw[3] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[2] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[3] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -179,10 +179,10 @@ static int opPSRAW_a32(uint32_t fetchdat)
|
|||
if (shift > 15)
|
||||
shift = 15;
|
||||
|
||||
MM[cpu_reg].sw[0] >>= shift;
|
||||
MM[cpu_reg].sw[1] >>= shift;
|
||||
MM[cpu_reg].sw[2] >>= shift;
|
||||
MM[cpu_reg].sw[3] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[2] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sw[3] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -200,26 +200,26 @@ static int opPSxxD_imm(uint32_t fetchdat)
|
|||
{
|
||||
case 0x10: /*PSRLD*/
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] >>= shift;
|
||||
MM[reg].l[1] >>= shift;
|
||||
cpu_state.MM[reg].l[0] >>= shift;
|
||||
cpu_state.MM[reg].l[1] >>= shift;
|
||||
}
|
||||
break;
|
||||
case 0x20: /*PSRAD*/
|
||||
if (shift > 31)
|
||||
shift = 31;
|
||||
MM[reg].sl[0] >>= shift;
|
||||
MM[reg].sl[1] >>= shift;
|
||||
cpu_state.MM[reg].sl[0] >>= shift;
|
||||
cpu_state.MM[reg].sl[1] >>= shift;
|
||||
break;
|
||||
case 0x30: /*PSLLD*/
|
||||
if (shift > 31)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[reg].l[0] <<= shift;
|
||||
MM[reg].l[1] <<= shift;
|
||||
cpu_state.MM[reg].l[0] <<= shift;
|
||||
cpu_state.MM[reg].l[1] <<= shift;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -243,11 +243,11 @@ static int opPSLLD_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].l[0] <<= shift;
|
||||
MM[cpu_reg].l[1] <<= shift;
|
||||
cpu_state.MM[cpu_reg].l[0] <<= shift;
|
||||
cpu_state.MM[cpu_reg].l[1] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -262,11 +262,11 @@ static int opPSLLD_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].l[0] <<= shift;
|
||||
MM[cpu_reg].l[1] <<= shift;
|
||||
cpu_state.MM[cpu_reg].l[0] <<= shift;
|
||||
cpu_state.MM[cpu_reg].l[1] <<= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -282,11 +282,11 @@ static int opPSRLD_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].l[0] >>= shift;
|
||||
MM[cpu_reg].l[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].l[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].l[1] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -301,11 +301,11 @@ static int opPSRLD_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 31)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
{
|
||||
MM[cpu_reg].l[0] >>= shift;
|
||||
MM[cpu_reg].l[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].l[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].l[1] >>= shift;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -323,8 +323,8 @@ static int opPSRAD_a16(uint32_t fetchdat)
|
|||
if (shift > 31)
|
||||
shift = 31;
|
||||
|
||||
MM[cpu_reg].sl[0] >>= shift;
|
||||
MM[cpu_reg].sl[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sl[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sl[1] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -340,8 +340,8 @@ static int opPSRAD_a32(uint32_t fetchdat)
|
|||
if (shift > 31)
|
||||
shift = 31;
|
||||
|
||||
MM[cpu_reg].sl[0] >>= shift;
|
||||
MM[cpu_reg].sl[1] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sl[0] >>= shift;
|
||||
cpu_state.MM[cpu_reg].sl[1] >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -359,20 +359,20 @@ static int opPSxxQ_imm(uint32_t fetchdat)
|
|||
{
|
||||
case 0x10: /*PSRLW*/
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
MM[reg].q >>= shift;
|
||||
cpu_state.MM[reg].q >>= shift;
|
||||
break;
|
||||
case 0x20: /*PSRAW*/
|
||||
if (shift > 63)
|
||||
shift = 63;
|
||||
MM[reg].sq >>= shift;
|
||||
cpu_state.MM[reg].sq >>= shift;
|
||||
break;
|
||||
case 0x30: /*PSLLW*/
|
||||
if (shift > 63)
|
||||
MM[reg].q = 0;
|
||||
cpu_state.MM[reg].q = 0;
|
||||
else
|
||||
MM[reg].q <<= shift;
|
||||
cpu_state.MM[reg].q <<= shift;
|
||||
break;
|
||||
default:
|
||||
pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
|
||||
|
|
@ -395,9 +395,9 @@ static int opPSLLQ_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[cpu_reg].q <<= shift;
|
||||
cpu_state.MM[cpu_reg].q <<= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -411,9 +411,9 @@ static int opPSLLQ_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[cpu_reg].q <<= shift;
|
||||
cpu_state.MM[cpu_reg].q <<= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -428,9 +428,9 @@ static int opPSRLQ_a16(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[cpu_reg].q >>= shift;
|
||||
cpu_state.MM[cpu_reg].q >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -444,9 +444,9 @@ static int opPSRLQ_a32(uint32_t fetchdat)
|
|||
MMX_GETSHIFT();
|
||||
|
||||
if (shift > 63)
|
||||
MM[cpu_reg].q = 0;
|
||||
cpu_state.MM[cpu_reg].q = 0;
|
||||
else
|
||||
MM[cpu_reg].q >>= shift;
|
||||
cpu_state.MM[cpu_reg].q >>= shift;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
18
src/x87.c
18
src/x87.c
|
|
@ -19,8 +19,6 @@
|
|||
#include "x87.h"
|
||||
#include "386_common.h"
|
||||
|
||||
double ST[8];
|
||||
MMX_REG MM[8];
|
||||
uint16_t npxs,npxc;
|
||||
|
||||
uint16_t x87_gettag()
|
||||
|
|
@ -55,13 +53,13 @@ void x87_dumpregs()
|
|||
{
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
pclog("MM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\n", MM[0].q, MM[1].q, MM[2].q, MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", MM[4].q, MM[5].q, MM[6].q, MM[7].q);
|
||||
pclog("MM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\n", cpu_state.MM[0].q, cpu_state.MM[1].q, cpu_state.MM[2].q, cpu_state.MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", cpu_state.MM[4].q, cpu_state.MM[5].q, cpu_state.MM[6].q, cpu_state.MM[7].q);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("ST(0)=%f\tST(1)=%f\tST(2)=%f\tST(3)=%f\t\n",ST[cpu_state.TOP],ST[(cpu_state.TOP+1)&7],ST[(cpu_state.TOP+2)&7],ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\t\n",ST[(cpu_state.TOP+4)&7],ST[(cpu_state.TOP+5)&7],ST[(cpu_state.TOP+6)&7],ST[(cpu_state.TOP+7)&7]);
|
||||
pclog("ST(0)=%f\tST(1)=%f\tST(2)=%f\tST(3)=%f\t\n",cpu_state.ST[cpu_state.TOP],cpu_state.ST[(cpu_state.TOP+1)&7],cpu_state.ST[(cpu_state.TOP+2)&7],cpu_state.ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\t\n",cpu_state.ST[(cpu_state.TOP+4)&7],cpu_state.ST[(cpu_state.TOP+5)&7],cpu_state.ST[(cpu_state.TOP+6)&7],cpu_state.ST[(cpu_state.TOP+7)&7]);
|
||||
}
|
||||
pclog("Status = %04X Control = %04X Tag = %04X\n",npxs,npxc,x87_gettag());
|
||||
}
|
||||
|
|
@ -70,13 +68,13 @@ void x87_print()
|
|||
{
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
pclog("\tMM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\t", MM[0].q, MM[1].q, MM[2].q, MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", MM[4].q, MM[5].q, MM[6].q, MM[7].q);
|
||||
pclog("\tMM0=%016llX\tMM1=%016llX\tMM2=%016llX\tMM3=%016llX\t", cpu_state.MM[0].q, cpu_state.MM[1].q, cpu_state.MM[2].q, cpu_state.MM[3].q);
|
||||
pclog("MM4=%016llX\tMM5=%016llX\tMM6=%016llX\tMM7=%016llX\n", cpu_state.MM[4].q, cpu_state.MM[5].q, cpu_state.MM[6].q, cpu_state.MM[7].q);
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("\tST(0)=%.20f\tST(1)=%.20f\tST(2)=%f\tST(3)=%f\t",ST[cpu_state.TOP&7],ST[(cpu_state.TOP+1)&7],ST[(cpu_state.TOP+2)&7],ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\tTOP=%i CR=%04X SR=%04X TAG=%04X\n",ST[(cpu_state.TOP+4)&7],ST[(cpu_state.TOP+5)&7],ST[(cpu_state.TOP+6)&7],ST[(cpu_state.TOP+7)&7], cpu_state.TOP, npxc, npxs, x87_gettag());
|
||||
pclog("\tST(0)=%.20f\tST(1)=%.20f\tST(2)=%f\tST(3)=%f\t",cpu_state.ST[cpu_state.TOP&7],cpu_state.ST[(cpu_state.TOP+1)&7],cpu_state.ST[(cpu_state.TOP+2)&7],cpu_state.ST[(cpu_state.TOP+3)&7]);
|
||||
pclog("ST(4)=%f\tST(5)=%f\tST(6)=%f\tST(7)=%f\tTOP=%i CR=%04X SR=%04X TAG=%04X\n",cpu_state.ST[(cpu_state.TOP+4)&7],cpu_state.ST[(cpu_state.TOP+5)&7],cpu_state.ST[(cpu_state.TOP+6)&7],cpu_state.ST[(cpu_state.TOP+7)&7], cpu_state.TOP, npxc, npxs, x87_gettag());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
17
src/x87.h
17
src/x87.h
|
|
@ -1,21 +1,6 @@
|
|||
uint32_t x87_pc_off,x87_op_off;
|
||||
uint16_t x87_pc_seg,x87_op_seg;
|
||||
extern uint16_t npxs, npxc;
|
||||
extern double ST[8];
|
||||
|
||||
typedef union MMX_REG
|
||||
{
|
||||
uint64_t q;
|
||||
int64_t sq;
|
||||
uint32_t l[2];
|
||||
int32_t sl[2];
|
||||
uint16_t w[5];
|
||||
int16_t sw[4];
|
||||
uint8_t b[8];
|
||||
int8_t sb[8];
|
||||
} MMX_REG;
|
||||
|
||||
extern MMX_REG MM[8];
|
||||
|
||||
static inline void x87_set_mmx();
|
||||
static inline void x87_emms();
|
||||
|
|
@ -23,5 +8,5 @@ static inline void x87_emms();
|
|||
uint16_t x87_gettag();
|
||||
void x87_settag(uint16_t new_tag);
|
||||
|
||||
/*Hack for FPU copy. If set then ST_i64 contains the 64-bit integer loaded by FILD*/
|
||||
/*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
|
||||
#define TAG_UINT64 (1 << 2)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZERO};
|
||||
|
||||
#define ST(x) ST[((cpu_state.TOP+(x))&7)]
|
||||
#define ST(x) cpu_state.ST[((cpu_state.TOP+(x))&7)]
|
||||
|
||||
#define C0 (1<<8)
|
||||
#define C1 (1<<9)
|
||||
|
|
@ -52,13 +52,13 @@ static inline void x87_checkexceptions()
|
|||
static inline void x87_push(double i)
|
||||
{
|
||||
cpu_state.TOP=(cpu_state.TOP-1)&7;
|
||||
ST[cpu_state.TOP]=i;
|
||||
cpu_state.ST[cpu_state.TOP] = i;
|
||||
cpu_state.tag[cpu_state.TOP&7] = (i == 0.0) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline double x87_pop()
|
||||
{
|
||||
double t=ST[cpu_state.TOP];
|
||||
double t = cpu_state.ST[cpu_state.TOP];
|
||||
cpu_state.tag[cpu_state.TOP&7] = 3;
|
||||
cpu_state.TOP=(cpu_state.TOP+1)&7;
|
||||
return t;
|
||||
|
|
@ -167,12 +167,12 @@ static inline void x87_st_fsave(int reg)
|
|||
|
||||
if (cpu_state.tag[reg] & TAG_UINT64)
|
||||
{
|
||||
writememl(easeg, cpu_state.eaaddr, MM[reg].q & 0xffffffff);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, MM[reg].q >> 32);
|
||||
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[reg].q & 0xffffffff);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, cpu_state.MM[reg].q >> 32);
|
||||
writememw(easeg, cpu_state.eaaddr + 8, 0x5555);
|
||||
}
|
||||
else
|
||||
x87_st80(ST[reg]);
|
||||
x87_st80(cpu_state.ST[reg]);
|
||||
}
|
||||
|
||||
static inline void x87_ld_frstor(int reg)
|
||||
|
|
@ -186,19 +186,19 @@ static inline void x87_ld_frstor(int reg)
|
|||
if (temp == 0x5555 && cpu_state.tag[reg] == 2)
|
||||
{
|
||||
cpu_state.tag[reg] = TAG_UINT64;
|
||||
MM[reg].q = readmeml(easeg, cpu_state.eaaddr);
|
||||
MM[reg].q |= ((uint64_t)readmeml(easeg, cpu_state.eaaddr + 4) << 32);
|
||||
ST[reg] = (double)MM[reg].q;
|
||||
cpu_state.MM[reg].q = readmeml(easeg, cpu_state.eaaddr);
|
||||
cpu_state.MM[reg].q |= ((uint64_t)readmeml(easeg, cpu_state.eaaddr + 4) << 32);
|
||||
cpu_state.ST[reg] = (double)cpu_state.MM[reg].q;
|
||||
}
|
||||
else
|
||||
ST[reg] = x87_ld80();
|
||||
cpu_state.ST[reg] = x87_ld80();
|
||||
}
|
||||
|
||||
static inline void x87_ldmmx(MMX_REG *r)
|
||||
static inline void x87_ldmmx(MMX_REG *r, uint16_t *w4)
|
||||
{
|
||||
r->l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
r->l[1] = readmeml(easeg, cpu_state.eaaddr + 4);
|
||||
r->w[4] = readmemw(easeg, cpu_state.eaaddr + 8);
|
||||
*w4 = readmemw(easeg, cpu_state.eaaddr + 8);
|
||||
}
|
||||
|
||||
static inline void x87_stmmx(MMX_REG r)
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ static int opFILDiq_a16(uint32_t fetchdat)
|
|||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
|
||||
|
||||
CLOCK_CYCLES(10);
|
||||
|
|
@ -103,7 +103,7 @@ static int opFILDiq_a32(uint32_t fetchdat)
|
|||
temp64 = geteaq(); if (cpu_state.abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.MM[cpu_state.TOP].q = temp64;
|
||||
cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;
|
||||
|
||||
CLOCK_CYCLES(10);
|
||||
|
|
@ -170,7 +170,7 @@ static int FISTPiq_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = MM[cpu_state.TOP].q;
|
||||
temp64 = cpu_state.MM[cpu_state.TOP].q;
|
||||
else
|
||||
temp64 = x87_fround(ST(0));
|
||||
seteaq(temp64); if (cpu_state.abrt) return 1;
|
||||
|
|
@ -185,7 +185,7 @@ static int FISTPiq_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
|
||||
temp64 = MM[cpu_state.TOP].q;
|
||||
temp64 = cpu_state.MM[cpu_state.TOP].q;
|
||||
else
|
||||
temp64 = x87_fround(ST(0));
|
||||
seteaq(temp64); if (cpu_state.abrt) return 1;
|
||||
|
|
|
|||
|
|
@ -99,20 +99,20 @@ static int FSTOR()
|
|||
cpu_state.eaaddr += 28;
|
||||
break;
|
||||
}
|
||||
x87_ldmmx(&MM[0]); x87_ld_frstor(0); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[1]); x87_ld_frstor(1); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[2]); x87_ld_frstor(2); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[3]); x87_ld_frstor(3); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[4]); x87_ld_frstor(4); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[5]); x87_ld_frstor(5); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[6]); x87_ld_frstor(6); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[7]); x87_ld_frstor(7);
|
||||
x87_ldmmx(&cpu_state.MM[0], &cpu_state.MM_w4[0]); x87_ld_frstor(0); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[1], &cpu_state.MM_w4[1]); x87_ld_frstor(1); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[2], &cpu_state.MM_w4[2]); x87_ld_frstor(2); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[3], &cpu_state.MM_w4[3]); x87_ld_frstor(3); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[4], &cpu_state.MM_w4[4]); x87_ld_frstor(4); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[5], &cpu_state.MM_w4[5]); x87_ld_frstor(5); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[6], &cpu_state.MM_w4[6]); x87_ld_frstor(6); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&cpu_state.MM[7], &cpu_state.MM_w4[7]); x87_ld_frstor(7);
|
||||
|
||||
cpu_state.ismmx = 0;
|
||||
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
|
||||
something like this is needed*/
|
||||
if (MM[0].w[4] == 0xffff && MM[1].w[4] == 0xffff && MM[2].w[4] == 0xffff && MM[3].w[4] == 0xffff &&
|
||||
MM[4].w[4] == 0xffff && MM[5].w[4] == 0xffff && MM[6].w[4] == 0xffff && MM[7].w[4] == 0xffff &&
|
||||
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
|
||||
cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
|
||||
!cpu_state.TOP && !(*(uint64_t *)cpu_state.tag))
|
||||
cpu_state.ismmx = 1;
|
||||
|
||||
|
|
@ -152,14 +152,14 @@ static int FSAVE()
|
|||
cpu_state.eaaddr+=14;
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -184,14 +184,14 @@ static int FSAVE()
|
|||
cpu_state.eaaddr+=14;
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -215,14 +215,14 @@ static int FSAVE()
|
|||
cpu_state.eaaddr+=28;
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -247,14 +247,14 @@ static int FSAVE()
|
|||
cpu_state.eaaddr+=28;
|
||||
if (cpu_state.ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
x87_stmmx(cpu_state.MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(cpu_state.MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -316,10 +316,10 @@ static int opFLD(uint32_t fetchdat)
|
|||
cpu_state.pc++;
|
||||
if (fplog) pclog("FLD %f\n", ST(fetchdat & 7));
|
||||
old_tag = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
|
||||
old_i64 = MM[(cpu_state.TOP + fetchdat) & 7].q;
|
||||
old_i64 = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;
|
||||
x87_push(ST(fetchdat&7));
|
||||
cpu_state.tag[cpu_state.TOP] = old_tag;
|
||||
MM[cpu_state.TOP].q = old_i64;
|
||||
cpu_state.MM[cpu_state.TOP].q = old_i64;
|
||||
CLOCK_CYCLES(4);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -338,9 +338,9 @@ static int opFXCH(uint32_t fetchdat)
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old_tag = cpu_state.tag[cpu_state.TOP];
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cpu_state.tag[cpu_state.TOP] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7];
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cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = old_tag;
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old_i64 = MM[cpu_state.TOP].q;
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||||
MM[cpu_state.TOP].q = MM[(cpu_state.TOP + fetchdat) & 7].q;
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MM[(cpu_state.TOP + fetchdat) & 7].q = old_i64;
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||||
old_i64 = cpu_state.MM[cpu_state.TOP].q;
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cpu_state.MM[cpu_state.TOP].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;
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||||
cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q = old_i64;
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CLOCK_CYCLES(4);
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return 0;
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@ -808,7 +808,7 @@ static int opFSTCW_a32(uint32_t fetchdat)
|
|||
if (cond_ ## condition) \
|
||||
{ \
|
||||
cpu_state.tag[cpu_state.TOP] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7]; \
|
||||
MM[cpu_state.TOP].q = MM[(cpu_state.TOP + fetchdat) & 7].q; \
|
||||
cpu_state.MM[cpu_state.TOP].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q; \
|
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ST(0) = ST(fetchdat & 7); \
|
||||
} \
|
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CLOCK_CYCLES(4); \
|
||||
|
|
|
|||
Loading…
Reference in a new issue