Cycle counts for recompiled blocks now generated at compile time.
This commit is contained in:
TomW
parent
087f412d3f
commit
2905c43db8
43 changed files with 1142 additions and 730 deletions
|
|
@ -16,7 +16,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR b,CL*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -30,51 +30,51 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL b,CL*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 1 : 0; \
|
||||
temp2 = temp & 0x80; \
|
||||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR b,CL*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 0x80 : 0; \
|
||||
temp2 = temp & 1; \
|
||||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteab(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL b,CL*/ \
|
||||
seteab(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
|
||||
if ((temp << (c - 1)) & 0x80) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR b,CL*/ \
|
||||
seteab(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
|
||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR b,CL*/ \
|
||||
tempc = ((temp >> (c - 1)) & 1); \
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
seteab(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -110,7 +110,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR w, c*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -124,51 +124,51 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL w, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 1 : 0; \
|
||||
temp2 = temp & 0x8000; \
|
||||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR w, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 0x8000 : 0; \
|
||||
temp2 = temp & 1; \
|
||||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteaw(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL w, c*/ \
|
||||
seteaw(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
|
||||
if ((temp << (c - 1)) & 0x8000) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR w, c*/ \
|
||||
seteaw(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
|
||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR w, c*/ \
|
||||
tempc = ((temp >> (c - 1)) & 1); \
|
||||
|
|
@ -181,7 +181,7 @@
|
|||
seteaw(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -204,7 +204,7 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR l, c*/ \
|
||||
while (c > 0) \
|
||||
|
|
@ -218,51 +218,51 @@
|
|||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL l, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 1 : 0; \
|
||||
temp2 = temp & 0x80000000; \
|
||||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR l, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
if (is486) CLOCK_CYCLES_ALWAYS(c); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 0x80000000 : 0; \
|
||||
temp2 = temp & 1; \
|
||||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 1; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
CLOCK_CYCLES((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||
seteal(temp << c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
|
||||
if ((temp << (c - 1)) & 0x80000000) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR l, c*/ \
|
||||
seteal(temp >> c); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
|
||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR l, c*/ \
|
||||
tempc = ((temp >> (c - 1)) & 1); \
|
||||
|
|
@ -275,7 +275,7 @@
|
|||
seteal(temp); if (abrt) return 1; \
|
||||
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
CLOCK_CYCLES((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
|
@ -555,7 +555,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
count = getbyte() & 31; \
|
||||
operation(); \
|
||||
\
|
||||
cycles -= 3; \
|
||||
CLOCK_CYCLES(3); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _CL_a16(uint32_t fetchdat) \
|
||||
|
|
@ -566,7 +566,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
count = CL & 31; \
|
||||
operation(); \
|
||||
\
|
||||
cycles -= 3; \
|
||||
CLOCK_CYCLES(3); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _i_a32(uint32_t fetchdat) \
|
||||
|
|
@ -577,7 +577,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
count = getbyte() & 31; \
|
||||
operation(); \
|
||||
\
|
||||
cycles -= 3; \
|
||||
CLOCK_CYCLES(3); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## operation ## _CL_a32(uint32_t fetchdat) \
|
||||
|
|
@ -588,7 +588,7 @@ static int opD3_l_a32(uint32_t fetchdat)
|
|||
count = CL & 31; \
|
||||
operation(); \
|
||||
\
|
||||
cycles -= 3; \
|
||||
CLOCK_CYCLES(3); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue