Cycle counts for recompiled blocks now generated at compile time.
This commit is contained in:
TomW
parent
087f412d3f
commit
2905c43db8
43 changed files with 1142 additions and 730 deletions
|
|
@ -9,7 +9,7 @@
|
|||
uint8_t src = getr8(reg); \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(rm, operation); \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
uint8_t src = getr8(reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
cycles -= timing_mr; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
uint8_t src = getr8(reg); \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(rm, operation); \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
uint8_t src = getr8(reg); \
|
||||
seteab(operation); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
cycles -= timing_mr; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
uint16_t src = regs[reg].w; \
|
||||
setflags ## 16 flagops; \
|
||||
regs[rm].w = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -62,11 +62,11 @@
|
|||
uint16_t src = regs[reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cycles -= timing_mr; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
|
||||
static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
|
||||
{ \
|
||||
int tempc = CF_SET(); \
|
||||
fetch_ea_32(fetchdat); \
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
uint16_t src = regs[reg].w; \
|
||||
setflags ## 16 flagops; \
|
||||
regs[rm].w = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -84,7 +84,7 @@
|
|||
uint16_t src = regs[reg].w; \
|
||||
seteaw(operation); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
cycles -= timing_mr; \
|
||||
CLOCK_CYCLES(timing_mr); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -99,7 +99,7 @@
|
|||
uint32_t src = regs[reg].l; \
|
||||
setflags ## 32 flagops; \
|
||||
regs[rm].l = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -107,7 +107,7 @@
|
|||
uint32_t src = regs[reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cycles -= timing_mrl; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -121,7 +121,7 @@
|
|||
uint32_t src = regs[reg].l; \
|
||||
setflags ## 32 flagops; \
|
||||
regs[rm].l = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
|
|
@ -129,7 +129,7 @@
|
|||
uint32_t src = regs[reg].l; \
|
||||
seteal(operation); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
cycles -= timing_mrl; \
|
||||
CLOCK_CYCLES(timing_mrl); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
|
|
@ -143,7 +143,7 @@
|
|||
src = geteab(); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(reg, operation); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -155,7 +155,7 @@
|
|||
src = geteab(); if (abrt) return 1; \
|
||||
setflags ## 8 flagops; \
|
||||
setr8(reg, operation); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -168,7 +168,7 @@
|
|||
src = geteaw(); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
regs[reg].w = operation; \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -180,7 +180,7 @@
|
|||
src = geteaw(); if (abrt) return 1; \
|
||||
setflags ## 16 flagops; \
|
||||
regs[reg].w = operation; \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -193,7 +193,7 @@
|
|||
src = geteal(); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
regs[reg].l = operation; \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rml; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
|
||||
return 0; \
|
||||
} \
|
||||
static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
|
||||
|
|
@ -205,7 +205,7 @@
|
|||
src = geteal(); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
regs[reg].l = operation; \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rml; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -216,7 +216,7 @@
|
|||
uint8_t src = getbytef(); \
|
||||
setflags ## 8 flagops; \
|
||||
AL = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -227,7 +227,7 @@
|
|||
uint16_t src = getwordf(); \
|
||||
setflags ## 16 flagops; \
|
||||
AX = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
return 0; \
|
||||
} \
|
||||
\
|
||||
|
|
@ -238,7 +238,7 @@
|
|||
uint32_t src = getlong(); if (abrt) return 1; \
|
||||
setflags ## 32 flagops; \
|
||||
EAX = operation; \
|
||||
cycles -= timing_rr; \
|
||||
CLOCK_CYCLES(timing_rr); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
|
@ -256,8 +256,8 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
setsub8(dst, getr8(reg));
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -266,8 +266,8 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
dst = geteab(); if (abrt) return 1;
|
||||
setsub8(dst, getr8(reg));
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -277,8 +277,8 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
setsub16(dst, regs[reg].w);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -287,8 +287,8 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
dst = geteaw(); if (abrt) return 1;
|
||||
setsub16(dst, regs[reg].w);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -298,8 +298,8 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
setsub32(dst, regs[reg].l);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
||||
|
|
@ -308,8 +308,8 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
dst = geteal(); if (abrt) return 1;
|
||||
setsub32(dst, regs[reg].l);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -319,7 +319,7 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
setsub8(getr8(reg), src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_b_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -328,7 +328,7 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
src = geteab(); if (abrt) return 1;
|
||||
setsub8(getr8(reg), src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -338,7 +338,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
setsub16(regs[reg].w, src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_w_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -347,7 +347,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
src = geteaw(); if (abrt) return 1;
|
||||
setsub16(regs[reg].w, src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rm;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -357,7 +357,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
|
|||
fetch_ea_16(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(regs[reg].l, src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rml;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_l_rm_a32(uint32_t fetchdat)
|
||||
|
|
@ -366,7 +366,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
|
|||
fetch_ea_32(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(regs[reg].l, src);
|
||||
cycles -= (mod == 3) ? timing_rr : timing_rml;
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -374,7 +374,7 @@ static int opCMP_AL_imm(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t src = getbytef();
|
||||
setsub8(AL, src);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -382,7 +382,7 @@ static int opCMP_AX_imm(uint32_t fetchdat)
|
|||
{
|
||||
uint16_t src = getwordf();
|
||||
setsub16(AX, src);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -390,7 +390,7 @@ static int opCMP_EAX_imm(uint32_t fetchdat)
|
|||
{
|
||||
uint32_t src = getlong(); if (abrt) return 1;
|
||||
setsub32(EAX, src);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -401,8 +401,8 @@ static int opTEST_b_a16(uint32_t fetchdat)
|
|||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_b_a32(uint32_t fetchdat)
|
||||
|
|
@ -412,8 +412,8 @@ static int opTEST_b_a32(uint32_t fetchdat)
|
|||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -424,8 +424,8 @@ static int opTEST_w_a16(uint32_t fetchdat)
|
|||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = regs[reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_w_a32(uint32_t fetchdat)
|
||||
|
|
@ -435,8 +435,8 @@ static int opTEST_w_a32(uint32_t fetchdat)
|
|||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = regs[reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -447,8 +447,8 @@ static int opTEST_l_a16(uint32_t fetchdat)
|
|||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = regs[reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_l_a32(uint32_t fetchdat)
|
||||
|
|
@ -458,8 +458,8 @@ static int opTEST_l_a32(uint32_t fetchdat)
|
|||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = regs[reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -467,21 +467,21 @@ static int opTEST_AL(uint32_t fetchdat)
|
|||
{
|
||||
uint8_t temp = getbytef();
|
||||
setznp8(AL & temp);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = getwordf();
|
||||
setznp16(AX & temp);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = getlong(); if (abrt) return 1;
|
||||
setznp32(EAX & temp);
|
||||
cycles -= timing_rr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -493,45 +493,45 @@ static int opTEST_EAX(uint32_t fetchdat)
|
|||
case 0x00: /*ADD ea, #*/ \
|
||||
setea ## ea_width(dst + src); if (abrt) return 1; \
|
||||
setadd ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x08: /*OR ea, #*/ \
|
||||
dst |= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x10: /*ADC ea, #*/ \
|
||||
setea ## ea_width(dst + src + tempc); if (abrt) return 1; \
|
||||
setadc ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x18: /*SBB ea, #*/ \
|
||||
setea ## ea_width(dst - (src + tempc)); if (abrt) return 1; \
|
||||
setsbc ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x20: /*AND ea, #*/ \
|
||||
dst &= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 1; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x38: /*CMP ea, #*/ \
|
||||
setsub ## flag_width(dst, src); \
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2); \
|
||||
else cycles -= ((mod == 3) ? 2 : 7); \
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2); \
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 7); \
|
||||
break; \
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue