116 lines
No EOL
6.5 KiB
Markdown
116 lines
No EOL
6.5 KiB
Markdown
---
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title: Michael Abrash's Graphics Programming Black Book, Special Edition
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author: Michael Abrash
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date: '1997-07-01'
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isbn: '1576101746'
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publisher: The Coriolis Group
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category: 'Web and Software Development: Game Development,Web and Software Development:
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Graphics and Multimedia Development'
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chapter: '23'
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pages: 441-443
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---
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#### Smooth Panning {#Heading7}
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The first thing you'll notice upon running the sample program is the
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remarkable smoothness with which the display pans from side-to-side and
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up-and-down. That the display can pan at all is made possible by two VGA
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features: 256K of display memory and the virtual screen capability. Even
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the most memory-hungry of the VGA modes, mode 12H (640x480), uses only
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37.5K per plane, for a total of 150K out of the total 256K of VGA
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memory. The medium-resolution mode, mode 10H (640x350), requires only
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28K per plane, for a total of 112K. Consequently, there is room in VGA
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memory to store more than two full screens of video data in mode 10H
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(which the sample program uses), and there is room in all modes to store
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a larger virtual screen than is actually displayed. In the sample
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program, memory is organized as two virtual screens, each with a
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resolution of 672x384, as shown in Figure 23.2. The area of the virtual
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screen actually displayed at any given time is selected by setting the
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display memory address at which to begin fetching video data; this is
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set by way of the start address registers (Start Address High, CRTC
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register 0CH, and Start Address Low, CRTC register 0DH). Together these
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registers make up a 16-bit display memory address at which the CRTC
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begins fetching data at the beginning of each video frame. Increasing
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the start address causes higher-memory areas of the virtual screen to be
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displayed. For example, the Start Address High register could be set to
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80H and the Start Address Low register could be set to 00H in order to
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cause the display screen to reflect memory starting at offset 8000H in
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each plane, rather than at the default offset of 0.
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The logical height of the virtual screen is defined by the amount of VGA
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memory available. As the VGA scans display memory for video data, it
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progresses from the start address toward higher memory one scan line at
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a time, until the frame is completed. Consequently, if the start address
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is increased, lines farther toward the bottom of the virtual screen are
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displayed; in effect, the virtual screen appears to scroll up on the
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physical screen.
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The logical width of the virtual screen is defined by the Offset
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register (CRTC register 13H), which allows redefinition of the number of
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words of display memory considered to make up one scan line. Normally,
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40 words of display memory constitute a scan line; after the CRTC scans
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these 40 words for 640 pixels worth of data, it advances 40 words from
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the start of that scan line to find the start of the next scan line in
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memory. This means that displayed scan lines are contiguous in memory.
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However, the Offset register can be set so that scan lines are logically
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wider (or narrower, for that matter) than their displayed width. The
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sample program sets the Offset register to 2AH, making the logical width
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of the virtual screen 42 words, or 42 \* 2 \* 8 = 672 pixels, as
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contrasted with the actual width of the mode 10h screen, 40 words or 640
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pixels. The logical height of the virtual screen in the sample program
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is 384; this is accomplished simply by reserving 84 \* 384 contiguous
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bytes of VGA memory for the virtual screen, where 84 is the virtual
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screen width in bytes and 384 is the virtual screen height in scan
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lines.
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The start address is the key to panning around the virtual screen. The
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start address registers select the row of the virtual screen that maps
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to the top of the display; panning down a scan line requires only that
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the start address be increased by the logical scan line width in bytes,
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which is equal to the Offset register times two. The start address
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registers select the column that maps to the left edge of the display as
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well, allowing horizontal panning, although in this case only relatively
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coarse byte-sized adjustments—panning by eight pixels at a time—are
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supported.
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Smooth horizontal panning is provided by the Horizontal Pel Panning
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register, AC register 13H, working in conjunction with the start
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address. Up to 7 pixels worth of single pixel panning of the displayed
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image to the left is performed by increasing the Horizontal Pel Panning
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register from 0 to 7. This exhausts the range of motion possible via the
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Horizontal Pel Panning register; the next pixel's worth of smooth
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panning is accomplished by incrementing the start address by one and
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resetting the Horizontal Pel Panning register to 0. Smooth horizontal
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panning should be viewed as a series of fine adjustments in the 8-pixel
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range between coarse byte-sized adjustments.
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A horizontal panning oddity: Alone among VGA modes, text mode (in most
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cases) has 9 dots per character clock. Smooth panning in this mode
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requires cycling the Horizontal Pel Panning register through the values
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8, 0, 1, 2, 3, 4, 5, 6, and 7. 8 is the "no panning" setting.
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There is one annoying quirk about programming the AC. When the AC Index
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register is set, only the lower five bits are used as the internal
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index. The next most significant bit, bit 5, controls the source of the
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video data sent to the monitor by the VGA. When bit 5 is set to 1, the
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output of the palette RAM, derived from display memory, controls the
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displayed pixels; this is normal operation. When bit 5 is 0, video data
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does not come from the palette RAM, and the screen becomes a solid
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color. The only time bit 5 of the AC Index register should be 0 is
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during the setting of a palette RAM register, since the CPU is only able
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to write to palette RAM when bit 5 is 0. (Some VGAs do not enforce this,
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but you should always set bit 5 to 0 before writing to the palette RAM
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just to be safe.) Immediately after setting palette RAM, however, 20h
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(or any other value with bit 5 set to 1) should be written to the AC
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Index register to restore normal video, and at all other times bit 5
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should be set to 1.
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> 
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> By the way, palette RAM can be set via the BIOS video interrupt
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> (interrupt 10H), function 10H. Whenever an VGA function can be performed
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> reasonably well through a BIOS function, as it can in the case of
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> setting palette RAM, it should be, both because there is no point in
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> reinventing the wheel and because the BIOS may well mask
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> incompatibilities between the IBM VGA and VGA clones. |