199 lines
7.2 KiB
Markdown
199 lines
7.2 KiB
Markdown
---
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title: Michael Abrash's Graphics Programming Black Book, Special Edition
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author: Michael Abrash
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date: '1997-07-01'
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isbn: '1576101746'
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publisher: The Coriolis Group
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category: 'Web and Software Development: Game Development,Web and Software Development:
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Graphics and Multimedia Development'
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chapter: '20'
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pages: 386-390
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---
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### V-Pipe-Capable Instructions {#Heading4}
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Any instruction can go through the U-pipe, and, for practical purposes,
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the U-pipe is always executing instructions. (The exceptions are when
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the U-pipe execution unit is waiting for instruction or data bytes after
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a cache miss, and when a U-pipe instruction finishes before a paired
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V-pipe instruction, as I'll discuss below.) Only the instructions shown
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in Table 20.1 can go through the V-pipe. In addition, the V-pipe can
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execute a separate instruction only when one of the instructions listed
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in Table 20.2 is executing in the U-pipe; superscalar execution is not
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possible while any instruction not listed in Table 20.2 is executing in
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the U-pipe. So, for example, if you use `SHR EDX,CL`, which takes 4
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cycles to execute, no other instructions can execute during those 4
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cycles; if, on the other hand, you use `SHR EDX,10`, it will take 1
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cycle to execute in the U-pipe, and another instruction can potentially
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execute concurrently in the V-pipe. (As you can see, similar instruction
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sequences can have vastly different performance characteristics on the
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Pentium.)
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Basically, after the current instruction or pair of instructions is
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finished (that is, once neither the U- nor V-pipe is executing
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anything), the Pentium sends the next instruction through the U-pipe. If
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the instruction after the one in the U-pipe is an instruction the V-pipe
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can handle, if the instruction in the U-pipe is pairable, and if
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register contention doesn't occur, then the V-pipe starts executing that
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instruction, as shown in Figure 20.2. Otherwise, the second instruction
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waits until the first instruction is done, then executes in the U-pipe,
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possibly pairing with the next instruction in line if all pairing
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conditions are met.
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```nasm
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MOV reg,reg (1 cycle)
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mem,reg (1 cycle)
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reg,mem (1 cycle)
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reg,immediate (1 cycle)
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mem,immediate (1 cycle)†
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AND/OR/XOR/ADD/SUB reg,reg (1 cycle)
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mem,reg (3 cycles)
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reg,mem (2 cycles)
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reg,immediate (1 cycle)
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mem,immediate (3 cycles)†
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INC/DEC reg (1 cycle)
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mem (3 cycles)
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CMP reg,reg (1 cycle)
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mem,reg (2 cycles)
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reg,mem (2 cycles)
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reg,immediate (1 cycle)
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mem,immediate (2 cycles)†
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TEST reg,reg (1 cycle)
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EAX,immediate (1 cycle)
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PUSH/POP reg (1 cycle)
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immediate (1 cycle)
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LEA reg,mem (1 cycle)
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JCC near (1 cycle if predicted correctly;
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5 cycles otherwise in V-pipe,
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4 cycles otherwise in U-pipe)
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JMP/CALL near (1 cycle if predicted correctly;
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3 cycles otherwise)
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```
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† Can't execute in V-pipe if address contains a displacement
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**Table 20.1 Instructions that can execute in the V-pipe.**
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The list of instructions the V-pipe can handle is not very long, and the
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list of U-pipe pairable instructions is not much longer, but these
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actually constitute the bulk of the instructions used in PC software. As
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a result, a fair amount of pairing happens even in normal,
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non-Pentium-optimized code. This fact, plus the 64-bit 66 MHz bus,
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branch prediction, dual 8K internal caches, and other Pentium features,
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together mean that a Pentium is considerably faster than a 486 at the
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same clock speed, even without Pentium-specific optimization, contrary
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to some reports.
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Besides, almost all operations can be performed by combinations of
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pairable instructions. For example, `PUSH [*mem*]` is not on either
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list, but both `MOV *reg*,[*mem*]` and `PUSH *reg*` are, and those
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two instructions can be used to push a value stored in memory. In fact,
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given the proper instruction stream, the discrete instructions can
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perform this operation effectively in just 1 cycle (taking one-half of
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each of 2 cycles, for 2\*0.5 = 1 cycle total execution time), as shown
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in Figure 20.3—a full cycle *faster* than `PUSH [*mem*]`, which takes
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2 cycles.
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```nasm
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MOV reg,reg (1 cycle)
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mem,reg (1 cycle)
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reg,mem (1 cycle)
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reg,immediate (1 cycle)
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mem,immediate (1 cycle)†
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AND/OR/XOR/ADD/SUB/ADC/SBB reg,reg (1 cycle)
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mem,reg (3 cycles)
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reg,mem (2 cycles)
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reg,immediate (1 cycle)
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mem,immediate (3 cycles)†
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INC/DEC reg (1 cycle)
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mem (3 cycles)
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CMP reg,reg (1 cycle)
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mem,reg (2 cycles)
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reg,mem (2 cycles)
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reg,immediate (1 cycle)
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mem,immediate (2 cycles)†
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TEST reg,reg (1 cycle)
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EAX,immediate (1 cycle)
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PUSH/POP reg (1 cycle)
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immediate (1 cycle)
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LEA reg,mem (1 cycle)
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SHL/SHR/SAL/SAR reg,immediate (1 cycle)††
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ROL/ROR/RCL/RCR reg,1 (1 cycle)
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```
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† Can't pair if address contains a displacement\
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†† Includes shift-by-1 forms of instructions
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**Table 20.2 Instructions that, when executed in the U-pipe, allow
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V-pipe-executable instructions to execute simultaneously (pair) in the
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V-pipe.**
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> 
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> A fundamental rule of Pentium optimization is that it pays to break
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> complex instructions into equivalent simple instructions, then shuffle
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> the simple instructions for maximum use of the V-pipe. This is true
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> partly because most of the pairable instructions are simple
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> instructions, and partly because breaking instructions into pieces
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> allows more freedom to rearrange code to avoid the AGIs and register
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> contention I'll discuss in the next chapter.
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One downside of this "RISCification" (turning complex instructions into
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simple, RISC-like ones) of Pentium-optimized code is that it makes for
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substantially larger code. For example,
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```nasm
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push dword ptr [esi]
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```
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is one byte smaller than this sequence:
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```nasm
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mov eax,[esi]
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push eax
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```
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A more telling example is the following
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```nasm
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add [MemVar],eax
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```
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versus the equivalent:
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```nasm
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mov edx,[MemVar]
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add edx,eax
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mov [MemVar],edx
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```
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The single complex instruction takes 3 cycles and is 6 bytes long; with
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proper sequencing, interleaving the simple instructions with other
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instructions that don't use EDX or `Mem Var`, the three-instruction
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sequence can be reduced to 1.5 cycles, but it is *14* bytes long.
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> 
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> It's not unusual for Pentium optimization to approximately double both
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> performance and code size at the same time. In an important loop, go for
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> performance and ignore the size, but on a program-wide basis, the size
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> bears watching.
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