fix init PIC + enable IRQ1 & 12 handeling
This commit is contained in:
Frater
parent
9cb9033a25
commit
82724598ee
7 changed files with 438 additions and 288 deletions
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@ -20,7 +20,9 @@
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;
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; =============================================================================
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%define MEM_SEG_DEB 0x0800 ; 0x0800:0000 = 0x8000 (32KB) évite IVT/BDA + stack 7C00
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%define MEM_SEG_END 0xA000 ; 0xA000:0000 = 0xA0000 (début zone vidéo)
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%define MEM_SEG_STEP 0x0040 ; 1KB = 0x400 bytes = 0x40 paragraphs
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; ---------------------------------------------------------------------------
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; Détection RAM conventionnelle
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@ -70,7 +72,7 @@ ram_setup:
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.fail_restore:
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; restaurer avant de sortir
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mov [es:di], bx
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mov [es:di], bx
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.done:
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; AX contient le nb de KB valides *à partir de MEM_SEG_DEB*.
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@ -87,7 +89,7 @@ ram_setup:
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mov bx, BDA_SEGMENT
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mov ds, bx
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mov [BDA_INFO_MEM_SIZE], ax
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mov [BDA_INFO_MEM_SEG],dx
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mov [BDA_INFO_MEM_SEG], dx
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ret
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@ -98,27 +100,23 @@ ram_setup:
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; Si une ROM est détectée, le code de la ROM sera appelé.
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; ---------------------------------------------------------------------------
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setup_load_rom:
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mov bx, 0xC000
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mov bx, 0xC000
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.scanloop:
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mov ds, bx
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cmp word[0x0000],0xAA55 ; ROM signature
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jne .norom
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; Debug
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mov al,'.'
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call debug_putc
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mov ds, bx
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cmp word[0x0000],0xAA55 ; ROM signature
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jne .norom
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; appel le code (en 0x0003) de la ROM
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push cs
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push word .norom ; address de retour
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push cs
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push word .norom ; address de retour
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push ds
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push 0x0003
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push ds
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push 0x0003
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retf ; call far ds:0x0003
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.norom:
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add bx, 0x80 ; add 2kb
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cmp bx, 0xE000
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jbe .scanloop
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add bx, 0x80 ; add 2kb
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cmp bx, 0xE000
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jbe .scanloop
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.end:
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ret
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@ -130,25 +128,22 @@ setup_load_rom:
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; ---------------------------------------------------------------------------
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setup_check_vga:
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; vérification de l'offset 0x0000:0x0040 qui DOIT etre différent de @default_isr
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xor ax,ax
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mov es,ax
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xor ax,ax
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mov es,ax
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; Lire INT10: offset+segment depuis 0000:0040
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mov bx, [es:0x0040] ; BX = offset INT10
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mov cx, [es:0x0042] ; CX = segment INT10
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mov ax, cs
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mov bx, [es:0x0040] ; BX = offset INT10
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mov cx, [es:0x0042] ; CX = segment INT10
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mov ax, cs
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; Comparer avec default_isr (offset) et CS (segment)
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mov dx, default_isr ; DX = offset default_isr (dans notre CS)
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cmp bx, dx
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jne .init_ok ; vecteur different, bios initialisé
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cmp cx, ax
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jne .init_ok
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mov dx, default_isr ; DX = offset default_isr (dans notre CS)
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cmp bx, dx
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jne .init_ok ; vecteur different, bios initialisé
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cmp cx, ax
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jne .init_ok
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mov ax,cs ; vecteur identique, sans doute pas d'initialisation
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mov ds,ax
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mov si, err_vganok
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call debug_puts
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mov ax,cs ; vecteur identique, sans doute pas d'initialisation
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mov ds,ax
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.init_ok:
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ret
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@ -158,20 +153,20 @@ setup_check_vga:
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; ---------------------------------------------------------------------------
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ivt_setup:
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; installation de la table d'interrupts
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xor ax, ax
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mov es, ax ; ES = 0000h -> base IVT
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xor di, di ; DI = 0000h -> offset IVT
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xor ax, ax
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mov es, ax ; ES = 0000h -> base IVT
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xor di, di ; DI = 0000h -> offset IVT
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mov ax, default_isr ; offset du handler
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mov dx, cs ; segment du handler (ROM)
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mov ax, default_isr ; offset du handler
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mov dx, cs ; segment du handler (ROM)
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mov cx, 256 ; 256 vecteurs
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mov cx, 256 ; 256 vecteurs
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.fill:
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stosw ; write offset (AX) -> [ES:DI], DI += 2
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xchg ax, dx ; AX = segment, DX = offset
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xchg ax, dx ; AX = segment, DX = offset
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stosw ; write segment (AX) -> [ES:DI], DI += 2
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xchg ax, dx ; AX = offset, DX = segment
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loop .fill
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xchg ax, dx ; AX = offset, DX = segment
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loop .fill
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; fin de la table d'interrupt
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ret
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@ -183,29 +178,29 @@ ivt_setup:
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; bx = offset handler
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; ---------------------------------------------------------------------------
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ivt_setvector:
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push es
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push di
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push es
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push di
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shl ax,2 ; ax=id *4
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mov di,ax
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shl ax,2 ; ax=id *4
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mov di,ax
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xor ax,ax
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mov es, ax ; ES = 0000h -> base IVT
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xor ax,ax
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mov es, ax ; ES = 0000h -> base IVT
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mov ax, bx ; offset du handler
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mov ax, bx ; offset du handler
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cli
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stosw ; write offset (AX) -> [ES:DI], DI += 2
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xchg ax, dx ; AX = segment, DX = offset
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xchg ax, dx ; AX = segment, DX = offset
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stosw ; write segment (AX) -> [ES:DI], DI += 2
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sti
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pop di
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pop es
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pop di
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pop es
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ret
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io_wait:
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xor al,al
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out 0x80,al
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xor al,al
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out 0x80,al
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ret
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; ---------------------------------------------------------------------------
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@ -216,52 +211,90 @@ io_wait:
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; https://wiki.nox-rhea.org/back2root/ibm-pc-ms-dos/hardware/8259
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; ---------------------------------------------------------------------------
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pic_init:
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push ax
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cli
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push ax
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; force un End Of Interrupt sur les 2 PIC
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mov al, 0x20
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out i8259_SLAVE_CMD, al ; EOI PIC esclave
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out i8259_MASTER_CMD, al ; EOI PIC maître
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; starts the initialization sequence (in cascade mode)
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mov al, ICW1_INIT | ICW1_ICW4
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out i8259_MASTER_CMD, al
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call io_wait
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mov al, ICW1_INIT | ICW1_ICW4
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out i8259_MASTER_CMD, al
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out i8259_SLAVE_CMD, al
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mov al, ICW1_INIT | ICW1_ICW4
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out i8259_SLAVE_CMD, al
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call io_wait
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mov al, i8259_MASTER_INT
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out i8259_MASTER_DATA, al ; ICW2: Master PIC vector offset
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call io_wait
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mov al, i8259_SLAVE_INT
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out i8259_SLAVE_DATA, al ; ICW2: Slave PIC vector offset
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call io_wait
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mov al, i8259_MASTER_INT
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out i8259_MASTER_DATA, al ; ICW2: Master PIC vector offset
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mov al, i8259_SLAVE_INT
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out i8259_SLAVE_DATA, al ; ICW2: Slave PIC vector offset
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; Master: cascade (IRQ2 => 1 << IRQ2 = 0x04)
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mov al, 0x04 ; master: slave on IRQ2: 0100b
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out i8259_MASTER_DATA, al ; ICW3: tell Master PIC that there is a slave PIC at IRQ2
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call io_wait
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mov al, 0x04 ; master: slave on IRQ2: 0100b
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out i8259_MASTER_DATA, al ; ICW3: tell Master PIC that there is a slave PIC at IRQ2
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; Slave: numéro de ligne sur master (2)
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mov al, 0x02 ; slave: cascade identity 2
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out i8259_SLAVE_DATA, al ; ICW3: tell Slave PIC its cascade identity (0000 0010)
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call io_wait
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mov al, 0x02 ; slave: cascade identity 2
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out i8259_SLAVE_DATA, al ; ICW3: tell Slave PIC its cascade identity (0000 0010)
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; ICW4: 8086 mode
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mov al, ICW4_8086
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out i8259_MASTER_DATA, al
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call io_wait
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mov al, ICW4_8086
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out i8259_MASTER_DATA, al
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out i8259_SLAVE_DATA, al
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mov al, ICW4_8086
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out i8259_SLAVE_DATA, al
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call io_wait
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; Unmask both PICs.
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xor al,al
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out i8259_MASTER_DATA, al
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out i8259_SLAVE_DATA, al
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pop ax
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pop ax
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ret
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; ------------------------------------------------------------------
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; set_irq_mask
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; AH = 0 (Enable/Unmask) ou 1 (Disable/Mask)
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; AL = Numéro de l'IRQ (0 à 15)
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; ------------------------------------------------------------------
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pic_set_irq_mask:
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push bx
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push cx
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push dx
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push ax ; Sauvegarde AX pour récupérer AH plus tard
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mov cl, al ; CL = numéro d'IRQ
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; Par défaut, PIC Maître (Data port)
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mov dx, i8259_MASTER_DATA
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cmp cl, 8
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jl .is_master
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; Si IRQ >= 8, on passe sur le PIC Esclave
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sub cl, 8 ; Ajuste l'index du bit (8-15 -> 0-7)
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; Port Data du PIC Esclave
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mov dx, i8259_SLAVE_DATA
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.is_master:
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; Préparation du masque de bit
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mov bl, 1
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shl bl, cl ; BL contient maintenant le bit correspondant (ex: IRQ 3 -> 00001000)
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in al, dx ; Lire l'IMR actuel depuis le port (0x21 ou 0xA1)
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test ah, ah ; AH est-il à 1 (Disable) ?
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jnz .do_disable
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.do_enable:
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not bl ; Inverser le masque (ex: 11110111)
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and al, bl ; Mettre le bit à 0 (Unmask)
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jmp .write_back
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.do_disable:
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or al, bl ; Mettre le bit à 1 (Mask)
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.write_back:
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out dx, al ; Écrire le nouveau masque dans l'IMR
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pop ax ; Restaurer AX
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pop dx
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pop cx
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pop bx
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ret
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; ---------------------------------------------------------------------------
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; Handler par défaut: fait juste IRET
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; IMPORTANT: doit être FAR (appelé par le CPU via IVT), et terminer par IRET
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