881 lines
48 KiB
JavaScript
881 lines
48 KiB
JavaScript
/**
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* @fileoverview PDP11-specific compile-time definitions.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @copyright © Jeff Parsons 2012-2016
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*
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* This file is part of PCjs, a computer emulation software project at <http://pcjs.org/>.
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*
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* It has been adapted from the JavaScript PDP 11/70 Emulator v1.4 written by Paul Nankervis
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* (paulnank@hotmail.com) as of September 2016 at <http://skn.noip.me/pdp11/pdp11.html>. This code
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* may be used freely provided the original authors are acknowledged in any modified source code.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every modified copy of this work
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* and to display that copyright notice when the software starts running; see COPYRIGHT in
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* <http://pcjs.org/modules/shared/lib/defines.js>.
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of PCjs
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* for purposes of the GNU General Public License, and the author does not claim any copyright
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* as to their contents.
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*/
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"use strict";
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/**
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* @define {string}
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*/
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var APPCLASS = "pdp11"; // this @define is the default application class (eg, "pcx86", "c1pjs")
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/**
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* APPNAME is used more for display purposes than anything else now. APPCLASS is what matters in terms
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* of folder and file names, CSS styles, etc.
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*
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* @define {string}
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*/
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var APPNAME = "PDPjs"; // this @define is the default application name (eg, "PCx86", "C1Pjs")
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/**
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* WARNING: DEBUGGER needs to accurately reflect whether or not the Debugger component is (or will be) loaded.
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* In the compiled case, we rely on the Closure Compiler to override DEBUGGER as appropriate. When it's *false*,
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* nearly all of debugger.js will be conditionally removed by the compiler, reducing it to little more than a
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* "type skeleton", which also solves some type-related warnings we would otherwise have if we tried to remove
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* debugger.js from the compilation process altogether.
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*
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* However, when we're in "development mode" and running uncompiled code in debugger-less configurations,
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* I would like to skip loading debugger.js altogether. When doing that, we must ALSO arrange for an additional file
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* (nodebugger.js) to be loaded immediately after this file, which *explicitly* overrides DEBUGGER with *false*.
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*
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* @define {boolean}
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*/
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var DEBUGGER = true; // this @define is overridden by the Closure Compiler to remove Debugger-related support
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/**
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* BYTEARRAYS is a Closure Compiler compile-time option that allocates an Array of numbers for every Memory block,
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* where each a number represents ONE byte; very wasteful, but potentially slightly faster.
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*
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* See the Memory component for details.
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*
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* @define {boolean}
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*/
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var BYTEARRAYS = false;
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/**
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* TYPEDARRAYS enables use of typed arrays for Memory blocks. This used to be a compile-time-only option, but I've
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* added Memory access functions for typed arrays (see MemoryPDP11.afnTypedArray), so support can be enabled dynamically now.
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*
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* See the Memory component for details.
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*/
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var TYPEDARRAYS = (typeof ArrayBuffer !== 'undefined');
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/**
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* MEMFAULT forces the Memory interfaces to signal a CPU fault when a word is accessed using an odd (unaligned) address.
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*
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* Since PDPjs inherited its Bus component from PCx86, it included support for both aligned and unaligned word accesses
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* by default. However, the PDP-11 adds a wrinkle: when an odd address is used to access a memory word, a BUS trap
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* must be generated. Note that odd IOPAGE word accesses are fine; this only affects the Memory component.
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*
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* When the MMU is enabled, these checks may also be performed at a higher level, eliminating the need for them at the
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* physical memory level.
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*/
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var MEMFAULT = true;
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/**
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* WORDBUS turns off support for unaligned memory words. Whereas MEMFAULT necessarily slows down memory word accesses
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* slightly, WORDBUS is able to speed them up slightly, by assuming that all word accesses (which didn't fault) must be
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* aligned. This affects all word accesses, even IOPAGE accesses, because it also eliminates cross-block boundary checks.
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*
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* Don't worry that the source code looks MORE complicated rather than LESS with the additional MEMFAULT and WORDBUS checks,
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* because the Closure Compiler eliminates those checks and throws away the (unreachable) code blocks that deal with unaligned
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* accesses.
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*/
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var WORDBUS = true;
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/*
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* Combine all the shared globals and machine-specific globals into one machine-specific global object,
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* which all machine components should start using; eg: "if (PDP11.DEBUG) ..." instead of "if (DEBUG) ...".
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*/
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var PDP11 = {
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APPCLASS: APPCLASS,
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APPNAME: APPNAME,
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APPVERSION: APPVERSION, // shared
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BYTEARRAYS: BYTEARRAYS,
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COMPILED: COMPILED, // shared
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CSSCLASS: CSSCLASS, // shared
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DEBUG: DEBUG, // shared
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DEBUGGER: DEBUGGER,
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MAXDEBUG: MAXDEBUG, // shared
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PRIVATE: PRIVATE, // shared
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TYPEDARRAYS:TYPEDARRAYS,
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MEMFAULT: MEMFAULT,
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WORDBUS: WORDBUS,
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SITEHOST: SITEHOST, // shared
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XMLVERSION: XMLVERSION, // shared
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/*
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* CPU model numbers (supported)
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*/
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MODEL_1120: 1120,
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MODEL_1145: 1145,
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MODEL_1170: 1170,
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/*
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* This constant is used to mark points in the code where the physical address being returned
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* is invalid and should not be used.
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*
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* In a 32-bit CPU, -1 (ie, 0xffffffff) could actually be a valid address, so consider changing
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* ADDR_INVALID to NaN or null (which is also why all ADDR_INVALID tests should use strict equality
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* operators).
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*
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* The main reason I'm NOT using NaN or null now is my concern that, by mixing non-numbers
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* (specifically, values outside the range of signed 32-bit integers), performance may suffer.
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*
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* WARNING: Like many of the properties defined here, ADDR_INVALID is a common constant, which the
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* Closure Compiler will happily inline (with or without @const annotations; in fact, I've yet to
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* see a @const annotation EVER improve automatic inlining). However, if you don't make ABSOLUTELY
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* certain that this file is included BEFORE the first reference to any of these properties, that
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* automatic inlining will no longer occur.
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*/
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ADDR_INVALID: -1,
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/*
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* Processor modes
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*/
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MODE: {
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KERNEL: 0x0,
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SUPER: 0x1,
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UNUSED: 0x2,
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USER: 0x3,
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MASK: 0x3
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},
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/*
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* Processor Status Word (stored in regPSW) at 177776
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*/
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PSW: {
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CF: 0x0001, // bit 0 (000001) Carry Flag
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VF: 0x0002, // bit 1 (000002) Overflow Flag (aka OF on Intel processors)
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ZF: 0x0004, // bit 2 (000004) Zero Flag
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NF: 0x0008, // bit 3 (000010) Negative Flag (aka SF -- Sign Flag -- on Intel processors)
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TF: 0x0010, // bit 4 (000020) Trap Flag
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PRI: 0x00E0, // bits 5-7 (000340) Priority
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UNUSED: 0x0700, // bits 8-10 (003400) UNUSED
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/*
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* PSW bits above this point are unused on 11/20-class machines
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*/
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REGSET: 0x0800, // bit 11 (004000) Register Set
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PMODE: 0x3000, // bits 12-13 (030000) Prev Mode (see PDP11.MODE)
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CMODE: 0xC000, // bits 14-15 (140000) Curr Mode (see PDP11.MODE)
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SHIFT: {
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CF: 0,
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VF: 1,
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ZF: 2,
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NF: 3,
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TF: 4,
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PRI: 5,
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PMODE: 12,
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CMODE: 14
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}
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},
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/*
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* Program Interrupt Register (stored in regPIR) at 177772
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*
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* The PIA bits at 5-7 are designed to align with PRI bits 5-7 in the PSW.
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*/
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PIR: {
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BITS: 0xFE00, // bits 9-15 correspond to interrupt requests 1-7
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PIA: 0x00EE, // the PIA bits contain two copies of the corresponding interrupt request priority
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PIA_INC: 0x0022, // both sets of PIA bits can be incremented with this constant
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SHIFT: {
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BITS: 9
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}
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},
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/*
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* PDP-11 trap vectors
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*/
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TRAP: {
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UNDEFINED: 0x00, // 000 (reserved)
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BUS: 0x04, // 004 unaligned address, non-existent memory, illegal instruction, etc
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RESERVED: 0x08, // 010 reserved instructions
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BPT: 0x0C, // 014 BPT: breakpoint trap (trace)
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IOT: 0x10, // 020 IOT: input/output trap
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PF: 0x14, // 024 power fail
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EMT: 0x18, // 030 EMT: emulator trap
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TRAP: 0x1C, // 034 TRAP instruction
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PIRQ: 0xA0, // 240 PIRQ: program interrupt request
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MMU: 0xA8 // 250 MMU: aborts and traps
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},
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/*
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* PDP-11 trap reasons; the reason may also be a non-negative address indicating a BUS memory error
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* (unaligned address or non-existent memory). Any reason >= RED (which includes BUS memory errors) generate
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* immediate (thrown) traps, as they are considered ABORTs; the rest generate synchronous traps.
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*/
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REASON: {
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ABORT: -1, // immediate MMU fault
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ILLEGAL: -2, // immediate invalid opcode (BUS)
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RED: -3, // immediate stack overflow fault (BUS)
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YELLOW: -4, // deferred stack overflow fault (BUS)
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FAULT: -5, // deferred MMU fault
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TRACE: -6, // deferred TF fault (BPT)
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HALT: -7, // illegal HALT (BUS)
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OPCODE: -8, // opcode-generated trap (eg, BPT, EMT, IOT, TRAP, or RESERVED opcode)
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INTERRUPT: -9, // device-generated trap (vector is device-specific)
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},
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REASONS: [
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"UNKNOWN",
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"ABORT",
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"ILLEGAL",
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"RED",
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"YELLOW",
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"FAULT",
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"TRACE",
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"HALT",
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"OPCODE",
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"INTERRUPT"
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],
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/*
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* Assorted common opcodes
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*/
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OPCODE: {
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HALT: 0x0000,
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WAIT: 0x0001,
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BPT: 0x0003,
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IOT: 0x0004,
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JSR_OP: 0x0800,
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JSR_MASK: 0xFE00,
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EMT_OP: 0x8800,
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EMT_MASK: 0xFF00,
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TRAP_OP: 0x8900,
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TRAP_MASK: 0xFF00,
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INVALID: 0xFFFF // far from the only invalid opcode, just a KNOWN invalid opcode
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},
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/*
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* Internal operation state flags
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*/
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OPFLAG: {
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IRQ_DELAY: 0x0001, // incremented until it becomes IRQ (set by SPL and traps)
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IRQ: 0x0002, // time to call checkInterrupts()
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IRQ_MASK: 0x0003,
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WAIT: 0x0008, // WAIT operation in progress
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PRESERVE: 0x000F, // OPFLAG bits to preserve prior to the next instruction
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TRAP_TF: 0x0010, // aka PDP11.PSW.TF (WARNING: do not change this bit, or you will likely break opRTI())
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TRAP_SP: 0x0020, // set for a deferred BUS trap (due to a "yellow" stack overflow condition)
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TRAP_MMU: 0x0040,
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TRAP_MASK: 0x0070,
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TRAP_LAST: 0x0080, // set if last operation was a trap (see trapLast for the vector, and trapReason for the reason)
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NO_FLAGS: 0x0100 // set whenever the PSW is written directly, requiring all updateXXXFlags() functions to leave flags unchanged
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},
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/*
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* Opcode reg (opcode bits 2-0)
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*/
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OPREG: {
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MASK: 0x07
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},
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/*
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* Opcode modes (opcode bits 5-3)
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*/
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OPMODE: {
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REG: 0x00, // REGISTER (register is operand)
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REGD: 0x08, // REGISTER DEFERRED (register is address of operand)
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POSTINC: 0x10, // AUTO-INCREMENT (register is address of operand, register incremented)
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POSTINCD: 0x18, // AUTO-INCREMENT DEFERRED (register is address of address of operand, register incremented)
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PREDEC: 0x20, // AUTO-DECREMENT (register decremented, register is address of operand)
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PREDECD: 0x28, // AUTO-DECREMENT DEFERRED (register decremented, register is address of address of operand)
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INDEX: 0x30, // INDEX (register + next word is address of operand)
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INDEXD: 0x38, // INDEX DEFERRED (register + next word is address of address of operand)
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MASK: 0x38,
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SHIFT: 3
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},
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DSTMODE: {
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REG: 0x0007,
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MODE: 0x0038,
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MASK: 0x003F,
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SHIFT: 0
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},
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SRCMODE: {
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REG: 0x01C0,
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MODE: 0x0E00,
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MASK: 0x0FC0,
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SHIFT: 6
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},
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REG: {
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SP: 6,
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PC: 7,
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},
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/*
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* Internal memory access flags
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*/
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ACCESS: {
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WORD: 0x00,
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BYTE: 0x01,
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READ: 0x02,
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WRITE: 0x04,
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UPDATE: 0x06,
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VIRT: 0x08, // getVirtualByMode() leaves bit 17 clear if this is set (otherwise the caller would have to clear it again)
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ISPACE: 0x00000,
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DSPACE: 0x10000 // getVirtualByMode() sets bit 17 in any 16-bit virtual address that refers to D space (as opposed to I space)
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},
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/*
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* Internal flags passed to writeDstByte()
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*
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* The BYTE and SBYTE values have been chosen so that they can be used directly as masks.
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*/
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WRITE: {
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BYTE: 0xff, // write byte normally
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SBYTE: 0xffff // sign-extend byte to word
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},
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CPUERR: { // 177766
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RED: 0x0004, // 000004 red zone stack limit
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YELLOW: 0x0008, // 000010 yellow zone stack limit
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TIMEOUT: 0x0010, // 000020 UNIBUS timeout error
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NOMEMORY: 0x0020, // 000040 non-existent memory error
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ODDADDR: 0x0040, // 000100 odd word address error (as in non-even, not strange)
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BADHALT: 0x0080 // 000200 HALT attempted in USER or SUPER modes
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},
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MMR0: { // 177572
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ENABLED: 0x0001, // 000001 address relocation enabled
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PAGE_NUM: 0x000E, // 000016 page number of last fault
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PAGE_D: 0x0010, // 000020 last fault occurred in D space (11/44 and 11/70 only)
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PAGE: 0x001E, // 000176 (all of the PAGE bits)
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MODE: 0x0060, // 000140 processor mode as of last fault
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COMPLETED: 0x0080, // 000200 last instruction completed (R/O) (11/70 only)
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DSTMODE: 0x0100, // 000400 only destination mode references will be relocated (aka MAINT bit)
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MMU_TRAPS: 0x0200, // 001000 enable MMU traps (11/70 only)
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UNUSED: 0x0C00, // 006000
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TRAP_MMU: 0x1000, // 010000 trap: MMU (11/70 only)
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ABORT_RO: 0x2000, // 020000 abort: read-only
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ABORT_PL: 0x4000, // 040000 abort: page length
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ABORT_NR: 0x8000, // 100000 abort: non-resident
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ABORT: 0xE000, // 160000 (all of the ABORT bits)
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UPDATE: 0xF0FE // Includes all of: ABORT, TRAP, COMPLETED, MODE, and PAGE bits
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},
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MMR1: { // 177574: general purpose auto-inc/auto-dec register (11/44 and 11/70 only)
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REG1_NUM: 0x0007, //
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REG1_DELTA: 0x00F8, //
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REG2_NUM: 0x0700, //
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REG2_DELTA: 0xF800 //
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},
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MMR2: { // 177576: virtual program counter register
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},
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MMR3: { // 172516: mapping register (11/44 and 11/70 only)
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USER_D: 0x0001,
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SUPER_D: 0x0002,
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KERNEL_D: 0x0004,
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MMU_22BIT: 0x0010,
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UNIBUS_MAP: 0x0020 // UNIBUS map relocation enabled
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},
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PDR: {
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ACF: {
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NR: 0x0, // non-resident, abort all accesses
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RO1: 0x1, // read-only, abort on write attempt, memory management trap on read (11/70 only)
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RO: 0x2, // read-only, abort on write attempt
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U1: 0x3, // unused, abort all accesses--reserved for future use
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RW1: 0x4, // read/write, memory management trap upon completion of a read or write
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RW2: 0x5, // read/write, memory management trap upon completion of a write (11/70 only)
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RW: 0x6, // read/write, no system trap/abort action
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U2: 0x7, // unused, abort all accesses--reserved for future use
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MASK: 0x7
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},
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ED: 0x0008, // expansion direction (if set, the page expands downward from block number 127)
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UNUSED: 0x0030,
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MODIFIED: 0x0040, // page has been written (bit cleared when either PDR or PAR is written)
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ACCESSED: 0x0080, // page has been accessed (bit cleared when either PDR or PAR is written) (11/70 only)
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PLF: 0x7F00, // page length field
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BC: 0x8000 // bypass cache (11/44 only)
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},
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/*
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* Assorted special (UNIBUS) addresses
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*
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* Within the PDP-11/45's 18-bit address space, of the 0x40000 possible addresses (256Kb), the top 0x2000
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* (8Kb) is called the IOPAGE and is reserved for CPU and I/O registers. The IOPAGE spans 0x3E000-0x3FFFF.
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*
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* Within the PDP-11/70's 22-bit address space, of the 0x400000 possible addresses (4Mb), the top 0x20000
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* (256Kb) is mapped to the UNIBUS (not physical memory), and as before, the top 0x2000 (8Kb) of that is
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* mapped to the IOPAGE.
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*
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* To map 18-bit UNIBUS addresses to 22-bit physical addresses, the 11/70 uses a UNIBUS relocation map.
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* It consists of 31 double-word registers that each hold a 22-bit base address. When UNIBUS relocation
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* is enabled, the top 5 bits of an address select one of the 31 mapping registers, and the bottom 13 bits
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* are then added to the contents of the selected mapping register.
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*
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* ES6 ALERT: By using octal constants, I'm finally dipping my toe into ES6 (aka ECMAScript 2015) waters.
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* You'll even see a few binary constants below, too. If you're loading this raw source code into your browser,
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* then by now (2016) you're almost certainly using an ES6-aware browser. Production sites should be using code
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* compiled by Google's Closure Compiler, which we configure to produce code that's backward-compatible with ES5
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* (for example, all binary, octal, and hex constants are converted to decimal values).
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*
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* For more details: https://github.com/google/closure-compiler/wiki/ECMAScript6
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*/
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UNIBUS: { //16-bit 18-bit 22-bit Hex Description
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UNIMAP: 0o170200, // UNIBUS Mapping Registers (0-31) 64 words (ends at 0o170372)
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SIPDR0: 0o172200, // Supervisor I Page Descriptor Register 0
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SIPDR1: 0o172202, // Supervisor I Page Descriptor Register 1
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SIPDR2: 0o172204, // Supervisor I Page Descriptor Register 2
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SIPDR3: 0o172206, // Supervisor I Page Descriptor Register 3
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SIPDR4: 0o172210, // Supervisor I Page Descriptor Register 4
|
|
SIPDR5: 0o172212, // Supervisor I Page Descriptor Register 5
|
|
SIPDR6: 0o172214, // Supervisor I Page Descriptor Register 6
|
|
SIPDR7: 0o172216, // Supervisor I Page Descriptor Register 7
|
|
SDPDR0: 0o172220, // Supervisor D Page Descriptor Register 0
|
|
SDPDR1: 0o172222, // Supervisor D Page Descriptor Register 1
|
|
SDPDR2: 0o172224, // Supervisor D Page Descriptor Register 2
|
|
SDPDR3: 0o172226, // Supervisor D Page Descriptor Register 3
|
|
SDPDR4: 0o172230, // Supervisor D Page Descriptor Register 4
|
|
SDPDR5: 0o172232, // Supervisor D Page Descriptor Register 5
|
|
SDPDR6: 0o172234, // Supervisor D Page Descriptor Register 6
|
|
SDPDR7: 0o172236, // Supervisor D Page Descriptor Register 7
|
|
SIPAR0: 0o172240, // Supervisor I Page Address Register 0
|
|
SIPAR1: 0o172242, // Supervisor I Page Address Register 1
|
|
SIPAR2: 0o172244, // Supervisor I Page Address Register 2
|
|
SIPAR3: 0o172246, // Supervisor I Page Address Register 3
|
|
SIPAR4: 0o172250, // Supervisor I Page Address Register 4
|
|
SIPAR5: 0o172252, // Supervisor I Page Address Register 5
|
|
SIPAR6: 0o172254, // Supervisor I Page Address Register 6
|
|
SIPAR7: 0o172256, // Supervisor I Page Address Register 7
|
|
SDPAR0: 0o172260, // Supervisor D Page Address Register 0
|
|
SDPAR1: 0o172262, // Supervisor D Page Address Register 1
|
|
SDPAR2: 0o172264, // Supervisor D Page Address Register 2
|
|
SDPAR3: 0o172266, // Supervisor D Page Address Register 3
|
|
SDPAR4: 0o172270, // Supervisor D Page Address Register 4
|
|
SDPAR5: 0o172272, // Supervisor D Page Address Register 5
|
|
SDPAR6: 0o172274, // Supervisor D Page Address Register 6
|
|
SDPAR7: 0o172276, // Supervisor D Page Address Register 7
|
|
KIPDR0: 0o172300, // Kernel I Page Descriptor Register 0
|
|
KIPDR1: 0o172302, // Kernel I Page Descriptor Register 1
|
|
KIPDR2: 0o172304, // Kernel I Page Descriptor Register 2
|
|
KIPDR3: 0o172306, // Kernel I Page Descriptor Register 3
|
|
KIPDR4: 0o172310, // Kernel I Page Descriptor Register 4
|
|
KIPDR5: 0o172312, // Kernel I Page Descriptor Register 5
|
|
KIPDR6: 0o172314, // Kernel I Page Descriptor Register 6
|
|
KIPDR7: 0o172316, // Kernel I Page Descriptor Register 7
|
|
KDPDR0: 0o172320, // Kernel D Page Descriptor Register 0
|
|
KDPDR1: 0o172322, // Kernel D Page Descriptor Register 1
|
|
KDPDR2: 0o172324, // Kernel D Page Descriptor Register 2
|
|
KDPDR3: 0o172326, // Kernel D Page Descriptor Register 3
|
|
KDPDR4: 0o172330, // Kernel D Page Descriptor Register 4
|
|
KDPDR5: 0o172332, // Kernel D Page Descriptor Register 5
|
|
KDPDR6: 0o172334, // Kernel D Page Descriptor Register 6
|
|
KDPDR7: 0o172336, // Kernel D Page Descriptor Register 7
|
|
KIPAR0: 0o172340, // Kernel I Page Address Register 0
|
|
KIPAR1: 0o172342, // Kernel I Page Address Register 1
|
|
KIPAR2: 0o172344, // Kernel I Page Address Register 2
|
|
KIPAR3: 0o172346, // Kernel I Page Address Register 3
|
|
KIPAR4: 0o172350, // Kernel I Page Address Register 4
|
|
KIPAR5: 0o172352, // Kernel I Page Address Register 5
|
|
KIPAR6: 0o172354, // Kernel I Page Address Register 6
|
|
KIPAR7: 0o172356, // Kernel I Page Address Register 7
|
|
KDPAR0: 0o172360, // Kernel D Page Address Register 0
|
|
KDPAR1: 0o172362, // Kernel D Page Address Register 1
|
|
KDPAR2: 0o172364, // Kernel D Page Address Register 2
|
|
KDPAR3: 0o172366, // Kernel D Page Address Register 3
|
|
KDPAR4: 0o172370, // Kernel D Page Address Register 4
|
|
KDPAR5: 0o172372, // Kernel D Page Address Register 5
|
|
KDPAR6: 0o172374, // Kernel D Page Address Register 6
|
|
KDPAR7: 0o172376, // Kernel D Page Address Register 7
|
|
|
|
MMR3: 0o172516, // 772516 17772516
|
|
|
|
RLCS: 0o174400, // RL11 Control Status Register
|
|
RLBA: 0o174402, // RL11 Bus Address Register
|
|
RLDA: 0o174404, // RL11 Disk Address Register
|
|
RLMP: 0o174406, // RL11 Multi-Purpose Register
|
|
RLBE: 0o174410, // RL11 Bus (Address) Extension Register (RLV12 controller only)
|
|
|
|
RKDS: 0o177400, // RK11 Drive Status Register
|
|
RKER: 0o177402, // RK11 Error Register
|
|
RKCS: 0o177404, // RK11 Control Status Register
|
|
RKWC: 0o177406, // RK11 Word Count Register
|
|
RKBA: 0o177410, // RK11 Bus Address Register
|
|
RKDA: 0o177412, // RK11 Disk Address Register
|
|
// NOTE: 177414 is unused
|
|
RKDB: 0o177416, // RK11 Data Buffer Register
|
|
|
|
LKS: 0o177546, // KW11-L Clock Status
|
|
|
|
PRS: 0o177550, // PC11 (and PR11) Reader Status Register
|
|
PRB: 0o177552, // PC11 (and PR11) Reader Buffer Register
|
|
PPS: 0o177554, // PC11 Punch Status Register
|
|
PPB: 0o177556, // PC11 Punch Buffer Register
|
|
|
|
RCSR: 0o177560, // DL11 Receiver Status Register
|
|
RBUF: 0o177562, // DL11 Receiver Data Buffer Register
|
|
XCSR: 0o177564, // DL11 Transmitter Status Register
|
|
XBUF: 0o177566, // DL11 Transmitter Data Buffer Register
|
|
|
|
CNSW: 0o177570, // Console (Front Panel) Switch/Display Register
|
|
|
|
MMR0: 0o177572, // 777572 17777572
|
|
MMR1: 0o177574, // 777574 17777574
|
|
MMR2: 0o177576, // 777576 17777576
|
|
|
|
UIPDR0: 0o177600, // User I Page Descriptor Register 0
|
|
UIPDR1: 0o177602, // User I Page Descriptor Register 1
|
|
UIPDR2: 0o177604, // User I Page Descriptor Register 2
|
|
UIPDR3: 0o177606, // User I Page Descriptor Register 3
|
|
UIPDR4: 0o177610, // User I Page Descriptor Register 4
|
|
UIPDR5: 0o177612, // User I Page Descriptor Register 5
|
|
UIPDR6: 0o177614, // User I Page Descriptor Register 6
|
|
UIPDR7: 0o177616, // User I Page Descriptor Register 7
|
|
UDPDR0: 0o177620, // User D Page Descriptor Register 0
|
|
UDPDR1: 0o177622, // User D Page Descriptor Register 1
|
|
UDPDR2: 0o177624, // User D Page Descriptor Register 2
|
|
UDPDR3: 0o177626, // User D Page Descriptor Register 3
|
|
UDPDR4: 0o177630, // User D Page Descriptor Register 4
|
|
UDPDR5: 0o177632, // User D Page Descriptor Register 5
|
|
UDPDR6: 0o177634, // User D Page Descriptor Register 6
|
|
UDPDR7: 0o177636, // User D Page Descriptor Register 7
|
|
UIPAR0: 0o177640, // User I Page Address Register 0
|
|
UIPAR1: 0o177642, // User I Page Address Register 1
|
|
UIPAR2: 0o177644, // User I Page Address Register 2
|
|
UIPAR3: 0o177646, // User I Page Address Register 3
|
|
UIPAR4: 0o177650, // User I Page Address Register 4
|
|
UIPAR5: 0o177652, // User I Page Address Register 5
|
|
UIPAR6: 0o177654, // User I Page Address Register 6
|
|
UIPAR7: 0o177656, // User I Page Address Register 7
|
|
UDPAR0: 0o177660, // User D Page Address Register 0
|
|
UDPAR1: 0o177662, // User D Page Address Register 1
|
|
UDPAR2: 0o177664, // User D Page Address Register 2
|
|
UDPAR3: 0o177666, // User D Page Address Register 3
|
|
UDPAR4: 0o177670, // User D Page Address Register 4
|
|
UDPAR5: 0o177672, // User D Page Address Register 5
|
|
UDPAR6: 0o177674, // User D Page Address Register 6
|
|
UDPAR7: 0o177676, // User D Page Address Register 7
|
|
|
|
R0SET0: 0o177700, //
|
|
R1SET0: 0o177701, //
|
|
R2SET0: 0o177702, //
|
|
R3SET0: 0o177703, //
|
|
R4SET0: 0o177704, //
|
|
R5SET0: 0o177705, //
|
|
R6KERNEL: 0o177706, //
|
|
R7KERNEL: 0o177707, //
|
|
R0SET1: 0o177710, //
|
|
R1SET1: 0o177711, //
|
|
R2SET1: 0o177712, //
|
|
R3SET1: 0o177713, //
|
|
R4SET1: 0o177714, //
|
|
R5SET1: 0o177715, //
|
|
R6SUPER: 0o177716, //
|
|
R6USER: 0o177717, //
|
|
|
|
/*
|
|
* This next group of registers is largely ignored; all accesses are routed to regsControl[],
|
|
* and therefore are managed as a block of 8 "CTRL" registers.
|
|
*/
|
|
CTRL: 0o177740,
|
|
LAERR: 0o177740, // Low Address Error (11/70 only)
|
|
HAERR: 0o177742, // High Address Error (11/70 only)
|
|
MEMERR: 0o177744, // Memory System Error (11/70 only)
|
|
CACHEC: 0o177746, // Cache Control (11/70 only)
|
|
MAINT: 0o177750, // Maintenance (11/70 only)
|
|
HITMISS: 0o177752, // Hit/Miss (11/70 only)
|
|
UNDEF1: 0o177754,
|
|
UNDEF2: 0o177756,
|
|
|
|
LSIZE: 0o177760, // Lower Size Register (last 64-byte block #) (11/70 only)
|
|
HSIZE: 0o177762, // Upper Size Register (always zero) (11/70 only)
|
|
SYSID: 0o177764, // System ID Register (11/70 only)
|
|
CPUERR: 0o177766, // CPU error (11/70 only)
|
|
MB: 0o177770, // Microprogram break (11/70 only)
|
|
PIR: 0o177772, // Program Interrupt Request
|
|
SL: 0o177774, // Stack Limit Register
|
|
PSW: 0o177776 // 777776 17777776 0x3FFFFE Processor Status Word
|
|
},
|
|
DL11: { // Serial Line Interface (program compatible with the KL11 for control of console teleprinters)
|
|
PRI: 4,
|
|
RVEC: 0o060,
|
|
XVEC: 0o064,
|
|
RCSR: { // 177560: DL11 Receiver Status Register
|
|
RE: 0x0001, // Reader Enable (W/O)
|
|
DTR: 0x0002, // Data Terminal Ready (R/W)
|
|
RTS: 0x0004, // Request To Send (R/W)
|
|
STD: 0x0008, // Secondary Transmitted Data (R/W)
|
|
DIE: 0x0020, // Dataset Interrupt Enable (R/W)
|
|
RIE: 0x0040, // Receiver Interrupt Enable (R/W)
|
|
RD: 0x0080, // Receiver Done (R/O)
|
|
SRD: 0x0400, // Secondary Received Data (R/O)
|
|
RA: 0x0800, // Receiver Active (R/O)
|
|
CD: 0x1000, // Carrier Detect (R/O)
|
|
CTS: 0x2000, // Clear To Send (R/O)
|
|
RI: 0x4000, // Ring Indicator (R/O)
|
|
DSC: 0x8000, // Dataset Status Change (R/O)
|
|
RMASK: 0xFFFE, // bits readable (TODO: All I know for sure is that bit 0 is NOT readable; see readRCSR())
|
|
WMASK: 0x006F, // bits writable
|
|
BAUD: 9600
|
|
},
|
|
RBUF: { // 177562: DL11 Receiver Data Buffer Register
|
|
DATA: 0x00ff, // Received Data (R/O)
|
|
PARITY: 0x1000, // Received Data Parity (R/O)
|
|
FE: 0x2000, // Framing Error (R/O)
|
|
OE: 0x4000, // Overrun Error (R/O)
|
|
ERROR: 0x8000 // Error (R/O)
|
|
},
|
|
XCSR: { // 177564: DL11 Transmitter Status Register
|
|
BREAK: 0x0001, // BREAK (R/W)
|
|
MAINT: 0x0004, // Maintenance (R/W)
|
|
TIE: 0x0040, // Transmitter Interrupt Enable (R/W)
|
|
READY: 0x0080, // Transmitter Ready (R/O)
|
|
RMASK: 0x00C5,
|
|
WMASK: 0x0045,
|
|
BAUD: 9600
|
|
},
|
|
XBUF: { // 177566: DL11 Transmitter Data Buffer Register
|
|
DATA: 0x00FF // Transmitted Data (W/O) TODO: Determine why pdp11.js effectively defined this as 0x7F
|
|
}
|
|
},
|
|
KW11: { // KW11-L Line Time Clock (60Hz; well, OK, or 50Hz, if you're in the UK, I suppose...)
|
|
PRI: 6,
|
|
VEC: 0o100,
|
|
DELAY: 0,
|
|
LKS: { // 177546: KW11-L Clock Status
|
|
IE: 0x0040, // Interrupt Enable
|
|
MON: 0x0080, // Monitor
|
|
MASK: 0x00C0 // these are the only bits that can read or written
|
|
}
|
|
},
|
|
PC11: { // High Speed Reader & Punch (PR11 is a Reader-only unit)
|
|
PRI: 4, // NOTE: reader has precedence over punch
|
|
RVEC: 0o070, // reader vector
|
|
PVEC: 0o074, // punch vector
|
|
PRS: { // 177550: PC11 (and PR11) Reader Status Register
|
|
RE: 0x0001, // Reader Enable (W/O)
|
|
RIE: 0x0040, // Reader Interrupt Enable (allows the DONE and ERROR bits to trigger an interrupt)
|
|
DONE: 0x0080, // Done (R/O)
|
|
BUSY: 0x0800, // Busy (R/O)
|
|
ERROR: 0x8000, // Error (R/O)
|
|
CLEAR: 0x08C0, // bits cleared on INIT
|
|
RMASK: 0xFFFE, // bits readable (TODO: All I know for sure is that bit 0 is NOT readable; see readPRS())
|
|
WMASK: 0x0041, // bits writable
|
|
BAUD: 3600
|
|
},
|
|
PRB: { // 177552: PC11 (and PR11) Reader Buffer Register
|
|
MASK: 0x00FF // Data
|
|
},
|
|
PPS: { // 177554: PC11 Punch Status Register
|
|
/*
|
|
* TODO: Flesh this out if/when we add Paper Tape Punch support
|
|
*/
|
|
BAUD: 600
|
|
},
|
|
PPB: { // 177556: PC11 Punch Buffer Register
|
|
/*
|
|
* TODO: Flesh this out if/when we add Paper Tape Punch support
|
|
*/
|
|
}
|
|
},
|
|
RK11: { // RK11 Disk Controller
|
|
PRI: 5,
|
|
VEC: 0o220,
|
|
RKDS: { // 177400: Drive Status Register
|
|
SC: 0x000F, // Sector Counter
|
|
SCESA: 0x0010, // Sector Counter Equals Sector Address
|
|
WPS: 0x0020, // Write Protected Status (set if write-protected)
|
|
RRDY: 0x0040, // Read/Write/Seek Ready
|
|
DRDY: 0x0080, // Drive Ready
|
|
SOK: 0x0100, // Sector Counter OK
|
|
SIN: 0x0200, // Seek Incomplete
|
|
DRU: 0x0400, // Drive Unsafe
|
|
RK05: 0x0800, // RK05 is the selected disk drive (always set)
|
|
DPL: 0x1000, // Drive Power Low
|
|
ID: 0xE000, // Drive ID (logical drive number of an interrupting drive)
|
|
SHIFT: {
|
|
ID: 13
|
|
}
|
|
},
|
|
RKER: { // 177402: Error Register
|
|
WCE: 0x0001, // Write Check Error
|
|
CSE: 0x0002, // Checksum Error
|
|
UNUSED: 0x001C, // unused (returns zero)
|
|
NXS: 0x0020, // Non-Existent Sector
|
|
NXC: 0x0040, // Non-Existent Cylinder
|
|
NXD: 0x0080, // Non-Existent Disk
|
|
TE: 0x0100, // Timing Error
|
|
DLT: 0x0200, // Date Late
|
|
NXM: 0x0400, // Non-Existent Memory
|
|
PGE: 0x0800, // Programming Error
|
|
SKE: 0x1000, // Seek Error
|
|
WLO: 0x2000, // Write Lock-Out Violation
|
|
OVR: 0x4000, // Overrun
|
|
DRE: 0x8000 // Drive Error
|
|
},
|
|
RKCS: { // 177404: Control Status Register
|
|
GO: 0x0001, // Go (W/O)
|
|
FUNC: 0x000E, // Function Code (F2,F1,F0) (R/W)
|
|
MEX: 0x0030, // Memory Extension (R/W)
|
|
IE: 0x0040, // Interrupt Enable (R/W)
|
|
CRDY: 0x0080, // Controller Ready (R/O)
|
|
SSE: 0x0100, // Stop on Soft Error (R/W)
|
|
EXB: 0x0200, // Extra Bit (R/W)
|
|
FMT: 0x0400, // Format (R/W)
|
|
IBA: 0x0800, // Inhibit RKBA Increment (R/W)
|
|
SCP: 0x2000, // Search Complete (R/O)
|
|
HE: 0x4000, // Hard Error (R/O)
|
|
ERR: 0x8000, // Composite Error (R/O) (set when any RKER bit is set)
|
|
UNUSED: 0x1200, // unused
|
|
RMASK: 0xEFFE, // bits readable
|
|
WMASK: 0x0F7F, // bits writable
|
|
SHIFT: {
|
|
FUNC: 1,
|
|
MEX: 4
|
|
}
|
|
},
|
|
RKDA: { // 177412: Disk Address Register
|
|
SA: 0x000F, // Sector Address
|
|
HS: 0x0010, // Head Select (aka SUR: clear for upper disk head, set for lower)
|
|
CA: 0x1FE0, // Cylinder Address (aka CYL ADDR)
|
|
DS: 0xE000, // Drive Select (aka DR SEL)
|
|
SHIFT: {
|
|
HS: 4,
|
|
CA: 5,
|
|
DS: 13
|
|
}
|
|
},
|
|
FUNC: { // NOTE: These function codes are pre-shifted to read/write directly from/to RKCS.FUNC
|
|
CRESET: 0b0000, // Controller Reset
|
|
WRITE: 0b0010, // Write
|
|
READ: 0b0100, // Read
|
|
WCHK: 0b0110, // Write Check
|
|
SEEK: 0b1000, // Seek
|
|
RCHK: 0b1010, // Read Check
|
|
DRESET: 0b1100, // Drive Reset
|
|
WLOCK: 0b1110 // Write Lock
|
|
}
|
|
},
|
|
RL11: { // RL11 Disk Controller
|
|
PRI: 5,
|
|
VEC: 0o160,
|
|
RLCS: { // Control Status Register (174400)
|
|
DRDY: 0x0001, // Drive Ready (R/O)
|
|
FUNC: 0x000E, // Function Code (F2,F1,F0) (R/W)
|
|
BAE: 0x0030, // Bus Address Extension bits (BA17,BA16) (R/W)
|
|
IE: 0x0040, // Interrupt Enable (R/W)
|
|
CRDY: 0x0080, // Controller Ready (R/W)
|
|
DS: 0x0300, // Drive Select (DS1,DS0) (R/W)
|
|
ERRC: 0x3C00, // Error Code (R/O)
|
|
DE: 0x4000, // Drive Error (R/O)
|
|
ERR: 0x8000, // Composite Error (R/O)
|
|
CLEAR: 0x3F7E, // bits cleared on INIT (bits 1-6 and 8-13 are cleared)
|
|
SET: 0x0080, // bits set on INIT (bit 7 is set)
|
|
RMASK: 0xFFFF, // no write-only bits
|
|
WMASK: 0x03FE, // bits writable
|
|
SHIFT: {
|
|
FUNC: 1,
|
|
BAE: 4,
|
|
DS: 8
|
|
}
|
|
},
|
|
RLBA: { // Bus Address Register (174402)
|
|
WMASK: 0xFFFE // bit 0 is effectively not writable (always zero)
|
|
},
|
|
/*
|
|
* This register has 3 formats: one for Seek, another for Read/Write, and a third for Get Status
|
|
*/
|
|
RLDA: { // Disk Address Register (174404)
|
|
SEEK_CMD: 0x0001, // Seek: bit 0 must be set, bits 1 and 3 must be clear
|
|
SEEK_DIR: 0x0004, // Direction (clear to move heads away from spindle (lower cylinder), set to move to higher cylinder)
|
|
SEEK_HS: 0x0010, // Head Select (clear to select upper head, set to select lower head)
|
|
SEEK_CAD: 0xFF80, // Cylinder Address Difference
|
|
RW_SA: 0x003F, // Sector Address
|
|
RW_HS: 0x0040, // Head Select
|
|
RW_CA: 0xFF80, // Cylinder Address (RL01 has 256 cylinders, RL02 has 512)
|
|
GS_CMD: 0x0003, // Get Status: bit 0 must be set, bit 1 set, and bits 2 and 4-7 clear (bits 8-15 unused)
|
|
GS_RST: 0x0008, // Reset (when set, clears error register before sending status word to controller)
|
|
SHIFT: {
|
|
RW_HS: 6,
|
|
RW_CA: 7
|
|
}
|
|
},
|
|
/*
|
|
* This register has 3 formats: one for Read Header, another for Read/Write, and a third for Get Status
|
|
*/
|
|
RLMP: { // Multi-Purpose Register (177406)
|
|
GS_ST: { // Major State Code (of the drive)
|
|
LOADC: 0x0, // Load Cartridge
|
|
SPINUP: 0x1, // Spin-Up
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BRUSHC: 0x2, // Brush Cycle
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LOADH: 0x3, // Load Heads
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SEEK: 0x4, // Seek
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LOCKON: 0x5, // Lock On
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UNLOADH:0x6, // Unload Heads
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|
SPINDN: 0x7 // Spin-Down
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|
},
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GS_BH: 0x0008, // Brushes Home
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GS_HO: 0x0010, // Heads Out
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GS_CO: 0x0020, // Cover Open (or dust cover is not in place)
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GS_HS: 0x0040, // Head Selected (0 for upper head, 1 for lower head)
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GS_DT: 0x0080, // Drive Type (0 for RL01, 1 for RL02)
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GS_DSE: 0x0100, // Drive Select Error
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GS_VC: 0x0200, // Volume Check (Set during transition from a head load state to a head-on-track state; cleared by execution of a Get Status command with Bit 3 asserted)
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GS_WGE: 0x0400, // Write Gate Error
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|
GS_SPE: 0x0800, // Spin Error
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|
GS_SKTO: 0x1000, // Seek Time-Out
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|
GS_WL: 0x2000, // Write Lock
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GS_CHE: 0x4000, // Current Head Error
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|
GS_WDE: 0x8000 // Write Data Error
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|
},
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|
RLBE: { // Bus (Address) Extension Register (174410)
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MASK: 0x003F // bits 5-0 correspond to bus address bits 21-16
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|
},
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|
ERRC: { // NOTE: These error codes are pre-shifted to read/write directly from/to RLCS.ERRC
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|
OPI: 0x0400, // Operation Incomplete
|
|
DCRC: 0x0800, // Read Data CRC
|
|
WCE: 0x0800, // Write Check Error
|
|
HCRC: 0x0C00, // Header CRC
|
|
DLT: 0x1000, // Data Late
|
|
HNF: 0x1400, // Header Not Found
|
|
NXM: 0x2000, // Non-Existent Memory
|
|
MPE: 0x2400 // Memory Parity Error (RLV12 only)
|
|
},
|
|
FUNC: { // NOTE: These function codes are pre-shifted to read/write directly from/to RLCS.FUNC
|
|
NOP: 0b0000, // No-Op
|
|
WCHK: 0b0010, // Write Check
|
|
STATUS: 0b0100, // Get Status
|
|
SEEK: 0b0110, // Seek
|
|
RHDR: 0b1000, // Read Header
|
|
WDATA: 0b1010, // Write Data
|
|
RDATA: 0b1100, // Read Data
|
|
RDNC: 0b1110 // Read Data without Header Check
|
|
}
|
|
},
|
|
VECTORS: {
|
|
0o060: "DL11.RCSR",
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|
0o064: "DL11.XCSR",
|
|
0o070: "PC11.PRS",
|
|
0o074: "PC11.PPS",
|
|
0o100: "KW11",
|
|
0o160: "RL11",
|
|
0o220: "RK11"
|
|
}
|
|
};
|
|
|
|
PDP11.ACCESS.READ_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.READ; // formerly READ_MODE (2)
|
|
PDP11.ACCESS.READ_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.READ; // formerly READ_MODE (2) | BYTE_MODE (1)
|
|
PDP11.ACCESS.WRITE_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.WRITE; // formerly WRITE_MODE (4)
|
|
PDP11.ACCESS.WRITE_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.WRITE; // formerly WRITE_MODE (4) | BYTE_MODE (1)
|
|
PDP11.ACCESS.UPDATE_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.UPDATE; // formerly MODIFY_WORD (2 | 4)
|
|
PDP11.ACCESS.UPDATE_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.UPDATE; // formerly MODIFY_BYTE (1 | 2 | 4)
|
|
|
|
/*
|
|
* PSW arithmetic flags are NOT stored directly into the PSW register; they are maintained across separate
|
|
* flag registers.
|
|
*/
|
|
PDP11.PSW.FLAGS = (PDP11.PSW.NF | PDP11.PSW.ZF | PDP11.PSW.VF | PDP11.PSW.CF);
|
|
|
|
if (NODE) {
|
|
global.APPCLASS = APPCLASS;
|
|
global.APPNAME = APPNAME;
|
|
global.DEBUGGER = DEBUGGER;
|
|
global.BYTEARRAYS = BYTEARRAYS;
|
|
global.TYPEDARRAYS = TYPEDARRAYS;
|
|
global.PDP11 = PDP11;
|
|
|
|
module.exports = PDP11;
|
|
}
|