127 lines
5.5 KiB
JavaScript
127 lines
5.5 KiB
JavaScript
/**
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* @fileoverview Defines PC8080 CPU constants.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @copyright © Jeff Parsons 2012-2017
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*
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* This file is part of PCjs, a computer emulation software project at <http://pcjs.org/>.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every modified copy of this work
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* and to display that copyright notice when the software starts running; see COPYRIGHT in
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* <http://pcjs.org/modules/shared/lib/defines.js>.
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of PCjs
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* for purposes of the GNU General Public License, and the author does not claim any copyright
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* as to their contents.
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*/
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"use strict";
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var CPUDef8080 = {
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/*
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* CPU model numbers (supported)
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*/
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MODEL_8080: 8080,
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/*
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* This constant is used to mark points in the code where the physical address being returned
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* is invalid and should not be used.
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*
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* In a 32-bit CPU, -1 (ie, 0xffffffff) could actually be a valid address, so consider changing
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* ADDR_INVALID to NaN or null (which is also why all ADDR_INVALID tests should use strict equality
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* operators).
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*
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* The main reason I'm NOT using NaN or null now is my concern that, by mixing non-numbers
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* (specifically, values outside the range of signed 32-bit integers), performance may suffer.
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*
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* WARNING: Like many of the properties defined here, ADDR_INVALID is a common constant, which the
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* Closure Compiler will happily inline (with or without @const annotations; in fact, I've yet to
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* see a @const annotation EVER improve automatic inlining). However, if you don't make ABSOLUTELY
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* certain that this file is included BEFORE the first reference to any of these properties, that
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* automatic inlining will no longer occur.
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*/
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ADDR_INVALID: -1,
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/*
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* Processor Status flag definitions (stored in regPS)
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*/
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PS: {
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CF: 0x0001, // bit 0: Carry Flag
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BIT1: 0x0002, // bit 1: reserved, always set
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PF: 0x0004, // bit 2: Parity Flag
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BIT3: 0x0008, // bit 3: reserved, always clear
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AF: 0x0010, // bit 4: Auxiliary Carry Flag
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BIT5: 0x0020, // bit 5: reserved, always clear
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ZF: 0x0040, // bit 6: Zero Flag
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SF: 0x0080, // bit 7: Sign Flag
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ALL: 0x00D5, // all "arithmetic" flags (CF, PF, AF, ZF, SF)
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MASK: 0x00FF, //
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IF: 0x0200 // bit 9: Interrupt Flag (set if interrupts enabled; Intel calls this the INTE bit)
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},
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PARITY: [ // 256-byte array with a 1 wherever the number of set bits of the array index is EVEN
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
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],
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/*
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* Interrupt-related flags (stored in intFlags)
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*/
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INTFLAG: {
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NONE: 0x0000,
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INTR: 0x00ff, // mask for 8 bits, representing interrupt levels 0-7
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HALT: 0x0100 // halt requested; see opHLT()
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},
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/*
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* Opcode definitions
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*/
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OPCODE: {
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HLT: 0x76, // Halt
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ACI: 0xCE, // Add with Carry Immediate (affects PS.ALL)
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CALL: 0xCD, // Call
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RST0: 0xC7
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// to be continued....
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}
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};
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/*
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* These are the internal PS bits (outside of PS.MASK) that getPS() and setPS() can get and set,
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* but which cannot be seen with any of the documented instructions.
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*/
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CPUDef8080.PS.INTERNAL = (CPUDef8080.PS.IF);
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/*
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* PS "arithmetic" flags are NOT stored in regPS; they are maintained across separate result registers,
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* hence the RESULT designation.
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*/
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CPUDef8080.PS.RESULT = (CPUDef8080.PS.CF | CPUDef8080.PS.PF | CPUDef8080.PS.AF | CPUDef8080.PS.ZF | CPUDef8080.PS.SF);
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/*
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* These are the "always set" PS bits for the 8080.
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*/
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CPUDef8080.PS.SET = (CPUDef8080.PS.BIT1);
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module.exports = CPUDef8080;
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