645 lines
19 KiB
NASM
645 lines
19 KiB
NASM
; Posted in comp.sys.ibm.pc by Michael A. Shiels 8/16/89
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; From https://groups.google.com/forum/#!searchin/comp.sys.ibm.pc/single-step$20interrupt/comp.sys.ibm.pc/irWPIdzmCHQ/SyqEtq9mqCEJ
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title CPUID - Determine CPU & NDP Type
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page 58,122
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name CPUID
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;
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; CPUID uniquely identifies each NEC & Intel CPU & NDP.
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;
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; Notes on program structure:
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;
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; This program uses four segments, two classes, and one group.
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; It demonstrates a useful technique for programmers who generate
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; .COM programs. In particular, it shows how to use segment
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; classes to re-order segments, and how to eliminate the linker's
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; warning message about the absence of a stack segment.
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;
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; The correspondence between segments and classes is as follows:
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;
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; Segment Class
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; ------- -----
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; STACK prog
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; DATA data
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; MDATA data
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; CODE prog
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;
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; The segments apprear in the above order in the program source
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; to avoid forward references in the CODE segment to labels in
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; the DATA/MDATA segments. However, because the STACK segment
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; appears first in the file, it and all segments in the same
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; class are made contiguous by the linker. Thus they precede
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; the DATA/MDATA segments in the resulting .COM file because
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; the latter are in a different class. In this manner, although
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; DATA and MDATA precede CODE in the source file, their order
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; is swapped in the .COM file. That way there is no need for
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; an initial skip over the data areas to get to the CODE
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; segment. As a side benefit, declaring a STACK segment (as
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; the first segment in the source) also eliminates the linker's
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; warning about that segment missing. Finally, all segments
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; are declared to be in the same group so the linker can properly
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; resolve offsets.
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;
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; Note that if you re-assemble the code for any reason, it is
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; important to use an assembler later than the IBM version 1.0.
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; That version has a number of bugs including an annoying habit
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; of alphabetizing segment names in the .OBJ file. If you use
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; IBM MASM 2.0, be sure to specify /S to order the segments
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; properly.
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;
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; If the program reports results at variance with your knowledge
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; of the system, please contact the author.
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;
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; Environments tested in:
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;
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; CPU Speed
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; System in MHz CPU NDP
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; ------ --------- --- ---
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; IBM PC AT 6 Intel 80286 Intel 80287
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; IBM PC AT 9 Intel 80286 Intel 80287
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; IBM PC AT 6 Intel 80286 none
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; IBM PC AT 8.5 Intel 80286 none
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; IBM PC 4.77 Intel 8088 Intel 8087-3
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; IBM PC 4.77 Intel 8088* Intel 8087-3
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; IBM PC XT 4.77 Intel 8088 none
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; IBM PC XT 4.77 Intel 8088 Intel 8087-3
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; IBM PC Portable 4.77 NEC V20 none
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; COMPAQ 4.77 Intel 8088 none
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; COMPAQ 4.77 NEC V20 none
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; AT&T PC 6300 8 Intel 8086 Intel 8087-2
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; AT&T PC 6300 8 NEC V30 Intel 8087-2
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; Tandy 2000 8 Intel 80186 none
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;
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; * = faulty CPU
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;
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; Program structure:
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;
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; Group PGROUP:
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; Stack segment STACK, byte-aligned, stack, class 'prog'
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; Program segment CODE, byte-aligned, public, class 'prog'
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; Data segment DATA, byte-aligned, public, class 'data'
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; Data segment MDATA, byte-aligned, public, class 'data'
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;
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; Assembly requirements:
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;
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; Use MASM 1.25 or later.
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; With IBM's MASM 2.0 only, use /S to avoid alphabetizing the segment names.
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; Use /r option to generate real NDP code.
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;
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; MASM CPUID/r; to convert .ASM to .OBJ
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; LINK CPUID; to convert .OBJ to .EXE
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; EXE2BIN CPUID CPUID.COM to convert .EXE to .COM
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; ERASE CPUID.EXE to avoid executing .EXE
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;
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; Note that the linker doesn't warn about a missing stack segment.
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;
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; Author:
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;
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; Original code by:
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;
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; Bob Smith May 1985
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; Qualitas, Inc.
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; 8314 Thoreau Dr.
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; Bethesda, MD 20817
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;
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; Arthur Zachai suggested the technique to distinguish within the
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; 808x and 8018x families by exploiting the difference in the
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; length of their pre-fetch instruction queues.
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;
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; Published in PC Tech Journal - April 1986 - Vol 4 No 4
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;
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subttl Structures, Records, Equates, & Macros
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page
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ARG_STR struct
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ARG_BP dw ? ; caller's BP
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ARG_OFF dw ? ; caller's offset
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ARG_SEG dw ? ; segment
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ARG_FLG dw ? ; flags
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ARG_STR ends
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; Record to define bits in the CPU's & NDP's flags' registers
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CPUFLAGS record RO:1,NT:1,IOPL:2,OF:1,_DF:1,_IF:1,TF:1,SF:1,ZF:1,R1:1,AF:1,R2:1,PF:1,R3:1,CF:1
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NDPFLAGS record R4:3,IC:1,RC:2,PC:2,IEM:1,R5:1,PM:1,UM:1,OM:1,ZM:1,DM:1,IM:1
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; FLG_PIQL Pre-fetch instruction queue length, 0 => 4-byte, 1 => 6-byte
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; FLG_08 Intel 808x
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; FLG_NEC NEC V20 or V30
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; FLG_18 Intel 8018x
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; FLG_28 Intel 8028x
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; FLG_87 Intel 8087
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; FLG_287 Intel 80287
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;
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; FLG_CERR Faulty CPU
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; FLG_NERR Faulty NDP switch setting
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FLG record RSVD:9,FLG_NERR:1,FLG_CERR:1,FLG_NDP:2,FLG_CPU:3
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; CPU-related flags
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FLG_PIQL equ 001b shl FLG_CPU
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FLG_08 equ 000b shl FLG_CPU
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FLG_NEC equ 010b shl FLG_CPU
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FLG_18 equ 100b shl FLG_CPU
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FLG_28 equ 110b shl FLG_CPU
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FLG_8088 equ FLG_08
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FLG_8086 equ FLG_08 or FLG_PIQL
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FLG_V20 equ FLG_NEC
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FLG_v30 equ FLG_NEC or FLG_PIQL
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FLG_80188 equ FLG_18
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FLG_80186 equ FLG_18 or FLG_PIQL
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FLG_80286 equ FLG_28 or FLG_PIQL
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; NDP-related flags
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; 00b shl FLG_NDP Not Present
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FLG_87 equ 01b shl FLG_NDP
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FLG_287 equ 10b shl FLG_NDP
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BEL equ 07h
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LF equ 0ah
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CR equ 0dh
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EOS equ '$'
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POPFF macro
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local L1,L2
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jmp short L2 ; skip over IRET
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L1:
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iret ; pop the CP & IP pushed below along
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; with the flags, our original purpose
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L2:
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push cs ; prepare for IRET by pushing CS
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call L1 ; push IP, jump to IRET
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endm ; POPFF macro
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TAB macro TYP
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push bx ; save for a moment
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and bx,mask FLG_&TYP ; isolate flags
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mov cl,FLG_&TYP ; shift amount
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shr bx,cl ; shift to low-order
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shl bx,1 ; times two to index table of words
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mov dx,TYP&MSG_TAB[bx] ; ds:dx => descriptive message
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pop bx ; restore
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mov ah,09h ; function code to display string
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int 21h ; request dos service
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endm ; TAB macro
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page
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INT_VEC segment at 0 ; start INT_VEC segment
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dd ? ; pointer to INT 00h
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INT01_OFF dw ? ; pointer to INT 01h
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INT01_SEG dw ?
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INT_VEC ends ; end INT_VEC segment
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PGROUP group STACK,CODE,DATA,MDATA
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; The following segment both positions class 'prog' segments lower in
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; memory than others so the first byte of the resulting .COM file is
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; in the CODE segment, as well as satisfies the LINKer's need to have
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; a stack segment.
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STACK segment byte stack 'prog' ; start STACK segment
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STACK ends ; end STACK segment
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I11_REC record I11_PRN:2,I11_RSV1:2,I11_COM:3,I11_RSV2:1,I11_DISK:2,I11_VID:2,I11_RSV3:2,I11_NDP:1,I11_IPL:1
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DATA segment byte public 'data' ; start DATA segment
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assume ds:PGROUP
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OLDINT01_VEC label dword ; save area for original INT 01h handler
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OLDINT01_OFF dw ?
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OLDINT01_SEG dw ?
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NDP_CW label word ; save area for NDP control word
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db ?
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NDP_CW_HI db 0 ; high byte of control word
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NDP_ENV dw 7 dup(?) ; save area for NDP environment
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DATA ends
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subttl Message Data Area
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page
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MDATA segment byte public 'data' ; start MDATA segment
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assume ds:PGROUP
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MSG_START db 'CPUID -- Version 1.0'
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db CR,LF,CR,LF,EOS
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MSG_8088 db 'CPU is an Intel 8088.'
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db CR,LF,EOS
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MSG_8086 db 'CPU is an Intel 8086.'
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db CR,LF,EOS
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MSG_V20 db 'CPU is an NEC V20.'
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db CR,LF,EOS
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MSG_V30 db 'CPU is an NEC V30.'
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db CR,LF,EOS
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MSG_80188 db 'CPU is an Intel 80188.'
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db CR,LF,EOS
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MSG_80186 db 'CPU is an Intel 80186.'
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db CR,LF,EOS
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MSG_UNK db 'CPU is a maverick -- 80288??.'
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db CR,LF,EOS
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MSG_80286 db 'CPU is an Intel 80286.'
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db CR,LF,EOS
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CPUMSG_TAB dw PGROUP:MSG_8088 ; 000 = Intel 8088
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dw PGROUP:MSG_8086 ; 001 = Intel 8086
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dw PGROUP:MSG_V20 ; 010 = NEC V20
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dw PGROUP:MSG_V30 ; 011 = NEC V30
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dw PGROUP:MSG_80188 ; 100 = Intel 80188
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dw PGROUP:MSG_80186 ; 101 = Intel 80186
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dw PGROUP:MSG_UNK ; 110 = ?
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dw PGROUP:MSG_80286 ; 111 = Intel 80286
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NDPMSG_TAB dw PGROUP:MSG_NDPX ; 00 = No NDP
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dw PGROUP:MSG_8087 ; 01 = Intel 8087
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dw PGROUP:MSG_80287 ; 10 = Intel 80287
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MSG_NDPX db 'NDP is not present.'
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db CR,LF,EOS
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MSG_8087 db 'NDP is an Intel 8087.'
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db CR,LF,EOS
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MSG_80287 db 'NDP is an Intel 80287.'
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db CR,LF,EOS
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CERRMSG_TAB dw PGROUP:MSG_CPUOK ; 0 = CPU healthy
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dw PGROUP:MSG_CPUBAD ; 1 = CPU faulty
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MSG_CPUOK db 'CPU appears to be healthy.'
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db CR,LF,EOS
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MSG_CPUBAD db BEL,'*** CPU incorrectly allows interrupts '
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db 'after a change to SS ***',CR,LF
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db 'It should be replaced with a more recent '
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db 'version as it could crash the',CR,LF
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db 'system at seemingly random times.',CR,LF,EOS
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NERRMSG_TAB dw PGROUP:MSG_NDPSWOK ; 0 = NDP switch set correctly
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dw PGROUP:MSG_NDPSWERR ; 1 = NDP switch set incorrectly
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MSG_NDPSWOK db EOS ; no message
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MSG_NDPSWERR db '*** Although there is an NDP installed '
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db 'on this sytem, the corresponding',CR,LF
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db 'system board switch is not properly set. '
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db 'To correct this, flip switch 2 of',CR,LF
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db 'switch block 1 on the system board.',CR,LF,EOS
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MDATA ends ; end MDATA segment
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subttl Main Routine
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page
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CODE segment byte public 'prog' ; start CODE segment
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assume cs:PGROUP,ds:PGROUP,es:PGROUP
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org 100h ; skip over PSP
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INITIAL proc near
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mov dx,offset ds:MSG_START ; starting message
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mov ah,09h ; function code to display string
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int 21h ; request DOS service
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call CPU_ID ; check the CPU's identity
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TAB CPU ; display CPU results
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TAB NDP ; display NDP results
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TAB CERR ; display CPU ERR results
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TAB NERR ; display NDP ERR results
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ret ; return to DOS
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INITIAL endp ; end INITIAL procedure
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subttl CPU_ID Procedure
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page
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CPU_ID proc near ; start CPU_ID procedure
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assume cs:PGROUP,ds:PGROUP,es:PGROUP
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; This procedure determines the type of CPU and NDP (if any) in use.
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;
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; The possibilities include:
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;
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; Intel 8086
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; Intel 8088
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; NEC V20
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; NEC V30
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; Intel 80186
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; Intel 80188
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; Intel 80286
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; Intel 8087
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; Intel 80287
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;
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; Also checked is whether or not the CPU allows interrupts after
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; changing the SS register segment. If the CPU does, it is faulty
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; and should be replaced.
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;
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; Further, if an NDP is installed, non-AT machines should have a
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; system board switch set. Such a discrepancy is reported.
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;
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; On exit, BX contains flag settings (as defined in FLG record) which
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; the caller can check. For example, to test for an Intel 80286, use
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;
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; and bx,mask FLAG_CPU
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; cmp bx,FLG_80286
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; je ITSA286
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irp XX,<ax,cx,di,ds,es> ; save registers
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push XX
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endm
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; test for 80286 -- this CPU executes PUSH SP by first storing SP on
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; stack, then decrementing it. earlier CPU's decrement, THEN store.
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mov bx,FLG_28 ; assume it's a 286
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push sp ; only 286 pushes pre-push SP
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pop ax ; get it back
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cmp ax,sp ; check for same
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je CHECK_PIQL ; they are, so it's a 286
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; test for 80186/80188 -- 18xx and 286 CPU's mask shift/rotate
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; operations mod 32; earlier CPUs use all 8 bits of CL.
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mov bx,FLG_18 ; assume it's an 8018x
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mov cl,32+1 ; 18x masks shift counts mod 32
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; note we can't use just 32 in CL
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mov al,0ffh ; start with all bits set
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shl al,cl ; shift one position if 18x
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jnz CHECK_PIQL ; some bits still on,
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; so its a 18x, check PIQL
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; test for V20
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mov bx,FLG_NEC ; assume it's an NEC V-series CPU
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call CHECK_NEC ; see if it's an NEC chip
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jcxz CHECK_PIQL ; good guess, check PIQL
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mov bx,FLG_08 ; it's an 808x
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subttl Check Length of Pre-Fetch Instruction Queue
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page
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; Check the length of the pre-fetch instruction queue (PIQ).
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;
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; xxxx6 CPUs have a PIQ length of 6 bytes,
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; xxxx8 CPUs have a PIQ length of 4 bytes
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;
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; Self-modifying code is used to distinguish the two PIQ lengths.
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CHECK_PIQL:
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call PIQL_SUB ; handle via subroutine
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jcxz CHECK_ERR ; if CX is 0, INC was not executed,
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; hence PIQ length is 4
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or bx,FLG_PIQL ; PIQ length is 6
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subttl Check for Allowing Interrupts After POP SS
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page
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; Test for faulty chip (allows interrupts after change to SS register)
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CHECK_ERR:
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xor ax,ax ; prepare to address
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; interrupt vector segment
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mov ds,ax ; DS points to segment 0
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assume ds:INT_VEC ; tell the assembler
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cli ; nobody move while we swap
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mov ax,offset cs:INT01 ; point to our own handler
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xchg ax,INT01_OFF ; get and swap offset
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mov OLDINT01_OFF,ax ; save to restore later
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mov ax,cs ; our handler's segment
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xchg ax,INT01_SEG ; get and swap segment
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mov OLDINT01_SEG,ax ; save to restore later
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; note we continue with interrupts disabled to avoid
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; an external interrupt occuring during this test
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mov cx,1 ; initialize a register
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push ss ; save ss to store back into itself
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pushf ; move flags
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pop ax ; ... into ax
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or ax,mask TF ; set trap flag
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push ax ; place onto stack
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POPFF ; ... and then into effect
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; some CPUs affect the trap flag
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; immediately, some
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; wait one instruction
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nop ; allow interrupt to take effect
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POST_NOP:
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pop ss ; change the stack segment register
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; (to itself)
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dec cx ; normal cpu's execute this instruction
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; before recognizing the single-step
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; interrupt
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hlt ; we never get here
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INT01:
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; Note: IF=TF=0
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; If we're stopped at or before POST_NOP, continue on
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push bp ; prepare to address the stack
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mov bp,sp ; hello, Mr. stack
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cmp [bp].ARG_STR.ARG_OFF,offset cs:POST_NOP ; check offset
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pop bp ; restore
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ja INTO1_DONE ; we're done
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iret ; return to caller
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INTO1_DONE:
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; restore old INT 01h handler
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les ax,OLDINT01_VEC ; ES:AX ==> old INT 01h handler
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assume es:nothing ; tell the assembler
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mov INT01_OFF,ax ; restore offset
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mov INT01_SEG,es ; ... and segment
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sti ; allow interrupts again (IF=1)
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add sp,3*2 ; strip IP, CS, and flags from stack
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push cs ; setup DS for code below
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pop ds
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assume ds:PGROUP ; tell the assembler
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jcxz CHECK_NDP ; if cx is 0, the dec cx was executed,
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; and the cpu is ok
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or bx,mask FLG_CERR ; it's a faulty chip
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subttl Check For Numeric Data Processor
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page
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; Test for a Numeric Data Processor -- Intel 8087 or 80287. The
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; technique used is passive -- it leaves the NDP in the same state in
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; which it is found.
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CHECK_NDP:
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cli ; protect FNSTENV
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fnstenv NDP_ENV ; if NDP present, save
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; current environment,
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; otherwise, this instruction
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; is ignored
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mov cx,50/7 ; cycle this many times
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loop $ ; wait for result to be stored
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sti ; allow interrupts
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fninit ; initialize processor to known state
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jmp short $+2 ; wait for initialization
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fnstcw NDP_CW ; save control word
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jmp short $+2 ; wait for result to be stored
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jmp short $+2
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cmp NDP_CW_HI,03h ; check for NDP initial control word
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jne CPUID_EXIT ; no NDP installed
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int 11h ; get equipment flags into ax
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test ax,mask I11_NDP ; check NDP-installed bit
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|
jnz CHECK_NDP1 ; it's correctly set
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|
or bx,mask FLG_NERR ; mark as in error
|
|
|
|
CHECK_NDP1:
|
|
and NDP_CW,not mask IEM ; enable interrupts
|
|
; (IEM=0, 8087 only)
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|
fldcw NDP_CW ; reload control word
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|
fdisi ; disable interrupts (IEM=1) on 8087,
|
|
; ignored by 80287
|
|
fstcw NDP_CW ; save control word
|
|
fldenv NDP_ENV ; restore original NDP environment
|
|
; no need to wait
|
|
; for environment to be loaded
|
|
test NDP_CW,mask IEM ; check interrupt enable mask
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|
; (8087 only)
|
|
jnz CPUID_8087 ; it changed, hence NDP is an 8087
|
|
or bx,FLG_287 ; NDP is an 80287
|
|
jmp short CPUID_EXIT ; exit with falgs in BX
|
|
|
|
CPUID_8087:
|
|
or bx,FLG_87 ; NDP is an 8087
|
|
|
|
CPUID_EXIT:
|
|
irp XX,<es,ds,di,cx,ax> ; restore registers
|
|
pop XX
|
|
endm
|
|
|
|
assume ds:nothing,es:nothing
|
|
ret ; return to caller
|
|
CPU_ID endp ; end CPU_ID procedure
|
|
|
|
subttl Check For NEC V20/V30
|
|
page
|
|
|
|
CHECK_NEC proc near
|
|
|
|
; The NEC V20/V30 are very compatible with the Intel 8086/8088.
|
|
; The only point of "incompatibility" is that they do not contain
|
|
; a bug found in the Intel CPU's. Specifically, the NEC CPU's
|
|
; correctly restart an interrupted multi-prefix string instruction
|
|
; at the start of the instruction. The Intel CPU's incorrectly
|
|
; restart in the middle of the instruction. This routine tests
|
|
; for that situation by executing such an instruction for a
|
|
; sufficiently long period of time for a timer interrupt to occur.
|
|
; If at the end of the instruction, CX is zero, it must be an NEC
|
|
; CPU; if not, it's an Intel CPU.
|
|
;
|
|
; Note that we're counting on the timer interrupt to do its thing
|
|
; every 18.2 times per second.
|
|
;
|
|
; Here's a worst case analysis: An Intel 8088/8086 executes 65535
|
|
; iterations of LODSB ES[SI] in 2+9+13*65535 = 851,966 clock ticks.
|
|
; If the Intel 8088/8086 is running at 10 MHz, each clock tick is
|
|
; 100 nanoseconds, hence the entire operation takes 85 milliseconds.
|
|
; If the timer is running at normal speed, it interrupts the CPU every
|
|
; 55ms and so should interrupt the repeated string instruction at least
|
|
; once.
|
|
|
|
mov cx,0ffffh ; move a lot of data
|
|
sti ; ensure timer enabled
|
|
|
|
; execute multi-prefix instruction. note that the value of ES as
|
|
; well as the direction flag setting is irrelevant.
|
|
|
|
push ax ; save registers
|
|
push si
|
|
rep lods byte ptr es:[si]
|
|
pop si ; restore
|
|
pop ax
|
|
|
|
; on exit: if cx is zero, it's an NEC CPU, otherwise it's an Intel CPU
|
|
|
|
ret ; return to caller
|
|
CHECK_NEC endp
|
|
|
|
subttl Pre-Fetch Instruction Queue Subroutine
|
|
page
|
|
|
|
PIQL_SUB proc near
|
|
|
|
; This subroutine discerns the length of the CPU's pre-fetch
|
|
; instruction queue (PIQ).
|
|
;
|
|
; The technique used is to first ensure that the PIQ is full, then
|
|
; change an instruction which should be in a 6-byte PIQ but not in a
|
|
; 4-byte PIQ. Then, if the original instruction is executed, the PIQ
|
|
; is 6-bytes long; if the new instruction is executed, PIQ length is 4.
|
|
;
|
|
; We ensure the PIQ is full be executing an instruction which takes
|
|
; long enough so that the Bus Interface Unit (BIU) can fill the PIQ
|
|
; while the instruction is executing.
|
|
;
|
|
; Specifically, for all byt the last STOSB, we're simple marking time
|
|
; waiting for the BIU to fill the PIQ. The last STOSB actually changes
|
|
; the instruction. By that time, the orignial instruction should be in
|
|
; a six-byte PIQ byt not a four-byte PIQ.
|
|
|
|
assume cs:PGROUP,es:PGROUP
|
|
@REP equ 3 ; repeat the store this many times
|
|
std ; store backwards
|
|
mov di,offset es:LAB_INC+@REP-1 ; change the instructions
|
|
; at ES:DI
|
|
; and preceding
|
|
mov al,ds:LAB_STI ; change to a sti
|
|
mov cx,@REP ; give the BIU time
|
|
; to pre-fetch instructions
|
|
cli ; ensure interrupts are disabled,
|
|
; otherwise a timer tick
|
|
; could change the PIQ filling
|
|
rep stosb ; change the instruction
|
|
; during execution of this instruction
|
|
; the BIU is refilling the PIQ. The
|
|
; current instruction is no longer
|
|
; in the PIQ.
|
|
; Note at end, CX is 0.
|
|
; The PIQ begins filling here
|
|
|
|
cld ; restore direction flag
|
|
nop ; PIQ fillers
|
|
nop
|
|
nop
|
|
|
|
; The following instruction is beyond a four-byte-PIQ CPU's reach,
|
|
; but within that of a six-byte-PIQ CPU.
|
|
|
|
LAB_INC label byte
|
|
inc cx ; executed only if PIQ length is 6
|
|
|
|
LAB_STI label byte
|
|
rept @REP-1
|
|
sti ; restore interrupts
|
|
endm
|
|
|
|
ret ; return to caller
|
|
|
|
assume ds:nothing,es:nothing
|
|
PIQL_SUB endp ; end PIQL_SUB procedure
|
|
|
|
CODE ends ; end code segment
|
|
|
|
end INITIAL ; end CPU_ID module
|