124 lines
3.8 KiB
NASM
124 lines
3.8 KiB
NASM
;
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; The following code comes from:
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;
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; http://www.6502.org/tutorials/vflag.html
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;
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; and is built with:
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;
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; ca65 vflag.asm -I ../.. -l -o vflag.obj
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; ld65 vflag.obj -o vflag.bin --target none
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;
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; An ASCII hex file which the OSI machine-language monitor can load
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; is produced with the following commands:
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;
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; echo -n ".0200/" > vflag.txt
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; hexdump -e '1/1 "%02X\n"' -v vflag.bin >> vflag.txt
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; echo -n ".0200" >> vflag.txt
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;
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.include "sim.inc"
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; Demonstrate that the V flag works as described
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;
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; Returns with ERROR = 0 if the test passes, ERROR = 1 if the test fails
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;
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; Five (additional) memory locations are used: ERROR, S1, S2, U1, and U2
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; which can be located anywhere convenient in RAM
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;
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; The program below takes about 16 seconds to complete at 1 MHz.
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;
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TEST: CLD ; Clear decimal mode (just in case) for test
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LDA #1
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STA ERROR ; Store 1 in ERROR until test passes
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LDA #$80
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STA S1 ; Initalize S1 and S2 to -128 ($80)
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STA S2
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LDA #0
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STA U1 ; Initialize U1 and U2 to 0
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STA U2
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LDY #1 ; Initialize Y (used to set and clear the carry flag) to 1
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LOOP: JSR ADD ; Test ADC
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CPX #1
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BEQ ERR ; End if V and unsigned result do not agree (X = 1)
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JSR SUB ; Test SBC
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CPX #1
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BEQ ERR ; End if V and unsigned result do not agree (X = 1)
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INC S1
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INC U1
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BNE LOOP ; Loop until all 256 possibilities of S1 and U1 are tested
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INC S2
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INC U2
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BNE LOOP ; Loop until all 256 possibilities of S2 and U2 are tested
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DEY
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BPL LOOP ; Loop until both possiblities of the carry flag are tested
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LDA #0
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STA ERROR ; All tests pass, so store 0 in ERROR
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SIM_MSG "PASS"
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BEQ DONE
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ERR: SIM_MSG "FAIL"
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DONE: SIM_HLT
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;
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; Test ADC
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;
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; X is initialized to 0
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; X is incremented when V = 1
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; X is incremented when the unsigned result predicts an overflow
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; Therefore, if the V flag and the unsigned result agree, X will be
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; incremented zero or two times (returning X = 0 or X = 2), and if they do
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; not agree X will be incremented once (returning X = 1)
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;
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ADD: CPY #1 ; Set carry when Y = 1, clear carry when Y = 0
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LDA S1 ; Test twos complement addition
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ADC S2
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LDX #0 ; Initialize X to 0
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BVC ADD1
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INX ; Increment X if V = 1
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ADD1: CPY #1 ; Set carry when Y = 1, clear carry when Y = 0
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LDA U1 ; Test unsigned addition
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ADC U2
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BCS ADD3 ; Carry is set if U1 + U2 >= 256
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BMI ADD2 ; U1 + U2 < 256, A >= 128 if U1 + U2 >= 128
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INX ; Increment X if U1 + U2 < 128
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ADD2: RTS
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ADD3: BPL ADD4 ; U1 + U2 >= 256, A <= 127 if U1 + U2 <= 383 ($17F)
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INX ; Increment X if U1 + U2 > 383
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ADD4: RTS
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;
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; Test SBC
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;
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; X is initialized to 0
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; X is incremented when V = 1
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; X is incremented when the unsigned result predicts an overflow
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; Therefore, if the V flag and the unsigned result agree, X will be
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; incremented zero or two times (returning X = 0 or X = 2), and if they do
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; not agree X will be incremented once (returning X = 1)
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;
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SUB: CPY #1 ; Set carry when Y = 1, clear carry when Y = 0
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LDA S1 ; Test twos complement subtraction
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SBC S2
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LDX #0 ; Initialize X to 0
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BVC SUB1
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INX ; Increment X if V = 1
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SUB1: CPY #1 ; Set carry when Y = 1, clear carry when Y = 0
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LDA U1 ; Test unsigned subtraction
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SBC U2
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PHA ; Save the low byte of result on the stack
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LDA #$FF
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SBC #$00 ; result = (65280 + U1) - U2, 65280 = $FF00
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CMP #$FE
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BNE SUB4 ; Branch if result >= 65280 ($FF00) or result < 65024 ($FE00)
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PLA ; Get the low byte of result
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BMI SUB3 ; result < 65280 ($FF00), A >= 128 if result >= 65152 ($FE80)
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SUB2: INX ; Increment X if result < 65152 ($FE80)
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SUB3: RTS
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SUB4: PLA ; Get the low byte of result (does not affect the carry flag)
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BCC SUB2 ; The carry flag is clear if result < 65024 ($FE00)
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BPL SUB5 ; result >= 65280 ($FF00), A <= 127 if result <= 65407 ($FF7F)
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INX ; Increment X if result > 65407 ($FF7F)
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SUB5: RTS
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.data
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ERROR: .byte 0
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S1: .byte 0
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S2: .byte 0
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U1: .byte 0
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U2: .byte 0
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