464 lines
23 KiB
JavaScript
464 lines
23 KiB
JavaScript
/**
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* @fileoverview Defines PCjs x86 constants.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @version 1.0
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* Created 2012-Sep-05
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*
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* Copyright © 2012-2015 Jeff Parsons <Jeff@pcjs.org>
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*
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* This file is part of PCjs, which is part of the JavaScript Machines Project (aka JSMachines)
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* at <http://jsmachines.net/> and <http://pcjs.org/>.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every source code file of every
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* copy or modified version of this work, and to display that copyright notice on every screen
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* that loads or runs any version of this software (see Computer.sCopyright).
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of the
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* PCjs program for purposes of the GNU General Public License, and the author does not claim
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* any copyright as to their contents.
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*/
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"use strict";
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var X86 = {
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/*
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* CPU model numbers
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*/
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MODEL_8086: 8086,
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MODEL_8088: 8088,
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MODEL_80186: 80186,
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MODEL_80188: 80188,
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MODEL_80286: 80286,
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MODEL_80386: 80386,
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/*
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* This constant is used to mark points in the code where the physical address being returned
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* is invalid and should not be used. TODO: There are still functions that will use an invalid
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* address, which is why we've tried to choose a value that causes the least harm, but ultimately,
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* we must add checks to those functions or throw special JavaScript exceptions to bypass them.
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*
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* This value is also used to indicate non-existent EA address calculations, which are usually
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* detected with "regEA === ADDR_INVALID" and "regEAWrite === ADDR_INVALID" tests. In a 32-bit
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* CPU, -1 (ie, 0xffffffff) could actually be a valid address, so consider changing ADDR_INVALID
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* to NaN or null (which is also why all ADDR_INVALID tests should use strict equality operators).
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*
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* The main reason I'm NOT using NaN or null now is my concern that, by mixing non-numbers
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* (specifically, values outside the range of signed 32-bit integers), performance may suffer.
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*/
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ADDR_INVALID: -1,
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/*
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* Processor Status flag definitions (stored in regPS)
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*/
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PS: {
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CF: 0x0001, // bit 0: Carry flag
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BIT1: 0x0002, // bit 1: reserved, always set
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PF: 0x0004, // bit 2: Parity flag
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BIT3: 0x0008, // bit 3: reserved, always clear
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AF: 0x0010, // bit 4: Auxiliary Carry flag (aka Arithmetic flag)
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BIT5: 0x0020, // bit 5: reserved, always clear
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ZF: 0x0040, // bit 6: Zero flag
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SF: 0x0080, // bit 7: Sign flag
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TF: 0x0100, // bit 8: Trap flag
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IF: 0x0200, // bit 9: Interrupt flag
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DF: 0x0400, // bit 10: Direction flag
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OF: 0x0800, // bit 11: Overflow flag
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IOPL: {
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MASK: 0x3000, // bits 12-13: I/O Privilege Level (always set on 8086/80186, clear on 80286 reset)
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SHIFT: 12
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},
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NT: 0x4000, // bit 14: Nested Task flag (always set on 8086/80186, clear on 80286 reset)
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BIT15: 0x8000 // bit 15: reserved (always set on 8086/80186, clear otherwise)
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},
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CR0: {
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/*
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* Machine Status Word (MSW) bit definitions
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*/
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MSW: {
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PE: 0x0001, // protected-mode enabled
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MP: 0x0002, // monitor processor extension (ie, coprocessor)
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EM: 0x0004, // emulate processor extension
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TS: 0x0008, // task switch indicator
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ON: 0xfff0, // on the 80286, these bits are always on (TODO: Verify)
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MASK: 0xffff // these are the only (MSW) bits that the 80286 can access (within CR0)
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},
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ET: 0x00000010, // coprocessor type (80287 or 80387); always 1 on post-80386 CPUs
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PG: 0x80000000|0 // 0: paging disabled
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},
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SEL: {
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RPL: 0x0003, // requested privilege level (0-3)
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LDT: 0x0004, // table indicator (0: GDT, 1: LDT)
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MASK: 0xfff8 // table index
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},
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DESC: { // Descriptor Table Entry
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LIMIT: { // LIMIT bits 0-15 (or OFFSET if this is an INTERRUPT or TRAP gate)
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OFFSET: 0x0
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},
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BASE: { // BASE bits 0-15 (or SELECTOR if this is a TASK, INTERRUPT or TRAP gate)
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OFFSET: 0x2
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},
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ACC: { // bit definitions for the access word (offset 0x4)
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OFFSET: 0x4,
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BASE1623: 0x00ff, // (not used if this a TASK, INTERRUPT or TRAP gate; bits 0-5 are parm count for CALL gates)
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TYPE: {
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OFFSET: 0x5,
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MASK: 0x1f00,
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SEG: 0x1000,
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NONSEG: 0x0f00,
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/*
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* The following bits apply only when SEG is set
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*/
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CODE: 0x0800, // set for CODE, clear for DATA
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ACCESSED: 0x0100, // set if accessed, clear if not accessed
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READABLE: 0x0200, // CODE: set if readable, clear if exec-only
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WRITABLE: 0x0200, // DATA: set if writable, clear if read-only
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CONFORMING: 0x0400, // CODE: set if conforming, clear if not
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EXPDOWN: 0x0400, // DATA: set if expand-down, clear if not
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/*
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* The following are all the possible (valid) types (well, except for the variations
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* of DATA and CODE where the ACCESSED bit (0x0100) may also be set)
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*/
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TSS: 0x0100,
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LDT: 0x0200,
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TSS_BUSY: 0x0300,
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GATE_CALL: 0x0400,
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GATE_TASK: 0x0500,
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GATE_INT: 0x0600,
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GATE_TRAP: 0x0700,
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DATA_READONLY: 0x1000,
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DATA_WRITABLE: 0x1200,
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DATA_EXPDOWN_READONLY: 0x1400,
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DATA_EXPDOWN_WRITABLE: 0x1600,
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CODE_EXECONLY: 0x1800,
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CODE_READABLE: 0x1a00,
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CODE_CONFORMING: 0x1c00,
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CODE_CONFORMING_READABLE: 0x1e00
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},
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DPL: {
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MASK: 0x6000,
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SHIFT: 13
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},
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PRESENT: 0x8000,
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INVALID: 0 // use X86.DESC.ACC.INVALID for invalid ACC values
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},
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EXT: { // descriptor extension word (reserved on the 80286; "must be zero")
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OFFSET: 0x6,
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LIMIT1619: 0x000f,
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AVAIL: 0x0010, // NOTE: set in various descriptors in OS/2
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/*
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* The BIG bit is known as the D bit for code segments; when set, all addresses and operands
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* in that code segment are assumed to be 32-bit.
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*
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* The BIG bit is known as the B bit for data segments; when set, it indicates: 1) all pushes,
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* pops, calls and returns use ESP instead of SP, and 2) the upper bound of an expand-down segment
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* is 0xffffffff instead of 0xffff.
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*/
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BIG: 0x0040, // clear if default operand/address size is 16-bit, set if 32-bit
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LIMITPAGES: 0x0080, // clear if limit granularity is bytes, set if limit granularity is 4Kb pages
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BASE2431: 0xff00
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},
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INVALID: 0 // use X86.DESC.INVALID for invalid DESC values
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},
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LADDR: { // linear address
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PDE: { // index of page directory entry
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MASK: 0xffc00000|0,
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SHIFT: 20 // (addr & DIR.MASK) >>> DIR.SHIFT yields a page directory offset (ie, index * 4)
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},
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PTE: { // index of page table entry
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MASK: 0x003ff000,
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SHIFT: 10 // (addr & PAGE.MASK) >>> PAGE.SHIFT yields a page table offset (ie, index * 4)
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},
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OFFSET: 0x00000fff
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},
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PTE: {
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FRAME: 0xfffff000|0,
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DIRTY: 0x00000040, // page has been modified
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ACCESSED: 0x00000020, // page has been accessed
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USER: 0x00000004, // set for user level (CPL 3), clear for supervisor level (CPL 0-2)
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READWRITE: 0x00000002, // set for read/write, clear for read-only (affects CPL 3 only)
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PRESENT: 0x00000001 // set for present page, clear for not-present page
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},
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TSS: {
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PREV_TSS: 0x00,
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CPL0_SP: 0x02, // start of values altered by task switches
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CPL0_SS: 0x04,
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CPL1_SP: 0x06,
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CPL1_SS: 0x08,
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CPL2_SP: 0x0a,
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CPL2_SS: 0x0c,
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TASK_IP: 0x0e,
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TASK_PS: 0x10,
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TASK_AX: 0x12,
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TASK_CX: 0x14,
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TASK_DX: 0x16,
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TASK_BX: 0x18,
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TASK_SP: 0x1a,
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TASK_BP: 0x1c,
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TASK_SI: 0x1e,
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TASK_DI: 0x20,
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TASK_ES: 0x22,
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TASK_CS: 0x24,
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TASK_SS: 0x26,
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TASK_DS: 0x28, // end of values altered by task switches
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TASK_LDT: 0x2a
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},
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/*
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* Processor Exception Interrupts
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*
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* Of the following exceptions, all are designed to be restartable, except for 0x08 and 0x09 (and 0x0D
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* after an attempt to write to a read-only segment).
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*
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* Error codes are pushed onto the stack for 0x08 (always 0) and 0x0A through 0x0D.
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*
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* Priority: Instruction exception, TRAP, NMI, Processor Extension Segment Overrun, and finally INTR.
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*
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* All exceptions can also occur in real-mode, except where noted. A GP_FAULT in real-mode can be triggered
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* by "any memory reference instruction that attempts to reference [a] 16-bit word at offset 0FFFFH".
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*
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* Interrupts beyond 0x10 (up through 0x1F) are reserved for future exceptions.
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*
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* Implementation Detail: For any opcode we know must generate a UD_FAULT interrupt, we invoke opInvalid(),
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* NOT opUndefined(). UD_FAULT is for INVALID opcodes, Intel's choice of "UD" notwithstanding.
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*
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* We reserve the term "undefined" for opcodes that require more investigation, and we invoke opUndefined()
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* ONLY until an opcode's behavior has finally been defined, at which point it becomes either valid or invalid.
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* The term "illegal" seems completely superfluous; we don't need a third way of describing invalid opcodes.
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*
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* The term "undocumented" should be limited to operations that are valid but Intel simply never documented.
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*/
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EXCEPTION: {
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DIV_ERR: 0x00, // Divide Error Interrupt
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TRAP: 0x01, // Single Step (aka Trap) Interrupt
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NMI: 0x02, // Non-Maskable Interrupt
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BREAKPOINT: 0x03, // Breakpoint Interrupt
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OVERFLOW: 0x04, // INTO Overflow Interrupt (FYI, return address does NOT point to offending instruction)
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BOUND_ERR: 0x05, // BOUND Error Interrupt
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UD_FAULT: 0x06, // Invalid (aka Undefined or Illegal) Opcode (see implementation detail above)
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NM_FAULT: 0x07, // No Math Unit Available (see ESC or WAIT)
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DF_FAULT: 0x08, // Double Fault (see LIDT)
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MP_FAULT: 0x09, // Math Unit Protection Fault (see ESC)
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TS_FAULT: 0x0A, // Invalid Task State Segment Fault (protected-mode only)
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NP_FAULT: 0x0B, // Not Present Fault (protected-mode only)
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SS_FAULT: 0x0C, // Stack Fault (protected-mode only)
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GP_FAULT: 0x0D, // General Protection Fault
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PG_FAULT: 0x0E, // Page Fault
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MF_FAULT: 0x10 // Math Fault (see ESC or WAIT)
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},
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ERRCODE: {
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EXT: 0x0001,
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IDT: 0x0002,
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LDT: 0x0004,
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MASK: 0xfff8 // index of corresponding entry in GDT, LDT or IDT
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},
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RESULT: {
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/*
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* Flags were originally computed using 16-bit result registers:
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*
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* CF: resultZeroCarry & resultSize (ie, 0x100 or 0x10000)
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* PF: resultParitySign & 0xff
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* AF: (resultParitySign ^ resultAuxOverflow) & 0x0010
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* ZF: resultZeroCarry & (resultSize - 1)
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* SF: resultParitySign & (resultSize >> 1)
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* OF: (resultParitySign ^ resultAuxOverflow ^ (resultParitySign >> 1)) & (resultSize >> 1)
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*
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* I386 support requires that we now rely on 32-bit result registers:
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*
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* resultDst, resultSrc, resultArith, resultLogic and resultType
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*
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* and flags are now computed as follows:
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*
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* CF: ((resultDst ^ ((resultDst ^ resultSrc) & (resultSrc ^ resultArith))) & resultType)
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* PF: (resultLogic & 0xff)
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* AF: ((resultArith ^ (resultDst ^ resultSrc)) & 0x0010)
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* ZF: (resultLogic & ((resultType - 1) | resultType))
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* SF: (resultLogic & resultType)
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* OF: (((resultDst ^ resultArith) & (resultSrc ^ resultArith)) & resultType)
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*
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* where resultType contains both a size, which must be one of BYTE (0x80), WORD (0x8000),
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* or DWORD (0x80000000), along with bits for each of the arithmetic and/or logical flags that
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* are currently "cached" in the result registers (eg, X86.RESULT.CF for carry, X86.RESULT.OF
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* for overflow, etc).
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*
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* WARNING: Do not confuse these RESULT flag definitions with the PS flag definitions. RESULT
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* flags are used only as "cached" flag indicators, packed into bits 0-5 of resultType; they do
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* not match the actual flag bit definitions within the Processor Status (PS) register.
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*
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* Arithmetic operations should call:
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*
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* setArithResult(dst, src, value, type)
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* eg:
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* setArithResult(dst, src, dst+src, X86.RESULT.BYTE | X86.RESULT.ALL)
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*
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* and logical operations should call:
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*
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* setLogicResult(value, type [, carry [, overflow]])
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*
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* Since most logical operations clear both CF and OF, most calls to setLogicResult() can omit the
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* last two optional parameters.
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*
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* The type parameter of these methods indicates both the size of the result (BYTE, WORD or DWORD)
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* and which of the flags should now be considered "cached" by the result registers. If the previous
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* resultType specifies any flags not present in the new type parameter, then those flags are
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* calculated and written to the appropriate regPS bit(s) *before* the result registers are updated.
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*
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* Arithmetic operations are assumed to represent an "added" result; if a "subtracted" result is
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* provided instead (eg, from CMP, DEC, SUB, etc), then setArithResult() must include a 5th parameter
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* (fSubtract); eg:
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*
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* setArithResult(dst, src, dst-src, X86.RESULT.BYTE | X86.RESULT.ALL, true)
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*
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* TODO: Consider separating setArithResult() into two functions: setAddResult() and setSubResult().
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*/
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BYTE: 0x80, // result is byte value
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WORD: 0x8000, // result is word value
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DWORD: 0x80000000|0,
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TYPE: 0x80008080|0,
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CF: 0x01, // carry flag is cached
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PF: 0x02, // parity flag is cached
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AF: 0x04, // aux carry flag is cached
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ZF: 0x08, // zero flag is cached
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SF: 0x10, // sign flag is cached
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OF: 0x20, // overflow flag is cached
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ALL: 0x3F, // all result flags are cached
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LOGIC: 0x1A, // all logical flags are cached; see setLogicResult()
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NOTCF: 0x3E // all result flags EXCEPT carry are cached
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},
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/*
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* Bit values for opFlags, which are all reset to zero prior to each instruction
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*/
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OPFLAG: {
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NOREAD: 0x0001,
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NOWRITE: 0x0002,
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NOINTR: 0x0004, // indicates a segreg has been set, or a prefix, or an STI (delay INTR acknowledgement)
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SEG: 0x0010, // segment override
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LOCK: 0x0020, // lock prefix
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REPZ: 0x0040, // repeat while Z (NOTE: this value MUST match PS.ZF; see opCMPSb/opCMPSw/opSCASb/opSCASw)
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REPNZ: 0x0080, // repeat while NZ
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REPEAT: 0x0100, // indicates that an instruction is being repeated (ie, some iteration AFTER the first)
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PUSHSP: 0x0200, // the SP register is potentially being referenced by a PUSH SP opcode, adjustment may be required
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DATASIZE: 0x1000, // data size override
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ADDRSIZE: 0x2000 // address size override
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},
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/*
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* Bit values for intFlags
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*/
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INTFLAG: {
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NONE: 0x00,
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INTR: 0x01, // h/w interrupt requested
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TRAP: 0x02, // trap (INT 0x01) requested
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HALT: 0x04, // halt (HLT) requested
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DMA: 0x08 // async DMA operation in progress
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},
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/*
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* Common opcodes (and/or any opcodes we need to refer to explicitly)
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*/
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OPCODE: {
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ES: 0x26, // opES()
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CS: 0x2E, // opCS()
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SS: 0x36, // opSS()
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DS: 0x3E, // opDS()
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PUSHSP: 0x54, // opPUSHSP()
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PUSHA: 0x60, // opPUHSA() (80186 and up)
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POPA: 0x61, // opPOPA() (80186 and up)
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BOUND: 0x62, // opBOUND() (80186 and up)
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ARPL: 0x63, // opARPL() (80286 and up)
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FS: 0x64, // opFS() (80386 and up)
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GS: 0x65, // opGS() (80386 and up)
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OS: 0x66, // opOS() (80386 and up)
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AS: 0x67, // opAS() (80386 and up)
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PUSHN: 0x68, // opPUSHn() (80186 and up)
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IMULN: 0x69, // opIMULn() (80186 and up)
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PUSH8: 0x6A, // opPUSH8() (80186 and up)
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IMUL8: 0x6B, // opIMUL8() (80186 and up)
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INSB: 0x6C, // opINSb() (80186 and up)
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INSW: 0x6D, // opINSw() (80186 and up)
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OUTSB: 0x6E, // opOUTSb() (80186 and up)
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OUTSW: 0x6F, // opOUTSw() (80186 and up)
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ENTER: 0xC8, // opENTER() (80186 and up)
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LEAVE: 0xC9, // opLEAVE() (80186 and up)
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CALLF: 0x9A, // opCALLF()
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MOVSB: 0xA4, // opMOVSb()
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MOVSW: 0xA5, // opMOVSw()
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CMPSB: 0xA6, // opCMPSb()
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CMPSW: 0xA7, // opCMPSw()
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STOSB: 0xAA, // opSTOSb()
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STOSW: 0xAB, // opSTOSw()
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LODSB: 0xAC, // opLODSb()
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LODSW: 0xAD, // opLODSw()
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SCASB: 0xAE, // opSCASb()
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SCASW: 0xAF, // opSCASw()
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INT3: 0xCC, // opINT3()
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INTn: 0xCD, // opINTn()
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INTO: 0xCE, // opINTO()
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LOOPNZ: 0xE0, // opLOOPNZ()
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LOOPZ: 0xE1, // opLOOPZ()
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LOOP: 0xE2, // opLOOP()
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CALL: 0xE8, // opCALL()
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JMP: 0xE9, // opJMP() (2-byte displacement)
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JMPF: 0xEA, // opJMPF()
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JMPS: 0xEB, // opJMPs() (1-byte displacement)
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LOCK: 0xF0, // opLOCK()
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REPNZ: 0xF2, // opREPNZ()
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REPZ: 0xF3, // opREPZ()
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GRP4W: 0xFF,
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CALLW: 0x10FF, // GRP4W: fnCALLw()
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CALLFDW: 0x18FF, // GRP4W: fnCALLFdw()
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CALLMASK: 0x38FF, // mask 2-byte GRP4W opcodes with this before comparing to CALLW or CALLFDW
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UD2: 0x0B0F // UD2 (invalid opcode "guaranteed" to generate UD_FAULT on all post-8086 processors)
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}
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};
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/*
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* BACKTRACK-related definitions (used only if BACKTRACK is defined)
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*/
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X86.BACKTRACK = {
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SP_LO: 0,
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SP_HI: 0
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};
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/*
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* These PS flags are always stored directly in regPS for the 8086/8088, hence the
|
|
* "direct" designation; other processors must adjust these bits accordingly. The final
|
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* adjusted value is stored in PS_DIRECT.
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*/
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X86.PS_DIRECT_8086 = (X86.PS.TF | X86.PS.IF | X86.PS.DF);
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|
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/*
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* These are the default "always set" PS bits for the 8086/8088; other processors must
|
|
* adjust these bits accordingly. The final adjusted value is stored in PS_SET.
|
|
*/
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X86.PS_SET_8086 = (X86.PS.BIT1 | X86.PS.IOPL.MASK | X86.PS.NT | X86.PS.BIT15);
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|
|
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/*
|
|
* These PS arithmetic and logical flags may be "cached" across several result registers;
|
|
* whether or not they're currently cached depends on the RESULT bits in resultType.
|
|
*/
|
|
X86.PS_CACHED = (X86.PS.CF | X86.PS.PF | X86.PS.AF | X86.PS.ZF | X86.PS.SF | X86.PS.OF);
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|
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/*
|
|
* PS_SAHF is a subset of the arithmetic flags, and refers only to those flags that the
|
|
* SAHF and LAHF "8080 legacy" opcodes affect.
|
|
*/
|
|
X86.PS_SAHF = (X86.PS.CF | X86.PS.PF | X86.PS.AF | X86.PS.ZF | X86.PS.SF);
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|
|
|
/*
|
|
* Before we zero opFlags, we first see if any of the following PREFIX bits were set. If any were set,
|
|
* they are OR'ed into opPrefixes; otherwise, opPrefixes is zeroed as well. This gives prefix-conscious
|
|
* instructions like LODS, MOVS, STOS, CMPS, etc, a way of determining which prefixes, if any, immediately
|
|
* preceded them.
|
|
*/
|
|
X86.OPFLAG_PREFIXES = (X86.OPFLAG.SEG | X86.OPFLAG.LOCK | X86.OPFLAG.REPZ | X86.OPFLAG.REPNZ | X86.OPFLAG.DATASIZE | X86.OPFLAG.ADDRSIZE);
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|
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if (typeof module !== 'undefined') module.exports = X86;
|