603 lines
32 KiB
JavaScript
603 lines
32 KiB
JavaScript
/**
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* @fileoverview PDP11-specific compile-time definitions.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @copyright © Jeff Parsons 2012-2016
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*
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* This file is part of PCjs, a computer emulation software project at <http://pcjs.org/>.
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*
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* It has been adapted from the JavaScript PDP 11/70 Emulator v1.4 written by Paul Nankervis
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* (paulnank@hotmail.com) as of September 2016 at <http://skn.noip.me/pdp11/pdp11.html>. This code
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* may be used freely provided the original authors are acknowledged in any modified source code.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every modified copy of this work
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* and to display that copyright notice when the software starts running; see COPYRIGHT in
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* <http://pcjs.org/modules/shared/lib/defines.js>.
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of PCjs
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* for purposes of the GNU General Public License, and the author does not claim any copyright
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* as to their contents.
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*/
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"use strict";
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/**
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* @define {string}
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*/
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var APPCLASS = "pdp11"; // this @define is the default application class (eg, "pcx86", "c1pjs")
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/**
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* APPNAME is used more for display purposes than anything else now. APPCLASS is what matters in terms
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* of folder and file names, CSS styles, etc.
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*
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* @define {string}
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*/
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var APPNAME = "PDPjs"; // this @define is the default application name (eg, "PCx86", "C1Pjs")
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/**
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* WARNING: DEBUGGER needs to accurately reflect whether or not the Debugger component is (or will be) loaded.
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* In the compiled case, we rely on the Closure Compiler to override DEBUGGER as appropriate. When it's *false*,
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* nearly all of debugger.js will be conditionally removed by the compiler, reducing it to little more than a
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* "type skeleton", which also solves some type-related warnings we would otherwise have if we tried to remove
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* debugger.js from the compilation process altogether.
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*
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* However, when we're in "development mode" and running uncompiled code in debugger-less configurations,
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* I would like to skip loading debugger.js altogether. When doing that, we must ALSO arrange for an additional file
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* (nodebugger.js) to be loaded immediately after this file, which *explicitly* overrides DEBUGGER with *false*.
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*
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* @define {boolean}
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*/
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var DEBUGGER = true; // this @define is overridden by the Closure Compiler to remove Debugger-related support
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/**
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* BYTEARRAYS is a Closure Compiler compile-time option that allocates an Array of numbers for every Memory block,
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* where each a number represents ONE byte; very wasteful, but potentially slightly faster.
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*
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* See the Memory component for details.
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*
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* @define {boolean}
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*/
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var BYTEARRAYS = false;
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/**
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* TYPEDARRAYS enables use of typed arrays for Memory blocks. This used to be a compile-time-only option, but I've
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* added Memory access functions for typed arrays (see MemoryPDP11.afnTypedArray), so support can be enabled dynamically now.
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*
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* See the Memory component for details.
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*/
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var TYPEDARRAYS = (typeof ArrayBuffer !== 'undefined');
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/**
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* MEMFAULT forces the Memory interfaces to signal a CPU fault when a word is accessed using an odd (unaligned) address.
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*
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* Since PDPjs inherited its Bus component from PCx86, it included support for both aligned and unaligned word accesses
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* by default. However, the PDP-11 adds a wrinkle: when an odd address is used to access a memory word, a BUS_ERROR trap
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* must be generated. Note that odd IOPAGE word accesses are fine; this only affects the Memory component.
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*
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* When the MMU is enabled, these checks may also be performed at a higher level, eliminating the need for them at the
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* physical memory level.
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*/
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var MEMFAULT = true;
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/**
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* WORDBUS turns off support for unaligned memory words. Whereas MEMFAULT necessarily slows down memory word accesses
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* slightly, WORDBUS is able to speed them up slightly, by assuming that all word accesses (which didn't fault) must be
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* aligned. This affects all word accesses, even IOPAGE accesses, because it also eliminates cross-block boundary checks.
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*
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* Don't worry that the source code looks MORE complicated rather than LESS with the additional MEMFAULT and WORDBUS checks,
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* because the Closure Compiler eliminates those checks and throws away the (unreachable) code blocks that deal with unaligned
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* accesses.
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*/
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var WORDBUS = true;
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/*
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* Combine all the shared globals and machine-specific globals into one machine-specific global object,
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* which all machine components should start using; eg: "if (PDP11.DEBUG) ..." instead of "if (DEBUG) ...".
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*/
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var PDP11 = {
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APPCLASS: APPCLASS,
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APPNAME: APPNAME,
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APPVERSION: APPVERSION, // shared
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BYTEARRAYS: BYTEARRAYS,
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COMPILED: COMPILED, // shared
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CSSCLASS: CSSCLASS, // shared
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DEBUG: DEBUG, // shared
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DEBUGGER: DEBUGGER,
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MAXDEBUG: MAXDEBUG, // shared
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PRIVATE: PRIVATE, // shared
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TYPEDARRAYS:TYPEDARRAYS,
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MEMFAULT: MEMFAULT,
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WORDBUS: WORDBUS,
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SITEHOST: SITEHOST, // shared
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XMLVERSION: XMLVERSION, // shared
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/*
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* CPU model numbers (supported)
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*/
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MODEL_1120: 1120,
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MODEL_1145: 1145,
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MODEL_1170: 1170,
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/*
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* This constant is used to mark points in the code where the physical address being returned
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* is invalid and should not be used.
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*
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* In a 32-bit CPU, -1 (ie, 0xffffffff) could actually be a valid address, so consider changing
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* ADDR_INVALID to NaN or null (which is also why all ADDR_INVALID tests should use strict equality
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* operators).
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*
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* The main reason I'm NOT using NaN or null now is my concern that, by mixing non-numbers
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* (specifically, values outside the range of signed 32-bit integers), performance may suffer.
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*
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* WARNING: Like many of the properties defined here, ADDR_INVALID is a common constant, which the
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* Closure Compiler will happily inline (with or without @const annotations; in fact, I've yet to
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* see a @const annotation EVER improve automatic inlining). However, if you don't make ABSOLUTELY
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* certain that this file is included BEFORE the first reference to any of these properties, that
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* automatic inlining will no longer occur.
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*/
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ADDR_INVALID: -1,
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/*
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* Processor modes
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*/
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MODE: {
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KERNEL: 0x0,
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SUPER: 0x1,
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UNUSED: 0x2,
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USER: 0x3,
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MASK: 0x3
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},
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/*
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* Processor Status flag definitions (stored in regPSW)
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*/
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PSW: {
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CF: 0x0001, // bit 0: Carry Flag
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VF: 0x0002, // bit 1: Overflow Flag (aka OF on Intel processors)
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ZF: 0x0004, // bit 2: Zero Flag
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NF: 0x0008, // bit 3: Negative Flag (aka SF -- Sign Flag -- on Intel processors)
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TF: 0x0010, // bit 4: Trap Flag
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PRI: 0x00E0, // bits 5-7: Priority
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UNUSED: 0x0700, // bits 8-10: unused
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/*
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* PSW bits above this point are unused on 11/20-class machines
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*/
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REGSET: 0x0800, // bit 11: Register Set (
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PMODE: 0x3000, // bits 12-13: Prev Mode (see PDP11.MODE)
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CMODE: 0xC000, // bits 14-15: Curr Mode (see PDP11.MODE)
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SHIFT: {
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CF: 0,
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VF: 1,
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ZF: 2,
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NF: 3,
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TF: 4,
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PRI: 5,
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PMODE: 12,
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CMODE: 14
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}
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},
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/*
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* Internal operation state flags
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*/
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OPFLAG: {
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INTQ_SPL: 0x01, // INTQ triggered by SPL
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INTQ: 0x02, // call checkInterrupts()
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WAIT: 0x04, // WAIT operation in progress
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TRAP_TF: 0x10, // aka PDP11.PSW.TF
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TRAP_MMU: 0x20,
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TRAP_SP: 0x40,
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TRAP_MASK: 0x70,
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NO_FLAGS: 0x80, // set whenever the PSW is written directly, requiring all updateXXXFlags() functions to leave flags unchanged
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PRESERVE: 0x07 // OPFLAG bits to preserve prior to the next instruction
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},
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/*
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* Opcode reg (opcode bits 2-0)
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*/
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OPREG: {
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MASK: 0x07
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},
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/*
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* Opcode modes (opcode bits 5-3)
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*/
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OPMODE: {
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REG: 0x00, // REGISTER (register is operand)
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REGD: 0x08, // REGISTER DEFERRED (register is address of operand)
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POSTINC: 0x10, // AUTO-INCREMENT (register is address of operand, register incremented)
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POSTINCD: 0x18, // AUTO-INCREMENT DEFERRED (register is address of address of operand, register incremented)
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PREDEC: 0x20, // AUTO-DECREMENT (register decremented, register is address of operand)
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PREDECD: 0x28, // AUTO-DECREMENT DEFERRED (register decremented, register is address of address of operand)
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INDEX: 0x30, // INDEX (register + next word is address of operand)
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INDEXD: 0x38, // INDEX DEFERRED (register + next word is address of address of operand)
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MASK: 0x38,
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SHIFT: 3
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},
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DSTMODE: {
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REG: 0x0007,
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MODE: 0x0038,
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MASK: 0x003F,
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SHIFT: 0
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},
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SRCMODE: {
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REG: 0x01C0,
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MODE: 0x0E00,
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MASK: 0x0FC0,
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SHIFT: 6
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},
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REG: {
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SP: 6,
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PC: 7,
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},
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/*
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* PDP-11 trap vectors
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*/
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TRAP: {
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UNDEFINED: 0x00, // 000 (reserved)
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BUS_ERROR: 0x04, // 004 illegal instructions, bus errors, stack limit, illegal internal address, microbreak
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RESERVED: 0x08, // 010 reserved instructions
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BREAKPOINT: 0x0C, // 014 BPT, breakpoint trap (trace)
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IOT: 0x10, // 020 IOT, input/output trap
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POWER_FAIL: 0x14, // 024 power fail
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EMULATOR: 0x18, // 030 EMT, emulator trap
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TRAP: 0x1C, // 034 TRAP instruction
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PIRQ: 0xA0, // 240 PIRQ, program interrupt request
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MMU_FAULT: 0xA8 // 250 MMU aborts and traps
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},
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/*
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* PDP-11 trap reasons (for diagnostic purposes only)
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*/
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REASON: {
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BPT: 1,
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EMT: 2,
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HALT: 3,
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IOT: 4,
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TRAP: 5,
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RESERVED: 6,
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ODDMEMADDR: 10,
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NOMEMORY: 12,
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ODDMMUADDR: 14,
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MAPERROR: 16,
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PUSHERROR: 18,
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NOREGADDR: 20,
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STACKMODE1: 22,
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STACKERROR: 24,
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INTERRUPT: 26,
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TRAPMMU: 28,
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TRAPSP: 30,
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TRAPTF: 32
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},
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/*
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* Internal memory access flags
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*/
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ACCESS: {
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WORD: 0x00,
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BYTE: 0x01,
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READ: 0x02,
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WRITE: 0x04,
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UPDATE: 0x06,
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VIRT: 0x08, // getVirtualByMode() leaves bit 17 clear if this is set (otherwise the caller would have to clear it again)
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ISPACE: 0x00000,
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DSPACE: 0x10000 // getVirtualByMode() sets bit 17 in any 16-bit virtual address that refers to D space (as opposed to I space)
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},
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/*
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* Internal flags passed to writeByteByMode(), etc.
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*/
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WRITE: {
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NORMAL: 0x0, // write byte or word normally
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SIGNEXT: 0x1 // sign-extend a byte to a word
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},
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CPUERR: {
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RED: 0x0004, // red zone stack limit
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YELLOW: 0x0008, // yellow zone stack limit
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TIMEOUT: 0x0010, // UNIBUS timeout error
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NOMEMORY: 0x0020, // non-existent memory error
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ODDADDR: 0x0040, // odd word address error (as in non-even, not strange)
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BADHALT: 0x0080 // HALT attempted in USER or SUPER modes
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},
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MMR0: {
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ENABLED: 0x0001, // address relocation enabled
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PAGE_NUM: 0x000E, // page number of last fault
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PAGE_D: 0x0010, // last fault occurred in D space
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PAGE_MODE: 0x0060, // processor mode as of last fault
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COMPLETED: 0x0080, // last instruction completed
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DSTMODE: 0x0100, // only destination mode references will be relocated (for diagnostic use)
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MMU_TRAPS: 0x0200, // enable MMU traps
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UNUSED: 0x0C00,
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TRAP_MMU: 0x1000, // trap: MMU
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ABORT_RO: 0x2000, // abort: read-only
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ABORT_PL: 0x4000, // abort: page length
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ABORT_NR: 0x8000, // abort: non-resident
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ABORT: 0xE000
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},
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MMR1: { // general purpose auto-inc/auto-dec register
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REG1_NUM: 0x0007,
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REG1_DELTA: 0x00F8,
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REG2_NUM: 0x0700,
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REG2_DELTA: 0xF800
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},
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MMR2: { // virtual program counter register
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},
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MMR3: { // mapping register
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USER_D: 0x0001,
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SUPER_D: 0x0002,
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KERNEL_D: 0x0004,
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MMU_22BIT: 0x0010,
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UNIBUS_MAP: 0x0020 // UNIBUS map relocation enabled
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},
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/*
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* Assorted special (UNIBUS) addresses
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*
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* Within the PDP-11/45's 18-bit address space, of the 0x40000 possible addresses (256Kb), the top 0x2000
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* (8Kb) is called the IOPAGE and is reserved for CPU and I/O registers. The IOPAGE spans 0x3E000-0x3FFFF.
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*
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* Within the PDP-11/70's 22-bit address space, of the 0x400000 possible addresses (4Mb), the top 0x20000
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* (256Kb) is mapped to the UNIBUS (not physical memory), and as before, the top 0x2000 (8Kb) of that is
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* mapped to the IOPAGE.
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*
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* To map 18-bit UNIBUS addresses to 22-bit physical addresses, the 11/70 uses a UNIBUS relocation map.
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* It consists of 31 double-word registers that each hold a 22-bit base address. When UNIBUS relocation
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* is enabled, the top 5 bits of an address select one of the 31 mapping registers, and the bottom 13 bits
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* are then added to the contents of the selected mapping register.
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*
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* ES6 ALERT: By using octal constants, this is the first place I'm dipping my toe into ECMAScript 6 waters.
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* If you're loading this raw source code into your browser, then by now (2016) you're almost certainly using
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* an ES6-aware browser. Everyone else should be using code compiled by Google's Closure Compiler, which
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* we configure to produce code that's backward-compatible with ES5 (for example, octal constants are
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* converted to decimal values).
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*
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* For more details: https://github.com/google/closure-compiler/wiki/ECMAScript6
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*/
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UNIBUS: { //16-bit 18-bit 22-bit Hex Description
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SISDR0: 0o172200, // Supervisor I Space Descriptor Register 0
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SISDR1: 0o172202, // Supervisor I Space Descriptor Register 1
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SISDR2: 0o172204, // Supervisor I Space Descriptor Register 2
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SISDR3: 0o172206, // Supervisor I Space Descriptor Register 3
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SISDR4: 0o172210, // Supervisor I Space Descriptor Register 4
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SISDR5: 0o172212, // Supervisor I Space Descriptor Register 5
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SISDR6: 0o172214, // Supervisor I Space Descriptor Register 6
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SISDR7: 0o172216, // Supervisor I Space Descriptor Register 7
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SDSDR0: 0o172220, // Supervisor D Space Descriptor Register 0
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SDSDR1: 0o172222, // Supervisor D Space Descriptor Register 1
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SDSDR2: 0o172224, // Supervisor D Space Descriptor Register 2
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SDSDR3: 0o172226, // Supervisor D Space Descriptor Register 3
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SDSDR4: 0o172230, // Supervisor D Space Descriptor Register 4
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SDSDR5: 0o172232, // Supervisor D Space Descriptor Register 5
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SDSDR6: 0o172234, // Supervisor D Space Descriptor Register 6
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SDSDR7: 0o172236, // Supervisor D Space Descriptor Register 7
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SISAR0: 0o172240, // Supervisor I Space Address Register 0
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SISAR1: 0o172242, // Supervisor I Space Address Register 1
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SISAR2: 0o172244, // Supervisor I Space Address Register 2
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SISAR3: 0o172246, // Supervisor I Space Address Register 3
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SISAR4: 0o172250, // Supervisor I Space Address Register 4
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SISAR5: 0o172252, // Supervisor I Space Address Register 5
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SISAR6: 0o172254, // Supervisor I Space Address Register 6
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SISAR7: 0o172256, // Supervisor I Space Address Register 7
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SDSAR0: 0o172260, // Supervisor D Space Address Register 0
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SDSAR1: 0o172262, // Supervisor D Space Address Register 1
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SDSAR2: 0o172264, // Supervisor D Space Address Register 2
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SDSAR3: 0o172266, // Supervisor D Space Address Register 3
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SDSAR4: 0o172270, // Supervisor D Space Address Register 4
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SDSAR5: 0o172272, // Supervisor D Space Address Register 5
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SDSAR6: 0o172274, // Supervisor D Space Address Register 6
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SDSAR7: 0o172276, // Supervisor D Space Address Register 7
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KISDR0: 0o172300, // Kernel I Space Descriptor Register 0
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KISDR1: 0o172302, // Kernel I Space Descriptor Register 1
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KISDR2: 0o172304, // Kernel I Space Descriptor Register 2
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KISDR3: 0o172306, // Kernel I Space Descriptor Register 3
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KISDR4: 0o172310, // Kernel I Space Descriptor Register 4
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KISDR5: 0o172312, // Kernel I Space Descriptor Register 5
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KISDR6: 0o172314, // Kernel I Space Descriptor Register 6
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KISDR7: 0o172316, // Kernel I Space Descriptor Register 7
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KDSDR0: 0o172320, // Kernel D Space Descriptor Register 0
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KDSDR1: 0o172322, // Kernel D Space Descriptor Register 1
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KDSDR2: 0o172324, // Kernel D Space Descriptor Register 2
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KDSDR3: 0o172326, // Kernel D Space Descriptor Register 3
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KDSDR4: 0o172330, // Kernel D Space Descriptor Register 4
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KDSDR5: 0o172332, // Kernel D Space Descriptor Register 5
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KDSDR6: 0o172334, // Kernel D Space Descriptor Register 6
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KDSDR7: 0o172336, // Kernel D Space Descriptor Register 7
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KISAR0: 0o172340, // Kernel I Space Address Register 0
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KISAR1: 0o172342, // Kernel I Space Address Register 1
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KISAR2: 0o172344, // Kernel I Space Address Register 2
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KISAR3: 0o172346, // Kernel I Space Address Register 3
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KISAR4: 0o172350, // Kernel I Space Address Register 4
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KISAR5: 0o172352, // Kernel I Space Address Register 5
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KISAR6: 0o172354, // Kernel I Space Address Register 6
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KISAR7: 0o172356, // Kernel I Space Address Register 7
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KDSAR0: 0o172360, // Kernel D Space Address Register 0
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KDSAR1: 0o172362, // Kernel D Space Address Register 1
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KDSAR2: 0o172364, // Kernel D Space Address Register 2
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KDSAR3: 0o172366, // Kernel D Space Address Register 3
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KDSAR4: 0o172370, // Kernel D Space Address Register 4
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KDSAR5: 0o172372, // Kernel D Space Address Register 5
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KDSAR6: 0o172374, // Kernel D Space Address Register 6
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KDSAR7: 0o172376, // Kernel D Space Address Register 7
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|
|
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MMR3: 0o172516, // 772516 17772516
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|
|
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LKS: 0o177546, // KW11-L Clock Status
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|
|
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PRS: 0o177550, // PC11/PR11 Reader Status Register
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PRB: 0o177552, // PC11/PR11 Reader Buffer Register
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|
|
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RCSR: 0o177560, // Display Terminal: Receiver Status Register
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RBUF: 0o177562, // Display Terminal: Receiver Data Buffer Register
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XCSR: 0o177564, // Display Terminal: Transmitter Status Register
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XBUF: 0o177566, // Display Terminal: Transmitter Data Buffer Register
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|
|
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CNSL: 0o177570, // Console Switch and Front Panel Display
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|
|
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MMR0: 0o177572, // 777572 17777572
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MMR1: 0o177574, // 777574 17777574
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MMR2: 0o177576, // 777576 17777576
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|
|
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UISDR0: 0o177600, // User I Space Descriptor Register 0
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UISDR1: 0o177602, // User I Space Descriptor Register 1
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UISDR2: 0o177604, // User I Space Descriptor Register 2
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UISDR3: 0o177606, // User I Space Descriptor Register 3
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UISDR4: 0o177610, // User I Space Descriptor Register 4
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|
UISDR5: 0o177612, // User I Space Descriptor Register 5
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|
UISDR6: 0o177614, // User I Space Descriptor Register 6
|
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UISDR7: 0o177616, // User I Space Descriptor Register 7
|
|
UDSDR0: 0o177620, // User D Space Descriptor Register 0
|
|
UDSDR1: 0o177622, // User D Space Descriptor Register 1
|
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UDSDR2: 0o177624, // User D Space Descriptor Register 2
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|
UDSDR3: 0o177626, // User D Space Descriptor Register 3
|
|
UDSDR4: 0o177630, // User D Space Descriptor Register 4
|
|
UDSDR5: 0o177632, // User D Space Descriptor Register 5
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|
UDSDR6: 0o177634, // User D Space Descriptor Register 6
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|
UDSDR7: 0o177636, // User D Space Descriptor Register 7
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UISAR0: 0o177640, // User I Space Address Register 0
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UISAR1: 0o177642, // User I Space Address Register 1
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UISAR2: 0o177644, // User I Space Address Register 2
|
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UISAR3: 0o177646, // User I Space Address Register 3
|
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UISAR4: 0o177650, // User I Space Address Register 4
|
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UISAR5: 0o177652, // User I Space Address Register 5
|
|
UISAR6: 0o177654, // User I Space Address Register 6
|
|
UISAR7: 0o177656, // User I Space Address Register 7
|
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UDSAR0: 0o177660, // User D Space Address Register 0
|
|
UDSAR1: 0o177662, // User D Space Address Register 1
|
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UDSAR2: 0o177664, // User D Space Address Register 2
|
|
UDSAR3: 0o177666, // User D Space Address Register 3
|
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UDSAR4: 0o177670, // User D Space Address Register 4
|
|
UDSAR5: 0o177672, // User D Space Address Register 5
|
|
UDSAR6: 0o177674, // User D Space Address Register 6
|
|
UDSAR7: 0o177676, // User D Space Address Register 7
|
|
|
|
R0SET0: 0o177700,
|
|
R1SET0: 0o177701,
|
|
R2SET0: 0o177702,
|
|
R3SET0: 0o177703,
|
|
R4SET0: 0o177704,
|
|
R5SET0: 0o177705,
|
|
R6KERNEL: 0o177706,
|
|
R7KERNEL: 0o177707,
|
|
R0SET1: 0o177710,
|
|
R1SET1: 0o177711,
|
|
R2SET1: 0o177712,
|
|
R3SET1: 0o177713,
|
|
R4SET1: 0o177714,
|
|
R5SET1: 0o177715,
|
|
R6SUPER: 0o177716,
|
|
R6USER: 0o177717,
|
|
|
|
/*
|
|
* This next group of registers is largely ignored; all accesses are routed to regsControl[]
|
|
*/
|
|
LAERR: 0o177740, // Low Address Error (11/70 only)
|
|
HAERR: 0o177742, // High Address Error (11/70 only)
|
|
MEMERR: 0o177744, // Memory System Error (11/70 only)
|
|
CACHEC: 0o177746, // Cache Control (11/70 only)
|
|
MAINT: 0o177750, // Maintenance (11/70 only)
|
|
HITMISS: 0o177752, // Hit/Miss (11/70 only)
|
|
UNDEF1: 0o177754,
|
|
UNDEF2: 0o177756,
|
|
|
|
LSIZE: 0o177760, // Lower Size Register (last 32-word block) (11/70 only)
|
|
HSIZE: 0o177762, // Upper Size Register (always zero) (11/70 only)
|
|
SYSID: 0o177764, // System ID Register (11/70 only)
|
|
CPUERR: 0o177766, // CPU error (11/70 only)
|
|
MB: 0o177770, // Microprogram break (11/70 only)
|
|
PIR: 0o177772, // Program Interrupt Request
|
|
SL: 0o177774, // Stack Limit Register
|
|
PSW: 0o177776 // 777776 17777776 0x3FFFFE Processor Status Word
|
|
},
|
|
PC11: { // High Speed Reader & Punch (PR11 is a Reader-only unit)
|
|
PRS: {
|
|
RE: 0x0001, // Reader Enable (W/O)
|
|
RIE: 0x0040, // Reader Interrupt Enable (allows the DONE and ERROR bits to trigger an interrupt)
|
|
DONE: 0x0080, // Done (R/O)
|
|
BUSY: 0x0800, // Busy (R/O)
|
|
ERROR: 0x8000, // Error (R/O)
|
|
CLEAR: 0x08C0, // bits cleared on INIT
|
|
WMASK: 0x0041 // bits writable
|
|
},
|
|
PRB: {
|
|
MASK: 0x00FF // Data
|
|
}
|
|
},
|
|
DL11: { // Serial Line Interface (program compatible with the KL11 for control of console teleprinters)
|
|
PRI: 4,
|
|
RVEC: 0o60,
|
|
XVEC: 0o64,
|
|
RCSR: { // 177560
|
|
RE: 0x0001, // Reader Enable (W/O) TODO: Determine if we really need to exclude this write-only bit from RMASK
|
|
DTR: 0x0002, // Data Terminal Ready (R/W)
|
|
RTS: 0x0004, // Request To Send (R/W)
|
|
STD: 0x0008, // Secondary Transmitted Data (R/W)
|
|
DIE: 0x0020, // Dataset Interrupt Enable (R/W)
|
|
RIE: 0x0040, // Receiver Interrupt Enable (R/W)
|
|
RD: 0x0080, // Receiver Done (R/O)
|
|
SRD: 0x0400, // Secondary Received Data (R/O)
|
|
RA: 0x0800, // Receiver Active (R/O)
|
|
CD: 0x1000, // Carrier Detect (R/O)
|
|
CTS: 0x2000, // Clear To Send (R/O)
|
|
RI: 0x4000, // Ring Indicator (R/O)
|
|
DSC: 0x8000, // Dataset Status Change (R/O)
|
|
RMASK: 0xFFFF, // read mask
|
|
WMASK: 0x006F // write mask
|
|
},
|
|
RBUF: { // 177562
|
|
DATA: 0x00ff, // Received Data (R/O)
|
|
PARITY: 0x1000, // Received Data Parity (R/O)
|
|
FE: 0x2000, // Framing Error (R/O)
|
|
OE: 0x4000, // Overrun Error (R/O)
|
|
ERROR: 0x8000, // Error (R/O)
|
|
DELAY: 1
|
|
},
|
|
XCSR: { // 177564
|
|
BREAK: 0x0001, // BREAK (R/W)
|
|
MAINT: 0x0004, // Maintenance (R/W)
|
|
TIE: 0x0040, // Transmitter Interrupt Enable (R/W)
|
|
READY: 0x0080, // Transmitter Ready (R/O)
|
|
RMASK: 0x00C5,
|
|
WMASK: 0x0045,
|
|
DELAY: 1
|
|
},
|
|
XBUF: { // 177566
|
|
DATA: 0x00FF, // Transmitted Data (W/O) TODO: Determine why pdp11.js effectively defined this as 0x7F
|
|
DELAY: 1
|
|
}
|
|
},
|
|
KW11: { // KW11-L Line Time Clock
|
|
PRI: 6,
|
|
VEC: 0o100,
|
|
DELAY: 0,
|
|
LKS: {
|
|
IE: 0x0040, // Interrupt Enable
|
|
MON: 0x0080 // Monitor
|
|
}
|
|
}
|
|
};
|
|
|
|
PDP11.ACCESS.READ_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.READ; // formerly READ_MODE (2)
|
|
PDP11.ACCESS.READ_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.READ; // formerly READ_MODE (2) | BYTE_MODE (1)
|
|
PDP11.ACCESS.WRITE_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.WRITE; // formerly WRITE_MODE (4)
|
|
PDP11.ACCESS.WRITE_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.WRITE; // formerly WRITE_MODE (4) | BYTE_MODE (1)
|
|
PDP11.ACCESS.UPDATE_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.UPDATE; // formerly MODIFY_WORD (2 | 4)
|
|
PDP11.ACCESS.UPDATE_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.UPDATE; // formerly MODIFY_BYTE (1 | 2 | 4)
|
|
|
|
/*
|
|
* PSW arithmetic flags are NOT stored directly into the PSW register; they are maintained across separate
|
|
* flag registers.
|
|
*/
|
|
PDP11.PSW.FLAGS = (PDP11.PSW.NF | PDP11.PSW.ZF | PDP11.PSW.VF | PDP11.PSW.CF);
|
|
|
|
if (NODE) {
|
|
global.APPCLASS = APPCLASS;
|
|
global.APPNAME = APPNAME;
|
|
global.DEBUGGER = DEBUGGER;
|
|
global.BYTEARRAYS = BYTEARRAYS;
|
|
global.TYPEDARRAYS = TYPEDARRAYS;
|
|
global.PDP11 = PDP11;
|
|
|
|
module.exports = PDP11;
|
|
}
|