Jeff
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f8bf346eab
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Renamed flags to be more consistent with DEC's names, and updated JSR and JSP to clear the BIS flag
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2017-03-28 16:27:18 -07:00 |
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Jeff
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d5c48df9bc
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Added support for MACRO-10 literal collapsing; it's not super-aggressive, but it's more than adequate for what DEC's diagnostics require
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2017-03-28 15:22:17 -07:00 |
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Jeff
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ae30a5e93c
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PDPjs passes the first four PDP-10 Basic Instruction Diagnostics (finally)
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2017-03-27 19:00:10 -07:00 |
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Jeff
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2a8c2a74d2
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Fixed a couple of PDP-10 opcode emulation bugs (AOBJN, AOBJP, and CMP), and rounded out the set of DEC's basic instruction diagnostics
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2017-03-27 11:44:42 -07:00 |
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Jeff
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9c96ec14ad
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Started executing basic PDP-10 instruction diagnostic #1
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2017-03-17 00:01:49 -07:00 |
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Jeff
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6e0e489bee
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Cleaned up the expression parser, fixed some PDP-10 evaluation errors, and added support unary minus
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2017-03-16 10:30:56 -07:00 |
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Jeff
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9ac0ffe679
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Perform the documented encoding of SIXBIT character data for MACRO-10
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2017-03-12 11:56:15 -07:00 |
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Jeff
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fcee8a2838
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Added support for future PDP-10 MACRO-10 assembler
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2017-03-10 10:28:32 -08:00 |
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Jeff
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3a9cd5cf04
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Code cleanup
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2017-03-09 17:49:54 -08:00 |
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Jeff
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a7b4321f53
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Added all the PDP-10 logical testing/modification instructions
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2017-03-09 15:37:26 -08:00 |
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Jeff
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0dc6b7276b
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Added lots of PDP-10 compare/increment/decrement/skip/jump instructions
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2017-03-09 12:30:51 -08:00 |
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Jeff
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e9d2b0ec25
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Rounded out the rest of the MUL and DIV instructions
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2017-03-08 15:52:33 -08:00 |
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Jeff
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b3982328ed
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Added a couple of doDIV() improvements
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2017-03-08 14:41:55 -08:00 |
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Jeff
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93e35dfa17
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Ported the Int36 72-bit division code to the PDP-10 component
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2017-03-08 11:38:54 -08:00 |
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Jeff
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48792873de
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Eliminate PDP-10 dependencies on the Int36 class (which is now used only for prototyping and command-line testing)
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2017-03-07 17:21:59 -08:00 |
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Jeff
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65eb821710
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Well, apparently the PDP-10 MUL instruction really DOES store the high-order word first, and it only stores the low-order word if the destination is an accumulator (weird)
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2017-03-07 14:09:24 -08:00 |
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Jeff
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7e207db2a1
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Added PDP-10 JSP and JFCL operations (which seem to be the simplest means of getting and setting the processor flags)
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2017-03-07 13:44:43 -08:00 |
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Jeff
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0e18448423
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Added PDP-10 SUB and MUL operations
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2017-03-07 10:21:17 -08:00 |
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Jeff
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38a598d21e
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Added PDP-10 ADD operations
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2017-03-06 23:36:48 -08:00 |
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Jeff
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6b68525f24
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Fixed minor ASHC bug
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2017-03-05 16:19:25 -08:00 |
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Jeff
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286a122b05
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Implemented (but have not yet tested) ASHC opcode for PDP-10
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2017-03-05 14:14:14 -08:00 |
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Jeff
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234e8871ba
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Added "lsh" and "rot" commands to the Int36 command-line tool to mimic the PDP-10 opcodes and test their logic
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2017-03-05 10:04:18 -08:00 |
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Jeff
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ffb7fa1221
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New improved PDP-10 processor flag handling
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2017-03-04 21:07:56 -08:00 |
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Jeff
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87e17a695c
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Fixed opIO() dispatch
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2017-03-04 16:52:44 -08:00 |
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Jeff
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1ac769431f
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Added initial logic for decoding PDP-10 input-output instructions
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2017-03-04 16:47:56 -08:00 |
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Jeff
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e04bec1af4
|
Typo
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2017-03-04 14:46:26 -08:00 |
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Jeff
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5d48383363
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Added logic (untested) for ASH
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2017-03-04 14:43:21 -08:00 |
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Jeff
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20c24053b9
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Simplified ROT and ROTC, converting all right (negative) rotations into left (positive) rotations
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2017-03-04 11:22:57 -08:00 |
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Jeff
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88f66f9590
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Added ROT and ROTC (albeit untested)
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2017-03-03 21:09:45 -08:00 |
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Jeff
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a08c8c30bf
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Added LSH and LSHC (albeit untested)
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2017-03-03 17:44:27 -08:00 |
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Jeff
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b8a38c8ac6
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Finished PDP-10 logical operations
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2017-03-03 15:58:15 -08:00 |
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Jeff
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616f9d4cda
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Started work on PDP-10 logical operations
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2017-03-03 11:30:34 -08:00 |
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Jeff
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796a23ce6c
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Added some "special considerations" to PDP-10 byte pointer processing
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2017-03-03 09:01:49 -08:00 |
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Jeff
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25aa95cec8
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First cut at PDP-10 byte instructions
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2017-03-02 23:10:24 -08:00 |
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Jeff
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affaa1075c
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Finished the PDP-10 Move Magnitude opcodes, along with the Push Down and Pop Up opcodes (uncovering some SIMH weirdness along the way)
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2017-03-02 16:38:00 -08:00 |
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Jeff
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84f8cece67
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All PDP-10 MOVN (Move Negative) opcodes implemented
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2017-03-02 10:19:37 -08:00 |
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Jeff
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202374dd09
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Added the PDP-10's four arithmetic flags along with a negate() function -- the first of our functions that actually needs to set those flags
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2017-03-01 17:23:54 -08:00 |
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Jeff
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e870fd6eec
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Fixed the accumulator update logic in all the PDP-10 half-word self-mode instructions, and started work on EXCH, BLT, and MOVE instructions (the BLT is a real odd-ball, and SIMH does some very strange things with the accumulator used by BLT, which we do NOT attempt to replicate; the strangeness is most noticeable when the accumulator is part of the range being transferred)
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2017-03-01 16:00:48 -08:00 |
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Jeff
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3508b1050e
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Started work on v1.34.2: More PDP-10 opcode handlers
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2017-03-01 12:26:57 -08:00 |
|
Jeff Parsons
|
cafd7c493c
|
Finished writing all the half-word move permutations, now it's time to test them all (ugh)
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2017-02-28 11:02:15 -08:00 |
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Jeff Parsons
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d7b8122a40
|
All HLL and HRL permutations implemented now (up next: HRR and HLR)
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2017-02-28 10:24:29 -08:00 |
|
Jeff Parsons
|
17e807ecb6
|
Tested a couple half-word instructions (so far, so good)
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2017-02-27 12:25:13 -08:00 |
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Jeff Parsons
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0255b7b891
|
Implemented all four primary half-word moves (HLL, HLR, HRL, HRR) but none of the flavors (Z, O, E); need to test the primary instructions first
|
2017-02-27 09:50:28 -08:00 |
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Jeff Parsons
|
6cf141baf9
|
getOpcode() can now handle infinite indirections without starving the emulator
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2017-02-26 12:17:21 -08:00 |
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Jeff Parsons
|
ed4c031035
|
Implemented my first 4 PDP-10 opcodes (HLL, HLLI, HLLM, HLLS)
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2017-02-26 10:51:49 -08:00 |
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Jeff Parsons
|
0451774bc6
|
Added preliminary PDP-10 opcode decoding
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2017-02-26 09:25:44 -08:00 |
|
Jeff Parsons
|
e3ab5b1ed5
|
Added preliminary PDP-10 opcode decoding
|
2017-02-26 09:13:16 -08:00 |
|
Jeff Parsons
|
3e30bde786
|
Some PDP-10 disassembler clean-up
|
2017-02-25 21:19:41 -08:00 |
|
Jeff Parsons
|
cb4d054ead
|
Added preliminary first-order opcode dispatch table
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2017-02-25 16:21:21 -08:00 |
|
Jeff Parsons
|
b628219f5c
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Used the new PDP-10 disassembler in test mode to help generate the cpuops.js skeleton
|
2017-02-25 13:28:47 -08:00 |
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