Jeff
|
e870fd6eec
|
Fixed the accumulator update logic in all the PDP-10 half-word self-mode instructions, and started work on EXCH, BLT, and MOVE instructions (the BLT is a real odd-ball, and SIMH does some very strange things with the accumulator used by BLT, which we do NOT attempt to replicate; the strangeness is most noticeable when the accumulator is part of the range being transferred)
|
2017-03-01 16:00:48 -08:00 |
|
Jeff
|
3508b1050e
|
Started work on v1.34.2: More PDP-10 opcode handlers
|
2017-03-01 12:26:57 -08:00 |
|
Jeff Parsons
|
cafd7c493c
|
Finished writing all the half-word move permutations, now it's time to test them all (ugh)
|
2017-02-28 11:02:15 -08:00 |
|
Jeff Parsons
|
d7b8122a40
|
All HLL and HRL permutations implemented now (up next: HRR and HLR)
|
2017-02-28 10:24:29 -08:00 |
|
Jeff Parsons
|
17e807ecb6
|
Tested a couple half-word instructions (so far, so good)
|
2017-02-27 12:25:13 -08:00 |
|
Jeff Parsons
|
0255b7b891
|
Implemented all four primary half-word moves (HLL, HLR, HRL, HRR) but none of the flavors (Z, O, E); need to test the primary instructions first
|
2017-02-27 09:50:28 -08:00 |
|
Jeff Parsons
|
6cf141baf9
|
getOpcode() can now handle infinite indirections without starving the emulator
|
2017-02-26 12:17:21 -08:00 |
|
Jeff Parsons
|
ed4c031035
|
Implemented my first 4 PDP-10 opcodes (HLL, HLLI, HLLM, HLLS)
|
2017-02-26 10:51:49 -08:00 |
|
Jeff Parsons
|
0451774bc6
|
Added preliminary PDP-10 opcode decoding
|
2017-02-26 09:25:44 -08:00 |
|
Jeff Parsons
|
e3ab5b1ed5
|
Added preliminary PDP-10 opcode decoding
|
2017-02-26 09:13:16 -08:00 |
|
Jeff Parsons
|
3e30bde786
|
Some PDP-10 disassembler clean-up
|
2017-02-25 21:19:41 -08:00 |
|
Jeff Parsons
|
cb4d054ead
|
Added preliminary first-order opcode dispatch table
|
2017-02-25 16:21:21 -08:00 |
|
Jeff Parsons
|
b628219f5c
|
Used the new PDP-10 disassembler in test mode to help generate the cpuops.js skeleton
|
2017-02-25 13:28:47 -08:00 |
|